JPS6221264A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a well by using a mask once so that the depth can be controlled, by providing a process, by which ions are implanted with sufficiently high energy so as to penetrate a blocking film, and providing a process, by which ions having the reverse conducting type with respect to said implanted ions are implanted with low energy. CONSTITUTION:A thin silicon oxide film 2 is grown on the surface of a P-type silicon substrate 1. Selecting etching is performed, and an ion implantation blocking region is formed. Then, boron is implanted with high acceleration energy. Phosphorus is implanted with acceleration energy lower than said high energy. When appropriate heat treatment is performed, a P-type region 3 and an N-type region 4 are formed. When the P-type region 3 is formed, a P-type region 3a beneath the silicon oxide film 2 is positioned close to the surface. A P-type region 3b beneath the N-type region 4 is positioned at a place, which is remotely separated from the surface, by forming the N-type region 4 precisely. The difference in positions of 3a and 3b in the depth direction can be determined by the thickness of the silicon oxide film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, particularly an OMO5.

Prior Art Conventional n-type well and p-type well structures acMO of this type
The manufacturing method of No. 3 is shown in FIG. The manufacturing method will be briefly described using FIG. A protective oxide film 5 and a nitrite film 6 are formed on the surface of a P-type silicon substrate 21, and the nitride film 6 and protective oxide film 6 are selectively removed to form a removed region 23.
N-type impurities are implanted only in (Fig. 2(&)). Then, after performing selective oxidation to form a thick thermal oxide film 7,
The nitride film 6 is removed, and P-type impurities are implanted only into the removed region 24 (FIG. 2(b)). After that, appropriate heat treatment is applied to remove the thermal oxide film 7, as shown in FIG.
As shown in c), both n-type and p-type wells were formed.

Problems to be Solved by the Invention This conventional configuration has a problem in that the process is more complicated than that of the single-well (n-type or p-type well) structure CMO8.

In view of these problems, the present invention provides a double-well structure CMO.
This invention provides a method for manufacturing a semiconductor device that can be manufactured by self-alignment without increasing the number of steps much compared to the single-well structure CMO8.

Means for Solving the Problem In order to solve this problem, the method for manufacturing a semiconductor device of the present invention provides that when forming either an n-type or p-type well, the well region to be formed is The method consists of forming an ion implantation blocking region on top of the ion implantation layer, performing ion implantation with high energy, and then implanting ions of the opposite conductivity type with low energy.

Effect With this configuration, ions implanted with high energy are present at the surface of the substrate in the ion implantation blocking region, and are present at a considerable depth from the surface in areas other than the blocking region. and,
Ions implanted with low energy exist on the surface other than the ion implantation blocking region. Since the ions implanted with high energy and the ions implanted with low energy are of opposite conductivity type, both wells are formed in a self-aligned manner.

Embodiment FIG. 1 shows a double well structure CMO8 according to an embodiment of the present invention.
1 is a schematic cross-sectional view when forming a well. In FIG. 1, 1 is a P-type silicon substrate, 2 is a silicon oxide film, and 3 is a P-type silicon substrate.
The shadow area, 4, is the N shadow area.

A method for manufacturing the structure shown in FIG. 1 will be briefly described below.

First, a silicon oxide film 2 having a thickness of 2 μm is grown on the surface of a P-type silicon substrate 1, and selectively etched to form an ion implantation blocking region. Next, boron is implanted with an acceleration energy of 2MelV, and phosphorus is implanted with an acceleration energy of 200V.

Thereafter, by applying appropriate heat treatment, a P shadow region 3 and an N shadow region 4 are formed. Here, the order of the high energy implantation step and the low energy implantation step does not matter.

That is, what is important in the present invention is the relationship between the ion implantation blocking ability of the ion implantation blocking region and the acceleration energy of high-energy implantation. Generally, once the material of the ion implantation blocking region is determined, the ion implantation blocking ability depends on its film thickness.

In this embodiment, when forming the P shadow region 3, the P shadow region 3 below the silicon oxide film 2! L is located near the surface,
The P shadow area 3b below the N shadow area 4 needs to be located away from the surface in order to accurately form the N shadow area 4. Therefore, the positional difference between 3a and 3b in the depth direction is
It is determined only by the thickness of silicon oxide film 2.

This depends on the requirements of the device characteristics.

It is shown that the thickness of the well can be freely controlled by changing the acceleration energy of the silicon oxide film 2 and the high-energy implantation. Here, the material of the ion implantation blocking region is a silicon oxide film, but it goes without saying that other materials, such as photoresist, or a multilayer film of these materials may also be used.

In this embodiment, the high-energy implanted ions were boron and the low-energy implanted ions were phosphorus, but it is also possible to form both wells with the reverse combination.

Furthermore, although a P-type silicon substrate was used as the starting material, it goes without saying that similar effects can be obtained using an N-type silicon substrate.

Effects of the Invention As described above, the present invention has practical advantages such as well formation for both wells CMO3 using a single mask by using high-energy implantation, and easy control of the well depth direction. The effects are huge.

[Brief explanation of the drawing]

FIG. 1 shows a double-well structure CMO in one embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view when forming well No. 8, and FIG. 2 is a diagram showing the manufacturing process of a conventional double-well structure CMO5. 1.21...P-type silicon substrate, 2...
・Silicon oxide film, 3, 23...P shadow area, 4
, 24...N shadow area, 5...Protective oxide film, 6...Nitride film, 7...Thermal oxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person11
iii1 ℃nu

Claims (1)

[Claims] A step of selectively forming an ion implantation blocking film on the main surface of a semiconductor substrate of one conductivity type, a step of implanting ions with energy high enough to penetrate the blocking film, and a step of implanting ions of the opposite conductivity type to the implanted ions. A method for manufacturing a semiconductor device, comprising a step of implanting with low energy.