JPS63126279A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enlarge the junction depth of a writing circuit part and increase surface breakdown voltage and junction breakdown strength, by introducing a second conductivity type impurity in a part where the drain regions of a low voltage circuit part and a high voltage circuit part are formed. CONSTITUTION:The respective diffusion regions 21 and 22 of a reading circuit part 5 are made shallow, and As is used as diffusion impurity. On the other hand, the respective diffusion regions 17 and 18 of a writing circuit part 4 are made rather deep, and constituted of an As diffusion layer and a P diffusion layer. Therefor a shallow P-N junction 25 is formed between the diffusion regions 21 and 22 of readout side and the substrate 1, and there the impurity concentration profile is made sharp. However, a rather deep P-H junction 26 is formed between the diffusion regions 17 and 18 of writing side and the substrate 1, and the impurity concentration in the direction of depth is gradually varied, which forms a graded junction.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device, for example, an EP RO
M (Electrically Programmable)
The present invention relates to a method for manufacturing an integrated circuit device that operates at high speed and at a high voltage, such as a BLE (ReadOnly Memory).

MOs that make up each circuit section for high integration and high speed
When the diffusion depth or junction depth of the source and drain/region of SFET is shallow, As may be used as a diffusion impurity. In circuits, although a shallow junction depth is advantageous for readout circuits, it is undesirable for embedded circuits.In other words, source and drain regions formed by As diffusion have shallow junction depths and Since the impurity a degree profile of F is steep,
The optical surface breakdown voltage and junction breakdown voltage of the ET will decrease. Since the write voltage applied to the write circuit section is, for example, 25 V, which is much higher than the read voltage (for example, 5 V), the above-mentioned breakdown is likely to occur.

In order to prevent surface breakdown, it is conceivable to make the gate oxide film very thick, for example, about 1500 Å.

However, when the film thickness is increased in this way, undesirable problems such as an increase in the threshold voltage (*th) and a decrease in gm occur.

SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device in which the read circuit section can be highly integrated and operate at high speed, and at the same time, the withstand voltage of the write circuit section can be increased. It is something to do.

Hereinafter, an embodiment in which the present invention is applied to an EFROM will be described in detail with reference to the drawings.

According to the ROMIC shown in FIG.
The shield 5101g%2 and the P+ type channel stopper 16 below it allow the memory cell portion 3. Write circuit section 4. They are separated into R output circuit sections 5, respectively. The memory cell section 3 has a well-known MO8FET structure,
Each gate is constituted by a polysilicon floating gate 6 and a control gate 7, and N+ diffusion regions 8 and 9, which serve as source or drain regions, are formed between these gates. 10 a, 10 b,
Reference numeral 10c denotes a gate oxide film, which is continuous with the surface oxide film 11 of polysilicon gates 6 and 7. Gate oxide films 10a and 10c both have a thickness of 500 Å, but gate oxide film 10b is relatively thick at 100 OA.

12 is a phosphosilicate glass film, and 13 is an aluminum bit line. The write circuit section 4 and the bladder outlet circuit section 5 each have polysilicon gates 14 and 15'i deposited in the same process as the 70-ring gate. These gates 14 and 15 have the same thickness and are formed thin. Aluminum electrodes 19.20 are deposited on the N-type diffusion regions 17.18 that will become the source or drain regions of the circuit section 4, and aluminum electrodes 19.20 will also be deposited on the N-type diffusion regions 21.22 that will become the source or drain regions of the circuit section 5. Electrodes 23,24 are applied.

What is important here is that each diffusion region 21 of the readout circuit section 5
．． 22 is, for example, a light surface temperature of ~10/cIA.

The diffusion depth is formed shallowly at ~0.3 μm, and As is used as the diffusion impurity.On the other hand, each diffusion region 17,18 of the write circuit section 4 is formed several times deeper, for example, at ~1 μm, and the surface concentration is ~10/d.

As diffusion layer with diffusion depth ~0.3μ and two surface angle ~10”
/cIi, and is composed of a P diffusion layer with a diffusion depth of ~1μ. Therefore, the diffusion regions 21 and 22 on the reading side form a shallow PN junction 25 with the substrate 1, and the impurity concentration profile there is steep. 1 and a relatively deep PN between
A junction 26 is formed, and the impurity concentration there (in the depth direction) changes gradually, forming a graded junction.
Juncti-on).

With this configuration, the diffusion regions 21 and 22 of the readout circuit section 5 are shallow and a short channel can be formed, so that high speed and high integration can be achieved. At the same time, a higher voltage (for example, 25V) is applied to the readout circuit section 5.
), the gate oxide film 10b of the write circuit section 4 is formed to be thicker than that of the read circuit section 5, and each of the diffusion regions 17 and 18 has a relatively shallow diffusion layer with a high concentration. Since it consists of a deep diffusion layer and the change in impurity concentration in the deep diffusion layer is gradual, the surface breakdown voltage and junction breakdown voltage can be made sufficiently high, and a high breakdown voltage can be achieved.

As a result of uniquely configuring the convolution circuit section 4 as described above, it has been experimentally confirmed that the characteristics are improved as follows compared to the case where the diffusion regions 17 and 18 are simply formed shallowly by A8 diffusion. .

Next, a method for creating the structure shown in FIG. 1 will be explained with reference to FIG.

First, as shown in FIG. 2A, selective oxidation is performed on the entire surface of the substrate 1 using the Si8N film 27 as a mask according to a well-known technique, and the field StO film 2 is grown in a predetermined pattern. As is well known, the P-type channel stopper 16 is formed by ion-implanting P-type impurities (for example, boron) using the Si, N, and film 27 as a mask before the selective oxidation, and then implanting impurities under the StO and film 2 by the selective oxidation. It can be formed by pressing the area.

Next, as shown in FIG. 2B, after removing Si, N, and the thin SiO layer 1128 under the film 27 by etching, gate oxidation is performed to grow a gate S10° film 29 with a thickness of about 80 OA. . Thereafter, as shown in FIG. 2C, only the area of the write circuit section is covered with a photoresist 30, and the SIO and film 29 in each area of the memory cell section and the read circuit section are removed by etching.

Next, after removing the photoresist 30, part oxidation is performed again to grow a Sin film 31 with a thickness of about 50 OA in each area of the memory cell part and the readout circuit part, as shown in FIG. 2D, and at the same time, the write circuit part is The area is further oxidized to increase the thickness of the Si film 29 to about 100 OA.

Next, as shown in FIG. 2E, a polysilicon film 32 is deposited over the entire surface by chemical vapor deposition (CVD) and patterned by well-known photoetching to form a gate electrode shape on SLO and i29 in the write circuit area. The remaining polysilicon film 14 is left and the rest is covered with a polysilicon film 32. In addition,
It is desirable that the entire polysilicon film 32 be subjected to a well-known phosphorus treatment before this patterning.

Next, as shown in FIG. 2F, when an ion beam 33 of N-type impurity having a large diffusion constant, especially phosphorus, is implanted at a dose of about 1×10 /d, polysilicon films 14 and 32 and S
10. Step S10.
Phosphorus ions are implanted through the membrane 29 and the phosphorus implanted region 3
4.35 is formed shallowly by the self-line. Next, the resistance of the polysilicon film 14.32 is reduced by heat treatment in a POCl atmosphere.

Next, as shown in FIG. 2G, the polysilicon group 32 is patterned by well-known photoetching to form the S of the readout circuit section.
tO, a polysilicon film 15 in the shape of a gate electrode is formed on the film 31.
On the other hand, in the memory cell part, the field sio,
Polysilicon E! adjacent to membrane 2! h, remove part of 32.

Gate oxidation is then carried out again in dry O1 at e.g. 1000°C.
2H for 100 minutes, thereby growing a thin SIO film 11 on the optical surface of each polysilicon 914, 15.32 as shown in FIG. Deep N type regions 17 and 18 are formed.

Next, as shown in FIG. 2I, a second layer of polysilicon film 36 is formed.
After depositing on the entire surface by CVD, a photoresist 37 is covered in a predetermined pattern as shown in FIG. membrane 11
．． The polysilicon film 32°StO and the film 31f are sequentially etched and patterned into the shape of each gate portion constituting each FET. That is, each gate portion is made of polysilicon film 7-8.
iO1 film 11-polysilicon film 6-gate oxide film 10a
Made with laminate.

Next, as shown in the figure, the second layer polysilicon film 36 of the write and read circuit part is removed by etching while the memory cell part is covered with a 7-photoresist 38.
, the films 11, 29 and 31 are removed by etching, respectively.

As a result, in the write circuit section, a relatively thick gate oxide film 10b with a thickness of 100 OA remaining from the SiO* film 29 is under the polysilicon film 14, and in the read circuit section, 5IOt&31
The remaining thin gate oxide films 10c having a thickness of 500 Å are located under the polysilicon film 15, respectively.

Next, as shown in FIG.
At the same time as the film 11 is grown, a thermally oxidized film 10 is grown to a thickness of about 300 Å on the exposed second surface of the substrate 1.

Next, as shown in FIG. 2M, an ion beam 39 of N-type impurity with a small diffusion coefficient, for example, As, is implanted to the extent of 1×10”/d, and the polysilicon film 6,7°14.15 and sio
, As ions are implanted into the substrate 1 through only the thin Sin film 10 using the film 2 as a mask to form a shallow ion implantation region 40.
are formed respectively.

Next, as shown in FIG. 2N, the phosphor gas film 12 is
is deposited on the entire surface by CVD, and then covered with a predetermined pattern using the photoresist 41 as a mask, the glass film 12,
The 5 liter film 10 is sequentially etched to form each contact hole.

Then, for example, in the atmosphere of POCJs, at 1000 ° C.
The above injected A8 by heat treatment for 0 min
As shown in FIG. 20, source or drain regions 8 and 9 are formed in the memory cell portion, and 21 and 22 are formed in the readout circuit portion. In the write circuit section, the concentration near the surface of the N-type regions 17 and 18 is further increased by As ion implantation.

On the other hand, there is POCl under the contact hole in the memory cell part.
Phosphorus from No. 2 is implanted, and this phosphorus implantation forms a partially deepened N+ region 9. Note that this heat treatment softens the red surface of the glass film 12 and flattens it to some extent, thereby reducing the problem of breakage that may occur during the subsequent formation of the two electrodes. That is, in the state shown in FIG. 20, aluminum is vapor-deposited on the entire surface for electrodes and their wiring, and each step shown in FIG. When forming the poles or wiring 13.19, 20, 23, 24,
In particular, since the glass film 12 is somewhat flattened in the contact hole portion, breaks in the vapor-deposited aluminum are less likely to occur, and poor contact can be prevented.

Through the process described above, especially since the diffusion regions 17 and 18 of the commitment circuit section are formed by phosphorus drive diffusion, the junction depth can be reliably increased (and the impurity concentration profile there is also gentle). Moreover, since no extra heat treatment step is introduced after ion implantation, the concentration profile of each diffusion region does not substantially change (therefore, the withstand voltage can be maintained sufficiently).

FIG. 3 shows another method as an alternative to FIG. 2 described above.

That is, in this step, unlike the above-mentioned step, phosphorus ions are not implanted into the write circuit portion in advance, and the series of processes shown in FIGS. 2A to 2L are performed. Therefore, as shown in FIG. 3A, there is no phosphorus diffusion region in the write circuit section, and the other regions have the same structure as in FIG. 2L.

Next, as shown in FIG. 3B, an As ion beam 39 is irradiated to form a thin S10! Ions are implanted through the film 10 to form shallow As ion implantation regions 40 at various locations.

Next, as shown in FIG.
, the film 42 is covered, and light oxidation is performed in this state to form the memory cell part and the bladder outlet circuit part 81 of the SIOT M-containing circuit part.
Only the 0□ film 10 is left at a film thickness of 30OA.

Next, after removing the Si3N4 film 42, as shown in FIG. 3D, a phosphorus ion beam 33 is implanted at low energy to implant phosphorus ions only through the thin sio film 10 in the ion implantation area, thereby removing the impurity 19 in the ion implanted region. doping with phosphorus, which has a large diffusion coefficient.

Next, by heat treatment, the implanted phosphorus is driven and diffused and As ions are activated, and as shown in FIG. 3E, an N+ type region 171 with a depth of 1 μm is formed in the write circuit section.
8, and in other circuit parts N-type regions 8.9. to a depth of ~0.3 Am. 21 and 22 are formed.

The method shown in FIG. 4 may be adopted instead of the step shown in FIG. 3D above.

That is, as shown in FIG. 3C, light oxidation is performed, and then light etching is performed to etch each 5-iot film 10. As a result, as shown in FIG. 4A, 810. 810 of the thickness of the membrane. gland 10
(film thickness 300A) is completely etched away.

Next, as shown in FIG. 4B, phosphorus is diffused into the exposed surface of the substrate 1 of the write circuit section by a well-known vapor phase diffusion technique to form deep phosphorus diffusion regions 17,18.

Next, heat treatment is performed to activate the implanted A8 ions, thereby stretching each impurity implanted region somewhat and forming an N type region 17. to a desired depth as shown in FIG. 4C. 1
8. 8. 9. 21. 22 respectively. Note that FIG. 4C shows a structure corresponding to FIG. 20.

FIG. 5 shows yet another method.

In this example, after etching the second layer polysilicon film 36 and thin S*OtM as shown in the figure, the Slow film Al-' is etched as shown in FIG.
H S t a N 4 W 43 k CV D K
J: Tight and adheres to the entire surface.

Next, as shown in FIG. 5B, the 8102 film or St, N film in the write circuit area is etched by well-known photoetching.

Only the antinode 43 is completely removed, and phosphorus is vapor-phase diffused from this removed portion or ions are implanted to form N-type regions 17 and 18.
form.

Next, after removing the Sin film 43 by etching, the fifth film 43 is removed by etching.
As shown in figure C, a thin Sin film 10°11 was grown by light oxidation, and 8 ions 39 were further implanted into the 5iO1 film 1.
A shallow As ion implantation region 40 is formed directly under the 0. After that, step 1, in the same manner as described above, deposits a phosphosilicate glass film, forms contact holes, activates implanted ions, etc., and creates a structure similar to that shown in FIG.

Although the present invention has been illustrated above, the embodiments described above can be further modified based on the technical idea of the present invention.

For example, the present invention is not limited to EPROMs, but is applicable to products including high voltage circuits and high speed circuits.

In addition, the structure of each FET and the material of each component may be changed in various ways (and the conductivity type of each semiconductor region may also be changed). is not limited to the method described above, and can be modified in various ways.

According to the present invention, as described above, since the junction depth of the write circuit section can be increased and the rotation change there can be made gentler, the surface breakdown voltage and the junction withstand voltage can be further increased. It is possible to achieve pressure resistance. Furthermore, since the lead-out circuit has a shallow junction depth, it is possible to perform high-speed operation with i'tT capability and to improve the degree of integration.

[Brief explanation of the drawing]

The drawings show embodiments of the present invention, and FIG.
2A to 20 are cross-sectional views of the main parts of the PROM; FIGS. 2A to 20 are cross-sectional views showing the manufacturing method in the order of steps; FIGS. 3A to 3E are cross-sectional views showing the main steps of a different method; and FIG. 4C and 5A to 5C are cross-sectional views sequentially showing the main steps of two further methods. In addition, regarding the symbols used on the first side, 3 is a memory cell section, 4 is a write circuit section, 5 is a read circuit section, and 25 and 26 are PN junctions. , -254,3 Fig. 2D Fig. 2T: Fig. 21 Fig. 2 Fig. j/ Fig. 3 C Fig. 4C

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device in which a high voltage circuit section and a low voltage circuit section consisting of an insulated gate FET are formed in a semiconductor region of a first conductivity type, wherein a drain region of the high voltage circuit section is formed. and introducing impurities of the second conductivity type into locations where drain regions of the low-voltage circuit section and the high-voltage circuit section are to be formed. A method for manufacturing a semiconductor integrated circuit device.