JPS57155771A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57155771A
JPS57155771A JP56040332A JP4033281A JPS57155771A JP S57155771 A JPS57155771 A JP S57155771A JP 56040332 A JP56040332 A JP 56040332A JP 4033281 A JP4033281 A JP 4033281A JP S57155771 A JPS57155771 A JP S57155771A
Authority
JP
Japan
Prior art keywords
junction
diffusion
regions
circuit
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56040332A
Other languages
Japanese (ja)
Inventor
Kazuhiro Komori
Jun Sugiura
Ken Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56040332A priority Critical patent/JPS57155771A/en
Publication of JPS57155771A publication Critical patent/JPS57155771A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Abstract

PURPOSE:To obtain an EPROM with high surface breakdown voltage and junction pressure-resistance and high operating speed by a method wherein the junction depth of a writing-in circuit part is increased, and the change of impurity density thereat is reduced with shallow junction of a reading-out circuit. CONSTITUTION:A memory cell part 3, writing circuit 4 and reading circuit 5 constituting the EPROM are respectively isolated by a field SiO2 film 2 and P<+> type channel stopper 16 on the lower part thereof. The memory cell part 3 is constituted using a known MOSFET. Hereupon, an N type diffused regions 21, 22 serving as the source, drain regions of the reading circuit part 5 are shallowly formed, for example, surface density -10<20>/cm<3> and diffusion depth -0.3mum; while each of diffusion regions 17, 18 of the reading circuit part is constituted for example, of arsenic diffusion layer with surface density -10<20>/cm<3> and diffusion depth -0.3mum and phosphorous diffused layer with surface density -10<19>/cm<3> and diffusion depth 1mum. In other words, the diffused regions 17, 18 are formed in deep slanting junction with a substrate 1 on the writing side.
JP56040332A 1981-03-23 1981-03-23 Semiconductor integrated circuit device Pending JPS57155771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56040332A JPS57155771A (en) 1981-03-23 1981-03-23 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56040332A JPS57155771A (en) 1981-03-23 1981-03-23 Semiconductor integrated circuit device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP62266329A Division JPS63126279A (en) 1987-10-23 1987-10-23 Manufacture of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS57155771A true JPS57155771A (en) 1982-09-25

Family

ID=12577662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56040332A Pending JPS57155771A (en) 1981-03-23 1981-03-23 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57155771A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59194473A (en) * 1983-04-19 1984-11-05 Sanyo Electric Co Ltd Manufacture of mos semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5168776A (en) * 1974-12-06 1976-06-14 Ibm Doreinryoikigako oyobi teifujunbutsunodobukaranaru denkaikokatoranjisuta
JPS5591877A (en) * 1978-12-30 1980-07-11 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5168776A (en) * 1974-12-06 1976-06-14 Ibm Doreinryoikigako oyobi teifujunbutsunodobukaranaru denkaikokatoranjisuta
JPS5591877A (en) * 1978-12-30 1980-07-11 Fujitsu Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59194473A (en) * 1983-04-19 1984-11-05 Sanyo Electric Co Ltd Manufacture of mos semiconductor device

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