JPS5952878A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5952878A JPS5952878A JP16346282A JP16346282A JPS5952878A JP S5952878 A JPS5952878 A JP S5952878A JP 16346282 A JP16346282 A JP 16346282A JP 16346282 A JP16346282 A JP 16346282A JP S5952878 A JPS5952878 A JP S5952878A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- polycrystalline silicon
- silicon layer
- impurities
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 238000005468 ion implantation Methods 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 238000001020 plasma etching Methods 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 244000025254 Cannabis sativa Species 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
微細寸法長のゲート電極に於けるホットギヤリア効果を
防止するに有効な浅いドレイン領域を形成するＬ Ｄ
Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｌｒり構造
体をなす半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention Forming a shallow drain region effective in preventing hot gearing effects in gate electrodes with fine dimensions L D
D (Relates to a method of manufacturing a semiconductor device having a Lightly Doped Drall structure.
（ｂ） 技術の背景
ＭＯ８型集積回路はメモリ、マイクロプロセッサへの応
用が広がると共に多結晶シリコンをゲート電極とするｎ
チャンネル型ＭＯ８ＩＣ，ＬＳＩが多く用いられる。近
年イオン打込技術、選択酸化技術、多結晶シリコン電極
ヤ成技術の発展に伴い、ＭＯ８ｍデバイスがＬＳＩの主
流となっている。(b) Background of the technology MO8 type integrated circuits are increasingly being applied to memories and microprocessors, and the use of polycrystalline silicon as gate electrodes
Channel type MO8ICs and LSIs are often used. In recent years, with the development of ion implantation technology, selective oxidation technology, and polycrystalline silicon electrode layer formation technology, MO8m devices have become the mainstream of LSIs.
例えばイオン打込技術′が広く使用されるのは低濃度領
域での制御性の良さを利用して、ゲート領域に不純物を
打込み、不純物濃度を変えることによるしきい値（、ｖ
ｔｈ）の制御である。−力選択酸化技術の基本は窒化シ
リコン膜（Ｓ１３Ｎ４）が酸化されにくいことを利用し
て、ＭＯ８ＩＣ，ＬＳＩのフィールド部に厚い二酸化シ
リコン膜（，５１０２ゝを形成させることにあ）この利
点は二酸化シリコン膜が厚くても平担になると共にフィ
ールド部分の酸化前に基板の８１部分に不純物をドープ
することにより選択的にフィールド部分の濃度が制御で
きる。即ち寄生ＭＯ８素子の防止が可能となる。For example, ion implantation technology is widely used because it takes advantage of its good controllability in low concentration regions, implants impurities into the gate region, and changes the impurity concentration by changing the threshold value (, v
th) control. - The basis of force selective oxidation technology is to utilize the fact that silicon nitride film (S13N4) is difficult to oxidize to form a thick silicon dioxide film (5102゜) in the field area of MO8IC, LSI. Even if the silicon film is thick, it becomes flat and the concentration in the field portion can be selectively controlled by doping the portion 81 of the substrate with impurities before oxidizing the field portion. That is, it is possible to prevent parasitic MO8 elements.
また多結晶シリコンをゲート電極とするＭＯＳプロセス
の特徴はゲート電極となる多結晶シリコンを拡散マスク
にしてソース、ドレインを形成することにある。このた
めゲート電極とソース、ドレインとの重なシは拡散層の
横方向への広がりによつて決まるため重なり部分を１μ
ｍ以下にすることができゲートドレイン間容量が小さく
なる。A feature of the MOS process using polycrystalline silicon as a gate electrode is that the source and drain are formed using polycrystalline silicon as a gate electrode as a diffusion mask. Therefore, the overlap between the gate electrode, source, and drain is determined by the lateral spread of the diffusion layer, so the overlap area should be 1 μm.
m or less, and the gate-drain capacitance becomes small.
又配線として拡散層、多結晶シリコン、アルミ電極の三
層が利用できる利点がある。Another advantage is that three layers, the diffusion layer, polycrystalline silicon, and aluminum electrode, can be used as wiring.
（Ｃ）従来技術と問題点
第１図は従来のｎチャンネル型シリコンゲート欅造のＭ
ｏ５ｓ）ランジスタの製造プロセスｆ 示Ｙ工程図であ
る。(C) Conventional technology and problems Figure 1 shows the conventional n-channel silicon gate Keyaki M
o5s) It is a process diagram showing the manufacturing process f of a transistor.
図中（５）に示すようなＰ形シリコン基板１の表面を１
．５μｍ程度高温酸化させて酸化膜（Ｓ１０２ ）２を
形成し、次いで活性領域全体の酸化膜２を除去する。次
いで（Ｂ） Ｋ：示すように酸化膜２を除去した活性領
域にゲート酸化膜３を形成する。この場合ドライ（Ｈ２
Ｏを含まない）酸素中での高温熱酸化法が用いられるが
（ト）の場合はウェット酸素中での厚い酸化膜形成を行
なう。次いで（０に示すようにＣＶＤ法によって多結晶
シリコン４をゲート酸化膜３上に形成する。次いで（ハ
）に示すようにゲート電極５とかる部分以外の多結晶シ
リコン４を除去したあと更にソースドレイン領域の酸化
膜３を除去する。次いで（２）に示すように多結晶シリ
コンでなるゲート電極５を拡散マスクとしてイオン打込
によ、クソース６．ドレイン７拡散を行う。打込まれる
不純物はｎｍの場合シん（Ｐ）或はひ素（ＡＳ）が拡散
されてｎ型領域となる。次いで（６）に示すように最終
保護膜としてりんシリケートガラス膜（ＰＳＧ）で被膜
し、メルト処理し、更にアルミ電極９を蒸着させる。The surface of the P-type silicon substrate 1 as shown in (5) in the figure is
．． An oxide film (S102) 2 is formed by high-temperature oxidation of about 5 μm, and then the oxide film 2 over the entire active region is removed. Then, as shown in (B) K:, a gate oxide film 3 is formed in the active region from which the oxide film 2 has been removed. In this case, dry (H2
In the case of (g), a thick oxide film is formed in wet oxygen. Next, as shown in (0), polycrystalline silicon 4 is formed on the gate oxide film 3 by the CVD method.Next, as shown in (c), after removing the polycrystalline silicon 4 other than the gate electrode 5, a source layer is further formed. The oxide film 3 in the drain region is removed.Then, as shown in (2), the source 6 and drain 7 are diffused by ion implantation using the gate electrode 5 made of polycrystalline silicon as a diffusion mask.The implanted impurity is In the case of nanometers, phosphorus (P) or arsenic (AS) is diffused to form an n-type region.Then, as shown in (6), a phosphorus silicate glass film (PSG) is coated as a final protective film and melt-treated. Then, an aluminum electrode 9 is further deposited.
このようなプロセスによって構成されるＴＸ’ｌ ＯＳ
型半導体装置において１〜２μｍ程度の微細寸法のゲー
ト長では、ゲート電極とドレイン領域の界面に電界集中
し、動作中にホットキャリア効果によりしきい値電圧（
Ｖｔｌ）、コンダクタンス（β）が変動し易く信頼性が
得られない。このためドレイン領域としてゲート電極近
傍には浅い不純物拡散層、隣接する領域に深い不純物拡
散層を備えたＬ Ｄ Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐｅ
ｄ Ｄｒａｉｎ）構造とすることによってホットキャリ
ア効果を防止することに着目したものである。ＬＤＤ構
造とするための製造プロセスにサイドエツチングがある
その具体例を第２図の工程図によって示す。TX'l OS configured by such processes
In a semiconductor device with a microscopic gate length of about 1 to 2 μm, the electric field concentrates at the interface between the gate electrode and the drain region, and during operation the threshold voltage (
Vtl) and conductance (β) are likely to fluctuate, making it difficult to obtain reliability. Therefore, as a drain region, an LDD (Lightly Dope) is used, which has a shallow impurity diffusion layer near the gate electrode and a deep impurity diffusion layer in the adjacent region.
d Drain) structure to prevent hot carrier effects. A specific example in which side etching is included in the manufacturing process for forming an LDD structure is shown in the process diagram of FIG.
（イ）に示すようにゲート電極をなす多結晶シリコン１
１上に窒化シリコン（ＳＩ３Ｎ４ ） １２及び二酸化
シリコン（Ｓｉ０２）をパターニング形成し、これをマ
スクとしてイオン打込を行う。次いで（ロ）に示すよう
に不純物層のソースドレイン領域１４゜１５を形成し、
更に多結晶シリコン１１を円筒型プラズマエツチング装
置によシサイドエッチングして図のように形成する。次
いで（ハ）に示すように平行平板型プラズマエツチング
により酸化シリコン、岱化シリコン膜をエツチング除去
し、更に多結晶シリコン１１をマスクとしてイオン打込
を行いソースドレイン領域を拡散成長させる。このよう
なプロセスによって次のに）に示すようにソースドレイ
ン領域１４．１５の形状はゲート電極近傍で浅くなるＬ
ＤＤ構造のＭＯ８型半導体装置が得られる。Polycrystalline silicon 1 forming the gate electrode as shown in (a)
Silicon nitride (SI3N4) 12 and silicon dioxide (Si02) are patterned on 1, and ions are implanted using this as a mask. Next, as shown in (b), source and drain regions 14 and 15 of the impurity layer are formed,
Further, the polycrystalline silicon 11 is side-etched using a cylindrical plasma etching device to form a structure as shown in the figure. Next, as shown in (c), the silicon oxide and silicon oxide films are etched away by parallel plate plasma etching, and ions are implanted using the polycrystalline silicon 11 as a mask to grow source and drain regions by diffusion. Through such a process, the shape of the source/drain regions 14 and 15 becomes shallow near the gate electrode, as shown in (2) below.
An MO8 type semiconductor device with a DD structure is obtained.
しかしこのプロセスではゲート電極をなす多結晶シリコ
ン１１を円筒型エツチング装置を用い等方性エツチング
するもので、そのエツチング装置は反応性ガス例えばＣ
Ｆ４ （フレオンガス）のグロー放電によって活性なフ
ッ素（フッ素ラジカル）を発生させてこれが多結晶シリ
コンと反応してエツチングされるが時間制御がむづかし
く、半導体ウェハ開のバラツキが大きい。このため再現
性が得られにくい。また安定性に欠ける憾がある。However, in this process, the polycrystalline silicon 11 forming the gate electrode is isotropically etched using a cylindrical etching device, and the etching device uses a reactive gas such as carbon dioxide.
Active fluorine (fluorine radicals) is generated by glow discharge of F4 (Freon gas), which reacts with polycrystalline silicon and etches it, but time control is difficult and there are large variations in semiconductor wafer opening. For this reason, it is difficult to obtain reproducibility. There is also a problem with the lack of stability.
（ｄ） 発明の目的
本発明は上記の点に鑑み、ＬＤＤ構造の半導体装置の低
ドープドレイン領域を再現性よく正確に形成することを
目的とする。(d) Object of the Invention In view of the above points, an object of the present invention is to accurately form a lightly doped drain region of a semiconductor device having an LDD structure with good reproducibility.
（ｅ） 発明の構成
り開目的は本発明によれば半導体基板上に形成されたゲ
ート電極ケマスクとし゛Ｃ該半導体基板に不純物を導入
する工）ｌと、該ゲート′１−極に隣接して形成された
多結晶シリコンのマスク材および核ゲート電椿をマスク
として該半導体基板に不純物を導入する工程を含むこと
によって達せられる。(e) Structure of the Invention According to the present invention, a gate electrode mask is formed on a semiconductor substrate. This can be achieved by including the step of introducing impurities into the semiconductor substrate using the formed polycrystalline silicon mask material and nuclear gate electrode as a mask.
（ｆ） 発明の実施例 以下本発明の実施例全図面により詳述する。(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to all the drawings.
２ｒ！３図りま本発明の一実施例であるＬｌ）’Ｌ）構
造の製造プロセスを示す工程図である。2r! FIG. 3 is a process diagram showing the manufacturing process of the Ll)'L) structure which is an embodiment of the present invention.
（ａ）に示すようにＰ型シリコン基板２１に形成したゲ
ート酸化膜２２上にＣＶＤ法により多結晶シリコン２３
を図のようＶＣパターン形成することによりゲート電極
２４が得られる。次いで（ｂ）に示すようにゲート電極
２４を含む活性領域内にＣＶＤ法によりシリコン酸化膜
（８１０２）２５を形成し、更に多結晶シリコン２６を
被膜形成させる。次いで（Ｃ）に示すように平行平板型
プラズマエツチングで多結晶シリコン２６をバターニン
グ形成し、図のような第２の多結晶シリコン層２７をゲ
ート電極２４に隣接して形成する。しかる後にゲート電
極２４及び第２の多結晶シリコン層２７をマスクとして
第１のイオン打込によυ高濃度の不純物をドープし、ソ
ース、ドレイン領域２８ｆ：形成させる。次いで（ｄ）
に示すように第２の多結晶シリコン膜２７を円筒型プラ
ズマエツチングにより、エツチング除去する。次いでゲ
ー）’に極２４をマスクとして第２のイオン打込により
低濃歴の不純物全ドープし、浅い不純物領域２９を形成
させ拡散成長させる。As shown in (a), polycrystalline silicon 23 is deposited on a gate oxide film 22 formed on a P-type silicon substrate 21 by CVD.
A gate electrode 24 is obtained by forming a VC pattern as shown in the figure. Next, as shown in (b), a silicon oxide film (8102) 25 is formed in the active region including the gate electrode 24 by the CVD method, and a polycrystalline silicon 26 is further formed as a film. Next, as shown in (C), polycrystalline silicon 26 is patterned by parallel plate plasma etching, and a second polycrystalline silicon layer 27 is formed adjacent to gate electrode 24 as shown in the figure. Thereafter, using the gate electrode 24 and the second polycrystalline silicon layer 27 as a mask, a first ion implantation is performed to dope impurities at a high concentration of υ to form source and drain regions 28f. Then (d)
As shown in FIG. 3, the second polycrystalline silicon film 27 is etched away by cylindrical plasma etching. Then, using the electrode 24 as a mask, the gate layer is completely doped with low concentration impurities by second ion implantation to form a shallow impurity region 29 and grow by diffusion.
第１のイオン打込はひ素イオン（ＡＳ”）を１２０ｋｅ
Ｖのエネルギ、打込ドーズ５４Ｘ １０ − とするの
に対し第２のイオン打込では５ｏｋｅＶ、 ｌＸｌ０Ｉ
２ｄ２でドープすることにより射貰しいドレイン領域が
得られる。The first ion implantation was 120ke of arsenic ions (AS”).
The energy of V and the implantation dose are 54X10-, whereas the second ion implantation is 5okeV and lXl0I.
By doping with 2d2, a drain region with high radiation density can be obtained.
次いで（ｅ）に示すようにシリコン酸化膜２５をエツチ
ング除去し、りんシリケートガラス膜２９で最終的保饅
膜を行い更にアルミ電極３０を蒸着形成することにより
Ｌ Ｉ） Ｉ）構造のＭＯ８型半導体装置が得られる。Next, as shown in (e), the silicon oxide film 25 is removed by etching, a final protective film is formed with a phosphorus silicate glass film 29, and an aluminum electrode 30 is formed by vapor deposition to form an MO8 type semiconductor having the LI) I) structure. A device is obtained.
このように構成することにより従来構成の半導体装置に
比し安定した特性がイＦＪられ寸たサイドエツチング法
に比して本発明は再現性に優れる大きな利点がある。Due to this structure, the present invention has a great advantage of superior reproducibility compared to the side etching method, which has almost resulted in stable characteristics compared to a semiconductor device having a conventional structure.
第４図及び第５図は他の実旋例であるＬ Ｉ） Ｄ構造
の製造プロセスを示す工程図である。FIGS. 4 and 5 are process diagrams showing the manufacturing process of the LI)D structure, which is another practical example.
第４図において、（５）に示すようしこＰ型シリコン基
板３１にＣＶＤ法によりゲート酸化膜３２上に多結晶シ
リコンをパターン形成してゲー１− ？１１極３３を設
ける。このゲート電極３３をマスクとして第１イオン打
込によって低濃度の不純物をドープし浅い不純物層をな
すソースドレイン領域３４を形成させる。次いで（Ｂ）
に示すようにＣＶ Ｄ法によりシリコン酸化膜、更に多
結晶シリコンを形成させ第３図に示す同一手順でゲート
電極３３に隣接する多結晶シリコン層３５を形成させる
。In FIG. 4, polycrystalline silicon is patterned on a gate oxide film 32 by the CVD method on a p-type silicon substrate 31 as shown in (5). 11 poles 33 are provided. Using this gate electrode 33 as a mask, a low concentration impurity is doped by first ion implantation to form a source/drain region 34 forming a shallow impurity layer. Then (B)
As shown in FIG. 3, a silicon oxide film and further polycrystalline silicon are formed by the CVD method, and a polycrystalline silicon layer 35 adjacent to the gate electrode 33 is formed in the same procedure as shown in FIG.
次いでゲ−） 電ｔＷ ３３及び多結晶シリコン層３５
をマスクとして第２のイオン打込によって高濃度の不純
物をドープし、深い不純物層をなすソースドレイン領域
３６を得る。次いで（Ｃ）に示すように円筒型プラズマ
エツチングによｐ多結晶シリコン３５及びシリコン酸化
膜をエツチング除去する。Then, the electric current tW 33 and the polycrystalline silicon layer 35
Using this as a mask, high concentration impurities are doped by second ion implantation to obtain source/drain regions 36 forming deep impurity layers. Next, as shown in (C), the p-polycrystalline silicon 35 and silicon oxide film are etched away by cylindrical plasma etching.
次いで（！Ｊ）に示すように不純物層のソースドレイン
仰域３４．３６を拡散成長させＬ Ｄ Ｄ構造のＭＯ８
型半導体装置が得られる。Next, as shown in (!J), the source/drain elevation regions 34 and 36 of the impurity layer are grown by diffusion to form MO8 of the LDD structure.
type semiconductor device is obtained.
第５図では（ａ）に示すようにゲート［械４１に瞬接し
て多結晶シリコン層４２を形成し、ゲート電極４１及び
多結晶シリコン層４２ｆ：マスクとして第１のイオン打
込によって高濃度の不純物をドープする。次いで（ｂ）
に示でように深い不純物領域４３を拡散成長させ、多結
晶シリコン＋ａ４Ｚをプラズマエツチングでエツチング
除去する。次いで（Ｃ）に示すようにゲート電極４１を
マスクとし、て第２のイオン打込を行い、低濃度の不純
物をドープする。In FIG. 5, as shown in FIG. 5(a), a polycrystalline silicon layer 42 is formed in momentary contact with a gate electrode 41 and a polycrystalline silicon layer 42f as a mask by the first ion implantation. Dope with impurities. Then (b)
As shown in FIG. 3, a deep impurity region 43 is grown by diffusion, and the polycrystalline silicon+a4Z is etched away by plasma etching. Next, as shown in (C), a second ion implantation is performed using the gate electrode 41 as a mask to dope impurities at a low concentration.
次いで（ｄ）＋ｖ示すように拡散成長りｆ行いＬ ］、
） Ｄ構造のＭ ＯＳ型半導体が得られる。このように
多結晶シリコンをゲート電極に隣接して設け、これをマ
スクとして不純物をドープすることによりＴ、 Ｄ Ｄ
構が（ヲが丁ｎチャンネル１（リシリコンゲート構造の
Ｔν１０Ｓトランジスタが得られる。更にひ素（Ａｓ
）又けりん（Ｐ）等の不純物を深い不純物領域或は浅い
不純物領域に組合せて用いること（でより更に特性の異
かる各種のトランジスタが得られる。Then, as shown in (d)+v, diffusion growth f is performed L ],
) A D-structure MOS type semiconductor is obtained. In this way, by providing polycrystalline silicon adjacent to the gate electrode and doping impurities using this as a mask, T, D D
With this structure, a Tν10S transistor with an n-channel 1 silicon gate structure can be obtained.
) Also, by using an impurity such as phosphorus (P) in combination in a deep impurity region or a shallow impurity region, various transistors with further different characteristics can be obtained.
（１２）発明の効果
以上詳細に説明したように本発明のゲート電極サイドに
多結晶シリコン層を形成」２、ゲート電極及び多結晶シ
リコン層をマスクとしてゲート重極近傍に低ドープドレ
イン領域を形成１゛るＬ Ｄ Ｄ構造とすることにより
ホットキャリア多１ノ冴２をμ力比する安定した特性が
得られる。またサイドエツチング処理法に比して再現性
よく正確な加工法である等大きな効果がある。(12) Effects of the Invention As explained in detail above, forming a polycrystalline silicon layer on the gate electrode side of the present invention" 2. Forming a lightly doped drain region near the gate pole using the gate electrode and polycrystalline silicon layer as a mask. By adopting an LDD structure of 1, stable characteristics can be obtained in which the number of hot carriers is 1, 2 and 2. It also has great effects, such as being a more accurate processing method with better reproducibility than the side etching method.
第１図は従来のｎチャンネル型シリコンゲート構造のＭ
ＯＳ）ランジスタの製造プロセスを示す工程図、第２図
はサイドエツチングによるＬＤＤ構造をなすＩＶ’［Ｏ
８）ランジスタの製造プロセスを示す工程図、第３図は
本発明の一実施例である多結晶シリコン層をマスクとす
るＬＤＤ構造の製造プロセスを示す工程図、第４図及び
第５図は他の実施例を示す工程図である。図中２１．．
３１１−ｔＰ型シリコン基板、２２．３２はゲート酸化
膜、２３は多結晶シリコン、２４，３３．４１はゲート
電極、２５ｔ／ｉシリコン酸化膜、２６は多結晶シリコ
ン膜、２７，３５．４２は多結晶シリコン層（マスク材
）、２８，３４，３６．４３は不純物領域を示す。
茅 １ 品
（切 （灼Figure 1 shows the conventional n-channel silicon gate structure.
FIG. 2 is a process diagram showing the manufacturing process of an IV'[O
8) A process diagram showing the manufacturing process of a transistor, FIG. 3 is a process diagram showing the manufacturing process of an LDD structure using a polycrystalline silicon layer as a mask, which is an embodiment of the present invention, and FIGS. 4 and 5 are other diagrams. It is a process diagram showing an example of. 21 in the figure. ．．
311-tP type silicon substrate, 22.32 is gate oxide film, 23 is polycrystalline silicon, 24, 33.41 is gate electrode, 25t/i silicon oxide film, 26 is polycrystalline silicon film, 27, 35.42 is The polycrystalline silicon layer (mask material) 28, 34, 36, and 43 indicate impurity regions. 1 piece of grass (cut)
Claims (1)
半導体基板に不純物を導入する工程と、該ゲート電極に
隣接して形成された多結晶シリコンのマスク材および該
ゲート雷１椿をマスクとして該半導体基板に不純物を導
入する工程を含むことを特徴とする半導体装置の製造方
法。A step of introducing impurities into the semiconductor substrate using a gate electrode formed on the semiconductor substrate as a mask, and a step of introducing an impurity into the semiconductor substrate using a polycrystalline silicon mask material formed adjacent to the gate electrode and the gate lightning as a mask. A method for manufacturing a semiconductor device, the method comprising the step of introducing impurities into a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16346282A JPS5952878A (en) | 1982-09-20 | 1982-09-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16346282A JPS5952878A (en) | 1982-09-20 | 1982-09-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5952878A true JPS5952878A (en) | 1984-03-27 |
| JPH0481327B2 JPH0481327B2 (en) | 1992-12-22 |
Family
ID=15774333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16346282A Granted JPS5952878A (en) | 1982-09-20 | 1982-09-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5952878A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60244074A (en) * | 1984-05-18 | 1985-12-03 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPS60245176A (en) * | 1984-05-18 | 1985-12-04 | Matsushita Electric Ind Co Ltd | Manufacture of mis type field effect transistor |
| JPS6229169A (en) * | 1985-07-30 | 1987-02-07 | Sony Corp | Manufacture of mos semiconductor device |
| JPS6342161A (en) * | 1986-08-07 | 1988-02-23 | Toshiba Corp | Manufacture of cmos type semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5283073A (en) * | 1975-12-29 | 1977-07-11 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS5444482A (en) * | 1977-09-14 | 1979-04-07 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device and its manufacture |
| JPS57106169A (en) * | 1980-12-24 | 1982-07-01 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1982
- 1982-09-20 JP JP16346282A patent/JPS5952878A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5283073A (en) * | 1975-12-29 | 1977-07-11 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS5444482A (en) * | 1977-09-14 | 1979-04-07 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device and its manufacture |
| JPS57106169A (en) * | 1980-12-24 | 1982-07-01 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60244074A (en) * | 1984-05-18 | 1985-12-03 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPS60245176A (en) * | 1984-05-18 | 1985-12-04 | Matsushita Electric Ind Co Ltd | Manufacture of mis type field effect transistor |
| JPS6229169A (en) * | 1985-07-30 | 1987-02-07 | Sony Corp | Manufacture of mos semiconductor device |
| JPS6342161A (en) * | 1986-08-07 | 1988-02-23 | Toshiba Corp | Manufacture of cmos type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0481327B2 (en) | 1992-12-22 |
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