JPS587070B2 - hand tai souchi no seizou houhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a field effect semiconductor device.

Conventionally, field effect semiconductor devices, especially field effect semiconductor devices with a junction gate structure, have a structure called a horizontal or vertical structure, depending on whether the current flow is parallel or perpendicular to the main surface. Semiconductor devices have been manufactured.

We proposed a field-effect semiconductor device with a planar structure that is completely different from the above concept, and it turned out that the device has a new structure that can obtain the desired characteristics almost independently of manufacturing conditions.

The present invention has been made in view of these points, and provides a new method for manufacturing a field effect semiconductor device having a planar structure.

Hereinafter, an example of the features and manufacturing method of the present invention will be explained with reference to the drawings.

Incidentally, FIGS. 1 and 2 show conventionally well-known field effect semiconductor devices having horizontal and vertical structures.

The gate electrode is arranged so that an electric field is applied perpendicularly to the direction of the current flowing between the source 3 and the drain 9, but in the former, the current flows parallel to the substrate surface, and in the latter, the current flows in the direction perpendicular to the substrate. ing.

FIG. 3 shows a planar field effect semiconductor device to which the method of the present invention is applied.

The difference from the lateral semiconductor device shown in FIG.
A deposited region sandwiched between the lower part of the gate electrode 6 and the substrate 1 existed.

However, the planar structure shown in FIG. 3 is characterized in that the direction of the electric field of the gate electrodes 6, 6 is also parallel to the main surface of the substrate 1.

In the figure, 1 is a substrate, 3 is a single crystal film, 6 is a gate region, 8 is a source, 9 is a drain, and 10 is an isolation oxide film.

A feature of this structure is that if the gate gap is determined in advance using a mask, the thickness of the region sandwiched between the gates (called a channel) will not change due to variations in manufacturing processes such as diffusion or vapor phase growth. It is easy to obtain the characteristics of

On the other hand, in the conventional structure, it is well known that the thickness of the vapor growth layer varies, and the variation in the diffusion of impurity 5 for forming the gate region directly leads to changes in the channel, resulting in changes in characteristics.

An example of the manufacturing process of the structure shown in FIG. 3 by the method of the present invention will be explained with reference to the cross-sectional views shown in FIGS. 4a to 4c.

That is, first, a film 11 consisting mainly of heavy elements is deposited on a single crystal substrate 1 and selectively removed by etching to form a mask for high-speed ion protection.

The film 11 is formed by laying a nitride film 11a as an underlayer, forming a film 11b on top of the nitride film 11a by vapor deposition of a heavy element, for example, gold, and selectively removing it.
The area directly under a becomes the gate formation region, and the area sandwiched between the gate formation regions (the part directly under the film 11) becomes the source,
This becomes a drain formation region, and the respective widths W1 and W2 are approximately the same length, for example, 2 to 5 μm.

Next, using this film 11 as a mask, for example, nitrogen ions (or oxygen ions or a mixture of both) are accelerated with high-speed energy, for example, 150 KeV to 1 MeV, and selectively implanted into the substrate 1.

Note that when nitrogen ions N are implanted with an energy of 200Ke■ to 400Ke■, the penetration depth into the substrate 1 is 0.5
~1 μm.

(FIG. 4a) The membrane 11 is made of a material and thick enough to stop these accelerated ions within the membrane 11.

The ions implanted at high speed have a Gaussian distribution with a peak at a certain depth within the substrate, and react with silicon during subsequent heat treatment to form an insulating layer (oxide film) 2.

After this, impurities of the same conductivity type as the substrate, such as boron B, are added.
A gate region is formed on the insulating layer 2 by ion implantation or diffusion to a depth that reaches the insulating layer 2.

(Figure 4b) When ion-implanting boron B, 100Ke~1 at 1013~1015/cm2.
It is sufficient to implant with an energy of 5 KeV.

After the ion implantation, the film 11 is removed, and a new film such as an oxide film is deposited only on the areas where ions have not been implanted unlike in the previous case, thereby forming the channel forming mask 12.

To form this channel forming mask 12, the film 1
Either the nitride film 11a as an underlayer of 1 and the film 1lb formed by vapor deposition of a heavy element such as gold are selectively oxidized by leaving only the underlying nitrogen film 11a as a mask to form an oxide film. 11 nitride film 1lb
There are ways to remove this.

Next, using the oxide film 12 formed in this manner as a mask, in other words, in the portion sandwiched between the gate regions, an impurity having a conductivity type opposite to that of the substrate 1, such as phosphorus P, is ion-implanted or diffused into at least the insulating layer 12. The impurity is allowed to penetrate to a region no shallower than the depth.

Figure 4C).

In addition, when ion-implanting phosphorus P+, 1011~
It is sufficient to inject energy of 150 KeV to 200 KeV at 1012/Cd.

After that, the source and drain regions are formed by the usual method.
For example, this can be carried out by implanting a highly concentrated impurity of the conductivity type opposite to that of the substrate 1.

The method of the present invention is a new type of semiconductor device, so it is different from the conventional method of manufacturing semiconductor devices, but in order to facilitate integration, the gate region is insulated from the substrate, and the semiconductor crystal is Since it can be used as a substrate, it has the advantage that a region with better crystallinity can be used as an operating region than when using an insulating substrate, and characteristics can be improved.

As described above, according to the present invention, an insulator is created under the gate by ion implantation to insulate the gate and the substrate, which reduces variations in the manufacturing process and creates a structure suitable for integration. Something that can be easily manufactured.

[Brief explanation of drawings]

1 and 2 are structural diagrams showing conventional field effect semiconductor devices, with FIG. 1 showing an example of a horizontal structure and FIG. 2 showing an example of a vertical structure. FIG. 3 is a perspective view showing a planar field-effect semiconductor device;
4A and 4C are cross-sectional structural diagrams of a semiconductor device showing an embodiment of the manufacturing method of the present invention. Note that the same reference numerals in the figures indicate the same or corresponding parts. 1 is a substrate, 2 is an oxide film (insulating layer), 3 is a single conjunctival membrane, 4 is a polycrystalline film, 5 is an oxide film, 6 is a gate, 7 is a depletion layer, 8 is a source, 9 is a drain, 10 is an isolation oxide film, 11 is a fast ion Protective mask, 12 is a channel forming mask.

Claims (1)

[Claims] 1. A step of selectively depositing a film made of a material made of a relatively heavy element on one main surface of a semiconductor substrate so that at least one pair of gate formation regions is formed, and masking this selectively deposited film. Injecting ions of nitrogen, oxygen, or a mixture of both at high energy into the gate formation region from the exposed surface, and implanting the ions in the gate formation region so that the distribution has a peak at a certain depth within the substrate,
and a step of forming an insulating layer through subsequent heat treatment, and a step of forming a gate region by introducing impurities of the same conductivity type as the substrate up to the upper main surface of the gate formation region where the ions are implanted and then the insulating layer is formed. . A method for manufacturing a semiconductor device, including the step of introducing an impurity having a conductivity type opposite to that of the substrate into a region sandwiched between upper gate regions, and causing the impurity to penetrate at least to a region not shallower than the insulating layer.