JPS60147132A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60147132A
JPS60147132A JP376384A JP376384A JPS60147132A JP S60147132 A JPS60147132 A JP S60147132A JP 376384 A JP376384 A JP 376384A JP 376384 A JP376384 A JP 376384A JP S60147132 A JPS60147132 A JP S60147132A
Authority
JP
Japan
Prior art keywords
silicon oxide
mask
film
region
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP376384A
Other languages
Japanese (ja)
Inventor
Tsunemitsu Koda
國府田 恒充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP376384A priority Critical patent/JPS60147132A/en
Publication of JPS60147132A publication Critical patent/JPS60147132A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To enable to isolate separate elements with excellent reproducibility, massproductivity and greater freedam on disignation for shapes by a method wherein a mask pattern for implanting oxygen ion is formed on the surface of a semiconductor by means of photolithography and then an insulating region for separating elements is formed after implanting oxygen ion. CONSTITUTION:A silicon oxide film 12 is formed on the surface of a semiconductor 1 by means of thermooxidation. Firstly a photoresist film is formed and then a photoresist pattern 2' with separating region and opening is formed. Then an opening 13 is formed on the silicon oxide film 12 utilizing the photoresist 2' as a mask. When the photoresist pattern 2' is removed, an oxide silicon film mask with an opening in an element separating part is formed. Secondly when oxygen ion is implanted utilizing the film 12 as a mask, the implanted region is changed into silicon oxide 14 to be an element separating region. Finally when the film 12 utilized as a mask and unnecessary silicon oxide are removed by etching process, the semiconductor substrate 1 filled with another silicon oxide 14' for separating elements may be completed.

Description

【発明の詳細な説明】 (技術分野) 本発明は半導体装置の製造方法に関し、特に改良された
素子分離法による半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device using an improved element isolation method.

(従来技術) 高速動作を要求される半導体素子の需要が高まっている
現在、半導体素子の高速動作を妨げる要因である寄生容
量を減少させるために種々のプロセスが開発、実施され
ている。その中でも寄生容量の少ない素子分離を行う手
法は、確実に半導体素子の高速特性を改善できるために
、一部の製品では既に実施されている。
(Prior Art) As demand for semiconductor devices that require high-speed operation is increasing, various processes have been developed and implemented to reduce parasitic capacitance, which is a factor that hinders high-speed operation of semiconductor devices. Among them, the method of element isolation with less parasitic capacitance is already being implemented in some products because it can reliably improve the high-speed characteristics of semiconductor devices.

これらの素子分離法の代表的なものとしては溝掘り法が
あげられる。溝堀り法の一例としては第1図(al〜(
g)の工程によシ実施されている。
A typical example of these element isolation methods is the trenching method. An example of the trenching method is shown in Figure 1 (al~(
This is carried out according to step g).

先ず、第1図ta+に示すように、半導体基板10表面
にホトリソグラフィ技術によりホトレジスト膜のパター
ン2を形成した後、第1図(b)に示すようにホトレジ
スト膜パターンをマスクとして、半導体基板を異方性エ
ツチングによりエツチングし7字形の断面形状を持つ溝
3を形成する。次いで第1図(C1に示すようにホトレ
ジスト膜2を除去する。次に第1図fd)に示すように
、溝をCVD S i 024で埋める。次に第1図(
e)に示すように溝部上のCVD、8.02にホトレジ
ストマスク5を形成し、第1図(f)K示すように不要
のCVD S + Oxをエツチング除去すると第1図
(g)に示すような素子分離領域イの形成された半導体
基板1が得られる。
First, as shown in FIG. 1 (ta+), a photoresist film pattern 2 is formed on the surface of the semiconductor substrate 10 by photolithography, and then the semiconductor substrate is exposed using the photoresist film pattern as a mask as shown in FIG. 1 (b). Etching is performed by anisotropic etching to form a groove 3 having a figure-7 cross-sectional shape. Next, as shown in FIG. 1 (C1), the photoresist film 2 is removed. Next, as shown in FIG. 1 fd, the trench is filled with CVD Si 024. Next, Figure 1 (
As shown in e), a photoresist mask 5 is formed on the CVD portion 8.02 above the groove, and unnecessary CVD S + Ox is etched away as shown in FIG. 1(f)K, as shown in FIG. 1(g). A semiconductor substrate 1 having such an element isolation region A formed therein is obtained.

しかし、溝堀シ法においては、溝の形成を異方性エツチ
ングに依っているためいくつかの欠点を有しているが、
そのうちで顕著なものは次の通りである。
However, the Mizohori method has some drawbacks because it relies on anisotropic etching to form the grooves.
The following are notable among them:

(1) 異方性エツチングは、エツチング条件の制約が
多く、その管理が困難なため、再現性に乏しく量産には
適さない。
(1) Anisotropic etching has many restrictions on etching conditions and is difficult to manage, resulting in poor reproducibility and is not suitable for mass production.

(2)得られる溝の形状がシリコンの結晶構造に依存し
ているため溝の形状に対する自由度がなく、特に深い溝
を得ようとした場合には基板表面に占める素子分離部の
面積が大きくなることである。
(2) Since the shape of the groove to be obtained depends on the crystal structure of silicon, there is no degree of freedom in the shape of the groove, and when trying to obtain a particularly deep groove, the area of the element isolation part on the substrate surface becomes large. It is what happens.

(発明の目的) 本発明の目的は、上記欠点を除去し、再現性。(Purpose of the invention) The purpose of the present invention is to eliminate the above drawbacks and improve reproducibility.

量産性に富み、その形状に対する自由度も大きい素子分
離が可能な半導体装置の製造方法を提供するにおる。
An object of the present invention is to provide a method for manufacturing a semiconductor device that is highly mass-producible, has a large degree of freedom regarding its shape, and is capable of element isolation.

(発明の構成) 本発明の第1の発明の半導体装置の製造方法は、半導体
基板の表面にホ) IJソグラフィ技術にょシ酸素イオ
ン打込み用のマスクパターンを形成する工程と、該マス
クパターンを介して酸素イオンを打込み素子分離用の絶
縁領域を形成する工程とを含んで構成される。
(Structure of the Invention) The method for manufacturing a semiconductor device according to the first aspect of the present invention includes the steps of: forming a mask pattern for oxygen ion implantation using IJ lithography technique on the surface of a semiconductor substrate; The method includes a step of implanting oxygen ions to form an insulating region for element isolation.

また、本発明の第2の発明の半導体装置の製造方法は、
半導体基板の表面にホトリソグラフィ技術によシ酸素イ
オン打込み用のマスクパターンを形成する工程と、該マ
スクパターンを介して酸素イオンを打込み素子分離用の
絶縁領域を形成する工程と、前記絶縁領域をエツチング
除去する工程と、前記エツチング除去された領域をCV
D酸化シリコンで埋める工程とを含んで構成される。
Further, the method for manufacturing a semiconductor device according to the second invention of the present invention includes:
A step of forming a mask pattern for implanting oxygen ions on the surface of a semiconductor substrate by photolithography technology, a step of implanting oxygen ions through the mask pattern to form an insulating region for element isolation, and a step of forming an insulating region for device isolation. a step of etching removal, and CVD of the etched area;
The structure includes a step of filling with D silicon oxide.

(実施例) 以下、本発明の実施例について、図面を参照して説明す
る。
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

第2図(al〜+f)は本発明の一実施例を説明するだ
めの工程順に示した断面図である。本実施例は次の工程
によ多構成される。
FIG. 2 (al to +f) is a sectional view showing an embodiment of the present invention in the order of steps. This embodiment consists of the following steps.

先ず、第2図(a)に示すように、半導体基板1の表面
を熱酸化しシリコン酸化膜12を形成する。
First, as shown in FIG. 2(a), the surface of the semiconductor substrate 1 is thermally oxidized to form a silicon oxide film 12.

次に、シリコン酸化膜12上にホトレジスト膜を形成し
、ホ)IJソグラフィ技術にょ夛分離領域に開孔部を持
つホトレジストパターン2′を形成すふ。
Next, a photoresist film is formed on the silicon oxide film 12, and (e) a photoresist pattern 2' having an opening in the isolation region is formed using IJ lithography technique.

次に、第2図1c)に示すように1ホトレジスト2′を
マスクとして、シリコン酸化膜に開孔部13を形成する
Next, as shown in FIG. 2 (c), an opening 13 is formed in the silicon oxide film using the photoresist 2' as a mask.

次に、第2図(d)K示すように、シリコン酸化膜のマ
スクパターン12の形成に使用したホトレジストパター
ン2を除去すると素子分離部に開孔を持つ酸化シリコン
膜iスクが形成できる。
Next, as shown in FIG. 2(d)K, when the photoresist pattern 2 used to form the silicon oxide film mask pattern 12 is removed, a silicon oxide film i-sk having openings in the element isolation portions can be formed.

次に、第2図telに示すように酸化シリコン膜12を
マスクとして酸素イオンを打込めば、打込み領域は酸化
シリコン14に変化し素子分離領域ができる。
Next, as shown in FIG. 2, oxygen ions are implanted using the silicon oxide film 12 as a mask, and the implanted region changes to silicon oxide 14 to form an element isolation region.

次に、第2図(fl忙示すように、マスクとした酸化シ
リコン膜12及び不要の酸化シリコンヲエッチング除去
すれば、素子分離用の酸化シリコン14′が埋込まれた
半導体基板1が完成する。
Next, as shown in FIG. 2 (fl), by etching away the silicon oxide film 12 used as a mask and the unnecessary silicon oxide, the semiconductor substrate 1 in which the silicon oxide 14' for element isolation is embedded is completed. .

なお、本実施例ではシリコン酸化膜を酸素イオン打込み
用マスクとして使用したが、ホトレジストで酸素イオン
の打込みに耐えるものが開発されれば、本発明はホトグ
ラフイエ程、酸素イオン打込み工程、レジスト除去T烏
の3T向で行らrシができ、より量産的な方法とするこ
とができる。
In this example, a silicon oxide film was used as a mask for oxygen ion implantation, but if a photoresist that can withstand oxygen ion implantation is developed, the present invention can be applied to the photolithography process, oxygen ion implantation process, and resist removal process. This can be done in the 3T direction, making it a more mass-producible method.

また、本発明による分離領域の形成にあたシ、シリコン
基板中への酸素イオン打込みによって生ずるシリコンが
酸化シリコンに変化するに伴って生ずる体積増加によシ
、シリコン基板中に発生する応力が問題となるが、これ
を少なくする方法としては熱処理を行うことによシ目的
が達せられるが、また、酸素イオン打込によって形成し
た応力発生源である酸化シリコンをエツチングによシ除
去し、しかる後従来例と同様にCVD酸化シリコンをエ
ツチング除去した溝に形成して溝を埋めることKよシよ
シ基板内の応力を減少させ、かつ本第1の発明の効果を
発揮することができる。
In addition, when forming the isolation region according to the present invention, stress generated in the silicon substrate is a problem due to the volume increase that occurs as silicon changes into silicon oxide due to oxygen ion implantation into the silicon substrate. However, as a method to reduce this, the objective can be achieved by performing heat treatment, but it is also possible to remove silicon oxide, which is a stress generation source, formed by oxygen ion implantation by etching, and then Similarly to the conventional example, by forming CVD silicon oxide in the etched grooves and filling the grooves, stress in the substrate can be reduced and the effects of the first invention can be exhibited.

(発明の効果) 以上説明したとおシ、本発明によれば、イオン打込みK
よシ素子分離領域を形成しているため、再現性、量産性
に富み、その領域の形状に対する自由度も大きくなる。
(Effects of the Invention) As explained above, according to the present invention, the ion implantation K
Since the device isolation region is formed in a straight line, it is highly reproducible and mass-producible, and the degree of freedom regarding the shape of the region is also increased.

従って、従来の溝堀シ法等と比較し非常に優れた素子分
離を行なうことができる。
Therefore, much better element isolation can be achieved compared to the conventional trench-horizon method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図Tal〜(g)は従来の素子分離法による半導体
装置の製造方法を説明するための工程順に示した断面図
、第2図(al〜(flは本発明の一実施例を説明する
ために工程順に示した断面図である。 1・・・・・・半導体基板、42′・・・・・・ホトレ
ジスト膜のパターン、3・・・・・・溝、4・・・・・
・CVD5102.4’・・曲溝を埋めたCvDsIo
2.5・・・・・・ホトレジスト膜、12・・・・・・
熱酸化膜、13・・・・・・熱酸化膜開孔部、14・・
・・・・イオン注入で形成された酸化シリコン、14′
・・・・・・素子分離用酸化膜。 阜1図 茅2f1
FIGS. 1A to 1G are cross-sectional views showing the order of steps for explaining a method for manufacturing a semiconductor device using a conventional element isolation method, and FIGS. 1. Semiconductor substrate, 42'... Photoresist film pattern, 3. Groove, 4.
・CVD5102.4'...CvDsIo with curved grooves filled
2.5...Photoresist film, 12...
Thermal oxide film, 13...Thermal oxide film opening, 14...
...Silicon oxide formed by ion implantation, 14'
...Oxide film for element isolation. Fu1zu 2f1

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板の表面にホトリソグラフィ技術によシ
酸素イオン打込用のマスクパターンを形成する工程と、
該マスクパターンを介して酸素イオンを打込み素子分離
用の絶縁領域を形成する工程とを含むことを特徴とする
半導体装置の製造方法。
(1) forming a mask pattern for oxygen ion implantation on the surface of the semiconductor substrate by photolithography;
A method for manufacturing a semiconductor device, comprising the step of implanting oxygen ions through the mask pattern to form an insulating region for element isolation.
(2)ホトリソグラフィ技術によシ酸素イオン打込用の
マスクパターンを形成する工程が、半導体基板表面に熱
酸化膜を形成する工程と、前記熱酸化膜をホトリソグラ
フィ技術によシバターン化する工程とを有することを特
徴とする特許請求の範囲第(1)項記載の半導体装置の
製造方法。
(2) The step of forming a mask pattern for oxygen ion implantation using photolithography technology is the step of forming a thermal oxide film on the surface of the semiconductor substrate, and the step of converting the thermal oxide film into a pattern using photolithography technology. A method for manufacturing a semiconductor device according to claim (1), comprising:
(3)半導体基板の表面にホトリソグラフィ技術によシ
酸素イオン打込み用のマスクパターンを形成する工程と
、該マスクパターンを介して酸素イオンを打込み素子分
離用の絶縁領域を形成する工程と、前記絶縁領域をエツ
チング除去する工程と、CVD酸化シリコンでエツチン
グ除去すれた領域を埋める工程とを含むことを特徴とす
る半導体装置の製造方法。
(3) forming a mask pattern for implanting oxygen ions on the surface of the semiconductor substrate by photolithography; and implanting oxygen ions through the mask pattern to form an insulating region for element isolation; 1. A method of manufacturing a semiconductor device, comprising the steps of etching away an insulating region and filling the etched region with CVD silicon oxide.
JP376384A 1984-01-12 1984-01-12 Manufacture of semiconductor device Pending JPS60147132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP376384A JPS60147132A (en) 1984-01-12 1984-01-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP376384A JPS60147132A (en) 1984-01-12 1984-01-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60147132A true JPS60147132A (en) 1985-08-03

Family

ID=11566207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP376384A Pending JPS60147132A (en) 1984-01-12 1984-01-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60147132A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01179431A (en) * 1988-01-06 1989-07-17 Toshiba Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01179431A (en) * 1988-01-06 1989-07-17 Toshiba Corp Manufacture of semiconductor device

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