JPH02203549A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of stress in an active region by a method wherein, after a comparative thick oxide film is formed on a semiconductor substrate, and an isolation trench is formed, a silicon nitride film is deposited on the whole surface, a crystal silicon film is buried in the isolation trench, and the surface is oxidized. CONSTITUTION:After a buried layer 12, an epitaxial layer 13, and a thermal oxide layer 14 are formed on a semiconductor substrate 11, an element isolation trench 15 is formed by dry etching. An oxide film 16 is formed, and a channel stopper region 17 is formed by ion-implanting high concentration boron. At this time, a silicon nitride film 18 is deposited; a polycrystalline silicon film 19 is deposited; the polycrystalline silicon film 19 except the isolation trench is eliminated by etching; the polycrystalline silicon film 19 is buried only in the isolation trench 15. Next, an oxide film 20 is formed on the surface; by using the silicon nitride film 18, an oxide film 20 is formed only in the isolation trench 15, thereby obtaining an element isolation structure having no recess in the vicinity of the surface, and obtaining a state where stress is scarcely applied in an active region 21 after element isolation process is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a method of manufacturing a semiconductor device, particularly a method of forming an isolation region of a semiconductor device.

Conventional technology Conventionally, as a method for forming element isolation regions in the manufacture of semiconductor devices, the area to be the element isolation region is etched to form a groove, the inside of the groove is oxidized, and a polycrystalline silicon film is buried in the groove. After that, there is a method of selectively oxidizing the groove surface and the vicinity of the groove to form an element isolation region. An example of the prior art will be explained with reference to FIG.

A silicon oxide film (SiO2) is formed on a semiconductor substrate (Si) 1.
) 2. After forming the silicon nitride film (S 13Na) 3, etching is performed using the resist as a mask to form the isolation trench 4.
form. (FIG. 2(a)) After removing the resist, the inner surface of the trench is oxidized to form an oxide film 5. After that, impurity ions are implanted to form a channel stopper 6 at the bottom of the substrate recess, and a polycrystalline silicon film 7 is deposited on the entire surface of the substrate. The film 7 is removed, and the polycrystalline silicon film 7 is buried only in the substrate recess (FIG. 2(b)).Then, the silicon nitride film 3 is patterned using a photomask, and the upper part of the trench and the vicinity of the trench are patterned. A surface oxide film 8 is formed by thermal oxidation to complete an element isolation region. (FIG. 2(C)) Problems to be Solved by the Invention In the conventional example, when forming the surface oxide film 8, the polycrystalline silicon film 7 near the oxide film in the trench and the semiconductor substrate silicon l are By the way, oxidation progresses faster than other parts, and vertical birds beak occurs in this part.
g occurs. (Figure 2 (C)) This vertica
The problem is that due to the occurrence of birds beak, large compressive stress is generated in the active region surrounded by the isolation trench, causing crystal defects in the silicon of the active region and increasing leakage current when devices are formed. A point occurred.

In addition, as semiconductor devices become finer, this vert
The compressive stress in the active region due to the ical birds peak becomes large, making it impossible to form fine semiconductor devices.

Furthermore, when embedding the polycrystalline silicon film 7 in the isolation trench, it is very difficult to bury it so that it is at the same height as the surface of the semiconductor substrate l. When the surface of the isolation trench is oxidized, the isolation trench becomes depressed compared to the surrounding area, resulting in disconnection of the AI wiring or damage to the AI during etching.
The problem of short circuit caused by the remaining parts also occurred.

Means for Solving the Problems The present invention was made in view of the above problems, and consists of forming a relatively thick oxide film on the surface of a semiconductor substrate, forming an isolation trench, depositing a silicon nitride film on the entire surface, and then performing isolation. A crystalline silicon film is buried in the trench, and the surface is oxidized to an optimal film thickness.

A relatively thick oxide film is formed on a working semiconductor substrate, and using a resist as a mask, the oxide film and the semiconductor substrate are etched to form isolation trenches. At this time, tensile stress is generated in the active region surrounded by the isolation trench. After this, an oxide film is formed on the surface inside the isolation trench, a silicon nitride film is deposited, a polycrystalline silicon film is buried, and thermal oxidation is carried out to the optimum film thickness. Therefore, the oxide film is formed only on the upper part of the isolation trench, and the
tical birds beak does not occur. At this time, moderate compressive stress is applied to the active region surrounded by the isolation trench due to deposition expansion caused by oxidation of the polycrystalline silicon film, and after the element isolation process, there is almost no stress in the active region. It will not take longer. In this case, even if the area surrounded by the separation groove becomes smaller,
The effects of the stress generated by the initially formed oxide film and the thermal oxidation of the isolation enhancement portion are balanced, and no stress is generated in the active region.

In addition, since a thermal oxide film is formed only on the upper part of the isolation trench,
A flat element isolation structure can be obtained without creating a depression in the isolation groove portion.

Embodiment One embodiment of the present invention will be explained along the process diagram shown in FIG. On the P-type Si substrate 11, an n" buried layer I2, for example, an n-type epitaxial layer 13 with a thickness of 2 μm, is formed, and a thermal oxide film 14 with a thickness of, for example, 600 nm is formed. After this,
Dry etching is performed using a photoresist as a mask, and the Si substrate 11 is dug to a depth of approximately 37 zm, and the element isolation grooves 15 are etched.
form.

(FIG. 1(a)) Next, the bottom and side surfaces of the trench are oxidized to form an oxide film 16 of approximately 110 mm.
A channel stopper region 17 is formed at the bottom of the trench 15 by implanting high concentration boron ions into the bottom of the isolation trench. After this, a silicon nitride film 18 is deposited to a thickness of about 120 nm as an oxidation prevention film, and a polycrystalline silicon film 19 is deposited to a thickness of about 2 μm.
m is deposited, and the polycrystalline silicon film 19 other than the isolation trench is removed by dry etching or wet etching, and the polycrystalline silicon film 19 is deposited only in the isolation trench so that the level difference from the surface is as small as possible. Embed.

(Fig. 1(b)) Next, when an oxide film 20 with a thickness of 600 nm is formed on the surface, since there is a silicon nitride film which is an oxidation prevention film, the oxide film is formed only in the isolation trenches. As a result, it is possible to create an element isolation structure with no depressions on the surface. (Figure 1 (C)
) At this time, since no vertical birds beak occurs, no large compressive stress is applied to the active region 21, and the compressive stress applied to the active region 21 when the surface of the polycrystalline silicon film 19 is oxidized and the thick thermal oxidation on the active region 21 are reduced. The tensile stress applied to the active region 21 is balanced by the film 14, and almost no stress is applied to the active region 21.

In other words, during this element isolation process, the stress generated in the active region 21 is 600 nm when the isolation trench 15 is formed.
The thermal oxide film of m changes to cancel out the tensile stress generated in the active region 21, and after the element isolation process is completed, the active region 21 is in a state where almost no stress is applied. Crystal defects are less likely to occur in this region, and leakage current caused by crystal defects is reduced, making it possible to fabricate semiconductor devices in this region.

Furthermore, even if the active region is miniaturized, the stress applied to the active region will continue to be applied so that the tensile stress and the compressive stress balance each other out.As a result, very small stress will be applied to the active region. Therefore, it becomes possible to fabricate a fine semiconductor element in this portion.

Effects of the Invention As described above, according to the present invention, the stress applied to the active region by the element isolation process can be extremely reduced even when the active region is small, so that it is possible to reduce the stress applied to the active region by the device isolation process. and)
It is now possible to form a microelectrode in the active region, and since there are no depressions in the isolation trench, there is no disconnection or short circuit of AI wiring, etc. Furthermore, since a thick thermal oxide film is used, the wiring can be easily formed. This reduces the capacity and greatly contributes to the production of high-density, high-speed, and high-yield semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the process of forming an isolation structure according to an embodiment of the present invention, and FIG. 2 is a sectional view of the process of forming an isolation structure in a conventional example. 11... Semiconductor substrate, 12... Buried layer, 13.
...Epitaxial layer, 14...Thermal oxide film, 15.
... Separation layer, 16... Oxide film, 17... Channel stopper region, 18... Silicon nitride film, 19...
・Polycrystalline silicon film, 20... Thermal oxide film, 21...
active area. Name of agent: Patent attorney Shigetaka Awano Haka 1 person 1st I! i
l!

Claims (2)

[Claims] (1) a step of forming an insulating film on a semiconductor substrate; a step of selectively etching the insulating film and the semiconductor substrate to form a recess; a step of forming an oxide film of a predetermined thickness in the recess; After forming an oxide film in the recess, depositing an oxidation prevention film; depositing a semiconductor thin film on the oxidation prevention film; and selectively removing the semiconductor thin film, leaving the semiconductor thin film only in the recess. 1. A method of manufacturing a semiconductor device, the method comprising the step of: an insulating film on the surface of the substrate having a thickness substantially equal to a thickness of an insulating film on the recess. (2) The method for manufacturing a semiconductor device according to claim 1, wherein a polycrystalline silicon film is used as the semiconductor thin film.