KR0172724B1 - Method of manufacturing field oxide film on the semiconductor device - Google Patents
Method of manufacturing field oxide film on the semiconductor device Download PDFInfo
- Publication number
- KR0172724B1 KR0172724B1 KR1019950069458A KR19950069458A KR0172724B1 KR 0172724 B1 KR0172724 B1 KR 0172724B1 KR 1019950069458 A KR1019950069458 A KR 1019950069458A KR 19950069458 A KR19950069458 A KR 19950069458A KR 0172724 B1 KR0172724 B1 KR 0172724B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- trench
- field oxide
- forming
- silicon substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
본 발명은 반도체 소자의 필드 산화막 형성방법에 관한 것으로서, 특히 넓은 활성 영역을 확보하면서 반도체 기판과의 단차를 완화시키기 위한 트렌치 형태의 필드 산화막 형성방법에 관한 것으로, 실리콘 기판상에 산화막을 형성하는 단계; 산화막에 상부에 감광막 패턴을 형성하는 단계; 감광막 패턴을 이용하여 비등방성 식각하여 각각의 트렌치 및 트렌치 사이의 돌출 부위를 형성하는 단계; 감광막을 제거하는 단계; 결과물 상부에 채널 스톱용 불순물을 이온주입하는 단계; 노출된 기판 표면을 열산화하여 열산화막을 형성하는 단계; 열산화막을 실리콘 기판이 노출되도록 화학-기계적 연마하여 필드 산화막을 형성하는 단계를 포함한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a field oxide film of a semiconductor device, and more particularly, to a method of forming a field oxide film in a trench form for alleviating a step with a semiconductor substrate while securing a wide active area. ; Forming a photoresist pattern on the oxide film; Anisotropic etching using the photoresist pattern to form protrusions between each trench and the trench; Removing the photoresist film; Ion implanting an impurity for channel stop on top of the result; Thermally oxidizing the exposed substrate surface to form a thermal oxide film; Chemically and mechanically polishing the thermal oxide film to expose the silicon substrate to form a field oxide film.
Description
제1도 (a) 내지 (b)는 종래의 반도체 소자의 필드 산화막 형성방법을 설명하기 위한 단면도.1A to 1B are cross-sectional views for explaining a method of forming a field oxide film of a conventional semiconductor device.
제2도 (a) 내지 (d)는 본 발명의 실시예 1에 따른 반도체 소자의 필드 산화막 형성방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views for explaining a method for forming a field oxide film of a semiconductor device according to Embodiment 1 of the present invention.
제3도 (a) 내지 (d)는 본 발명의 실시예 2에 따른 반도체 소자의 필드 산화막 형성방법을 설명하기 위한 단면도.3A to 3D are cross-sectional views for explaining a method for forming a field oxide film of a semiconductor device according to Embodiment 2 of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 21 : 실리콘 기판 12, : 열산화막11, 21 silicon substrate 12, thermal oxide film
13, 23 : 트렌치 15, 14 : 열산화막13, 23: trench 15, 14: thermal oxide film
16, 25 : 필드 산화막16, 25: field oxide film
본 발명은 반도체 소자의 필드 산화막 형성방법에 관한 것으로서, 특히 넓은 활성 영역을 확보하면서 반도체 기판과의 단차를 완화시키기 위한 트렌치 형태의 필드 산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a field oxide film of a semiconductor device, and more particularly, to a method for forming a field oxide film in a trench form to reduce a step with a semiconductor substrate while securing a wide active area.
일반적으로, 반도체 회로 제조시 중요한 하나의 단게는 소자간의 분리에 있으며, 여기서는 접합 분리방법, 산화 분리방법, 및 트렌치 분리방법등이 있고, 이 중에서 공정의 편의와 우수한 격리 특성 및 반도체 기판과의 산화 마스크로 질화막을 이용할 수 있는 산화 분리방법, 특히 소자 사이에 두껍고 일렬로 늘어선 산화물층을 제공하는 LOCOS(LOCal Oxidation of Silicon:이하 LOCOS라 칭함) 공정이 주로 사용되어 있다.In general, one important step in the fabrication of semiconductor circuits is separation between devices, including junction separation, oxide separation, and trench isolation, among which process convenience and excellent isolation characteristics and oxidation with semiconductor substrates. Oxide separation methods that can utilize nitride films as masks, in particular LOCOS (LOCal Oxidation of Silicon) processes, which provide thick, lined oxide layers between devices, are mainly used.
제1도의 (a)는 종래의 반도체 산화 분리방법에 의한 필드 산화막 형성후의 단면도로서, 이를 통하여 종래 기술을 살펴보면 다음과 같다.FIG. 1 (a) is a cross-sectional view after the field oxide film is formed by the conventional semiconductor oxide separation method.
실리콘 기판(1)에 패드 산화막(2)과 질화막(3)을 형성한 다음, 상기 질화막(3) 및 패드 산화막(2)을 선택적으로 식각하여 필드 산화막 형성 영역의 상기 실리콘 기판(1)을 노출시킨 다음, 열산화 공정을 통해 필드 산화막을 형성하는 방법이다.After forming the pad oxide film 2 and the nitride film 3 on the silicon substrate 1, the nitride film 3 and the pad oxide film 2 are selectively etched to expose the silicon substrate 1 in the field oxide film formation region. After that, a field oxide film is formed through a thermal oxidation process.
상기와 같은 종래 기술은 도면에서 알 수 있는 바와같이, 질화막 하부로 필드 산화막이 침투하면서 새부리 형상이 유발됨으로 인해 활성 영역이 감소되는 단점이 있다.As can be seen in the drawing, the prior art has a disadvantage in that the active area is reduced due to the beak shape as the field oxide film penetrates under the nitride film.
제1도의 (b)는 상기 열산화막에 의한 문제점을 해결하기 위한 종래의 다른 방법인 트랜치 형태의 필드 산화막 형성 후의 단면도로서, 도면부호 1은 실리콘 기판, 4'은 필드 산화막, L은 트랜치 영역의 폭, H는 트렌치 영역의 깊이를 나타낸다.FIG. 1B is a cross-sectional view after forming a trench type field oxide film, which is another conventional method for solving the problem caused by the thermal oxide film, in which 1 is a silicon substrate, 4 'is a field oxide film, and L is a trench region The width, H, represents the depth of the trench region.
상기 트렌치 구조의 필드 산화막은 활성 영역이 감소되는 문제를 어느정도 개선할 수는 있지만, 트렌치 영역의 폭에 대한 깊이의 비(L/H)인 종횡비(aspect ratio)에 따라 매립 상태가 결정되며, 종횡비가 다른 트렌치가 동일한 기판내에 형성될 경우, 필드 산화막의 폭과 깊이도 달라지는 문제점이 따른다.Although the field oxide film of the trench structure may somewhat improve the problem of reducing the active region, the buried state is determined according to an aspect ratio, which is a ratio of depth to width of the trench region (L / H). If different trenches are formed in the same substrate, there is a problem that the width and depth of the field oxide film also vary.
상기와 같은 종래의 문제점을 해결하기 위해 안출된 본 발명은, 열공정으로 인한 활성 영역의 침투를 방지하면서, 종횡비가 서로 다른 트렌치 영역이 형성된 실리콘 기판에 일정 폭의 필드 산화막을 형성할 수 있는 반도체 소자의 필드 산화막 형성방법을 제공하는데 그 목적이 있다.Disclosed is a semiconductor capable of forming a field oxide film having a predetermined width on a silicon substrate in which trench regions having different aspect ratios are formed while preventing penetration of an active region due to a thermal process. It is an object of the present invention to provide a method for forming a field oxide film of a device.
상기와 같은 본 발명의 목적을 달성하기 위해 본 발명은, 실리콘 기판상에 산화막을 형성하는 단계; 상기 산화막에 상부에 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 이용하여 비등방성 식각하여 각각의 트렌치 및 트렌치 사이의 돌출 부위를 형성하는 단계; 상기 감광막을 제거하는 단계; 상기 결과물 상부에 채널스톱용 불순물을 이온주입하는 단계; 상기 노출된 기판 표면을 열산화하여 열산화막을 형성하는 단계; 상기 열산화막을 실리콘 기판이 노출되도록 화학-기계적 연마하여 필드 산화막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention to achieve the above object of the present invention, forming an oxide film on a silicon substrate; Forming a photoresist pattern on the oxide layer; Anisotropic etching using the photoresist pattern to form protrusions between the trenches and the trenches; Removing the photosensitive film; Ion implanting an impurity for channel stop on the result; Thermally oxidizing the exposed substrate surface to form a thermal oxide film; And chemically-mechanically polishing the thermal oxide film to expose a silicon substrate to form a field oxide film.
이하, 본 발명의 바람직한 실시에를 첨부도면에 의거하여 상세히 설명한다.BEST MODE Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[실시예1]Example 1
제2도의 (a) 내지 (d) 및 제3도는 본 발명의 실시예 1에 따른 필드 산화막 형성과정을 나타내는 단면도이다.2A to 3D and FIG. 3 are cross-sectional views illustrating a process of forming a field oxide film according to Embodiment 1 of the present invention.
먼저, 제2도의 (a)에 도시된 바와같이, 실리콘 기판(11)상에 약 300 내지 500Å의 두께로 산화막(12)을 형성한 다음, 소정의 감광막(13) 패턴을 형성하고, 상기 감광막(13)을 식각 마스크로 하여 비등방성 식각하므로써, 실리콘 기판(11)에 약 0.5 내지 1.2㎛의 깊이를 갖는 트렌치(14)를 형성한다. 여기서, 상기 트렌치(14)에 의해 형성될 필드 산화막의 최소폭이 3a일 경우, 트렌치의 폭이 a가 되고 각각의 트렌치 사이로 돌출된 부위, 즉 실리콘 기판 섬(island)의 폭도 a가 되도록 형성한다.First, as shown in FIG. 2A, an oxide film 12 is formed on the silicon substrate 11 to a thickness of about 300 to 500 kV, and then a predetermined photoresist film 13 pattern is formed, and the photoresist film is formed. By anisotropic etching using (13) as an etching mask, the trench 14 having a depth of about 0.5 to 1.2 mu m is formed in the silicon substrate 11. Here, when the minimum width of the field oxide film to be formed by the trench 14 is 3a, the width of the trench is a and the portion protruding between the trenches, that is, the width of the silicon substrate island is formed to be a. .
이때, 제2도와 같이 동일한 실리콘 기판(11)내에서 형성될 필드 산화막의 폭이 서로 달라서 최소폭 3a보다 큰 경우에는, 복수개의 실리콘 기판 섬이 형성되도록 한다.At this time, when the widths of the field oxide films to be formed in the same silicon substrate 11 are different from each other and larger than the minimum width 3a, a plurality of silicon substrate islands are formed.
이어서, 제2도의 (b)에서, 상기 감광막(13)을 제거한 다음에, 약 5 내지 20°정도 기울여서 채널스톱용으로 BF2불순물을 20 내지 50 KeV, 1×1012내지 1×1017원자/㎤의 조건으로 상기 트렌치(14) 내부에 2회 반복하여 이온주입한다. 이때, 상기 산화막(12)이 이온주입 저지층 역할을 한다.Subsequently, in FIG. 2 (b), after removing the photoresist film 13, the substrate is tilted by about 5 to 20 degrees, and 20 to 50 KeV, 1 × 10 12 to 1 × 10 17 atoms of BF 2 impurities are used for the channel stop. Ion implantation is repeated twice in the trench 14 under the condition of / cm 3. In this case, the oxide film 12 serves as an ion implantation blocking layer.
다음으로, 제2도의 (c)에서, 공지의 열산화법으로 트렌치(14) 내부를 포함한 실리콘 기판(11)에 약 2a의 두께를 갖는 열산화막(15)을 형성한다. 상기 열산화막(15)으로 트렌치(14)가 매립되도록 한다.Next, in Fig. 2C, a thermal oxide film 15 having a thickness of about 2a is formed on the silicon substrate 11 including the trench 14 by a known thermal oxidation method. The trench 14 is buried in the thermal oxide film 15.
마지막으로, 제2도의 (d)와 같이, 강산의 슬러리를 이용한 화학-기계적 연마법으로 상기 실리콘 기판(11)이 노출되도록 상기 열산화막(15)을 연마하여 필드 산화막(16)을 형성한다.Finally, as shown in (d) of FIG. 2, the thermal oxide film 15 is polished to expose the silicon substrate 11 by a chemical-mechanical polishing method using a slurry of strong acid to form a field oxide film 16.
[실시예 2]Example 2
제3도의 (a) 내지 (d)는 본 발명의 실시예 2에 따른 필드 산화막 형성과정을 나타낸 단면도이다.3A to 3D are cross-sectional views illustrating a process of forming a field oxide film according to Embodiment 2 of the present invention.
먼저, 제3도의 (a)에 도시된 바와같이, 실리콘 기판(21)상에 소정의 감광막(22) 패턴을 형성하고, 상기 감광막(22)을 식각 마스크로 하여 비등방성 식각하므로써, 실리콘 기판(21)에 약 0.5 내지 1.2㎛의 깊이를 갖는 트렌치(23)를 형성한다. 여기서 상기 트렌치(23)에 의해 형성될 필드 산화막의 최소폭이 3a일 경우, 트렌치의 폭이 a가 되고 각각의 트렌치 사이로 돌출된 부위, 즉 실리콘 기판 섬(island)의 폭도 a가 되도록 형성한다.First, as shown in FIG. 3A, a predetermined photosensitive film 22 pattern is formed on the silicon substrate 21, and anisotropic etching is performed using the photosensitive film 22 as an etching mask, thereby forming a silicon substrate ( 21 to form a trench 23 having a depth of about 0.5 to 1.2 μm. In this case, when the minimum width of the field oxide film to be formed by the trench 23 is 3a, the width of the trench becomes a and the portion protruding between each trench, that is, the width of the silicon substrate island is formed to be a.
이때, 상기 실시예 1에서 제시된 도면인 제3도와 같이 동일한 실리콘 기판(21)내에서 형성될 필드 산화막의 폭이 서로 달라서 최소폭 3a보다 큰 경우에는, 복수개의 실리콘 기판 섬이 형성되도록 한다.In this case, when the widths of the field oxide films to be formed in the same silicon substrate 21 are different from each other as shown in FIG. 3, the plurality of silicon substrate islands are formed.
이어서, 제3도의 (b)에서, 채널스톱용으로 BF2불순물을 20 내지 50 KeV, 1×1012내지 1×1017원자/㎤의 조건으로 상기 트렌치(23) 내부에 이온주입한다. 이때, 상기 감광막(22)이 이온주입 저지층 역할을 한다.Next, in FIG. 3B, BF 2 impurities are implanted into the trench 23 under the conditions of 20 to 50 KeV and 1 × 10 12 to 1 × 10 17 atoms / cm 3 for channel stop. At this time, the photosensitive film 22 serves as an ion implantation blocking layer.
다음으로, 제3도의 (c)에서, 상기 감광막(22)을 제거한 다음에, 공지의 열산화법으로 트렌치(23) 내부를 포함한 실리콘 기판(21)에 약 2a의 두께를 갖는 열산화막(24)을 형성한다. 상기 열산화막(24)으로 트렌치(23)가 매립되도록 한다.Next, in FIG. 3C, after removing the photosensitive film 22, the thermal oxide film 24 having a thickness of about 2 a is formed on the silicon substrate 21 including the trench 23 by a known thermal oxidation method. To form. The trench 23 is buried in the thermal oxide film 24.
마지막으로, 제3도의 (d)와 같이, 강산의 슬러리를 이용한 화학-기계적 연마법으로 상기 실리콘 기판(21)이 노출되도록 상기 열산화막(24)을 연마하여 필드 산화막(25)을 형성한다.Finally, as shown in FIG. 3D, the thermal oxide film 24 is polished to expose the silicon substrate 21 by chemical-mechanical polishing using a slurry of strong acid to form a field oxide film 25.
즉, 실시예 1에서는 실리콘 기판(11)에 산화막(12)을 형성하고, 이 산화막(12)을 이온주입 저지층으로 이용하는 반면에, 실시예 2에서는 산화막을 형성하지 않고, 감광막(22)을 이온주입 저지층으로 이용하는 차이가 있다.That is, in Example 1, an oxide film 12 is formed on the silicon substrate 11, and the oxide film 12 is used as an ion implantation blocking layer. In Example 2, the photosensitive film 22 is not formed but an oxide film is formed. There is a difference in use as an ion implantation blocking layer.
이와 같이 본 발명은 질화막을 사용하지 않으므로 미립자의 발생에 의한 실리콘 기판의 오염을 줄일 수 있으며, 또한 활성 영역이 충분히 확보되어 반도체 소자의 집적도 및 전기적 특성이 향상되는 효과가 있다.As described above, since the present invention does not use a nitride film, contamination of the silicon substrate due to the generation of fine particles can be reduced, and an active region is sufficiently secured, thereby improving the integration degree and electrical characteristics of the semiconductor device.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069458A KR0172724B1 (en) | 1995-12-30 | 1995-12-30 | Method of manufacturing field oxide film on the semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069458A KR0172724B1 (en) | 1995-12-30 | 1995-12-30 | Method of manufacturing field oxide film on the semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053482A KR970053482A (en) | 1997-07-31 |
| KR0172724B1 true KR0172724B1 (en) | 1999-03-30 |
Family
ID=19448456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950069458A KR0172724B1 (en) | 1995-12-30 | 1995-12-30 | Method of manufacturing field oxide film on the semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172724B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180001513U (en) | 2016-11-14 | 2018-05-24 | 김진형 | Zipper pulls |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100675892B1 (en) * | 2005-05-06 | 2007-02-02 | 주식회사 하이닉스반도체 | Method for forming isolation area of semiconductor device and semiconductor device thereby |
-
1995
- 1995-12-30 KR KR1019950069458A patent/KR0172724B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180001513U (en) | 2016-11-14 | 2018-05-24 | 김진형 | Zipper pulls |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053482A (en) | 1997-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100213196B1 (en) | Trench device separation | |
| US6174784B1 (en) | Technique for producing small islands of silicon on insulator | |
| KR100252751B1 (en) | Semiconductor element manufacturing method | |
| JP2802600B2 (en) | Method for manufacturing semiconductor device | |
| US5733813A (en) | Method for forming planarized field isolation regions | |
| KR19980034499A (en) | Isolation Area Formation Method | |
| KR19980029023A (en) | Method of forming an isolation region of a semiconductor device | |
| JP3407023B2 (en) | Method for manufacturing semiconductor device | |
| KR0172724B1 (en) | Method of manufacturing field oxide film on the semiconductor device | |
| KR100582147B1 (en) | Semiconductor ic apparatus and method for fabricating the same | |
| JPS60198841A (en) | Element isolation of semiconductor device | |
| KR100204417B1 (en) | Method for forming an element isolation in a semiconductor device | |
| US5952707A (en) | Shallow trench isolation with thin nitride as gate dielectric | |
| US5668043A (en) | Method for forming isolated regions in a semiconductor device | |
| KR100204416B1 (en) | Method for forming an element isolation in a semiconductor device | |
| KR100204418B1 (en) | Method for forming an element isolation in a semiconductor device | |
| KR100312656B1 (en) | Method for fabricating bc-soi device | |
| KR100232198B1 (en) | Method of forming an element isolation region in a semiconductor device | |
| KR0161727B1 (en) | Element isolation method of semiconductor device | |
| KR0144026B1 (en) | Forming method of element isolation | |
| KR0148611B1 (en) | Formation method of element isolation layer for semiconductor devices | |
| KR100195227B1 (en) | Isolation method in semiconductor device | |
| KR100205339B1 (en) | Method for forming isolation region of semiconductor device | |
| KR100239669B1 (en) | Mask of field oxidation in semiconductor device and method of manufacturing the same | |
| KR0172545B1 (en) | Method of manufacturing isolation film on the semiconductor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20120924 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20130916 Year of fee payment: 16 |
|
| FPAY | Annual fee payment |
Payment date: 20140917 Year of fee payment: 17 |
|
| EXPY | Expiration of term |