JPS6358852A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a complete isolation structure in a simple process which is the strong point of an anode formation method by a method wherein grooves, which penetrate an N-type semiconductor layer and reach a P-type semiconductor layer, are formed and after the grooves are filled with a P-type semiconductor, an anode formation treatment is performed, the whole region of the P-type semiconductor and the P-type semiconductor layer just under the N-type semiconductor layer are covered into a porous semiconductor layer and the porous semiconductor layer is converted into an oxide film. CONSTITUTION:Opening parts 26 are provided in a nitride film 25 and an oxide film 24 for buffering, grooves 27 to reach a P-type Si substrate 21 are formed, a P-type poly Si layer 28 is deposited to fill the grooves 27, the poly Si layer 28 is etched back and the poly Si layer 28 is made to remain only in the interiors of the grooves 27. Then, the P-type poly Si layer 28 and the P-type Si substrate 21 are converted into a porous Si layer 29. Then, the porous Si layer 29 is converted into a porous Si oxide film 30 using the nitride film 25 as a mask, the nitride film 25 and the oxide film 24 for buffering are removed and an n-type element forming region 31 consisting of an n<+> buried diffusion layer 22 and an n<-> epitaxial layer 23 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to an element iv.

(Prior art) The element size of a non-polar type semiconductor integrated circuit device was originally achieved by using the PN junction separation method, but as the elements become smaller and the viscosity increases, it becomes necessary to reduce the number of separation regions. This led to a transition to an oxide film separation method using silicon oxide Dk, the so-called isoplanar method.

The oxide film isolation method not only significantly reduces the isolation area compared to the PN junction isolation method, but also converts all areas other than the element formation area into a thick oxide film, which reduces the stray capacitance between the wiring and the substrate. This was an effective method that also contributed to speeding up the process.

However, in recent years, there has been an increasing demand for higher speed devices, and studies are being conducted to reduce the parasitic capacitance fAk, which is an impediment to higher speeds, as much as possible.

Regarding element isolation technology, parasitic capacitance between substrate and collector1
In order to reduce F, it is effective to increase the speed by creating a complete isolation structure in which not only the sides but also the bottom of the element are separated by an insulator.

Completely separated structure? As a step toward realization, half-core transistor research 5SD79-95. As disclosed in pages 45 to 54, a method has been proposed in which a porous silicon layer is formed in a silicon substrate by an anodization method and a porous silicon oxide film obtained by oxidizing the layer is utilized.

In the anodization method, porous silicon is formed by hole current in silicon, so by forming the anodization current in an appropriate path, porous silicon can be formed anywhere in the silicon substrate. It is possible to form

FIG. 2 shows, as an example of the prior art, a cross-sectional view of the steps taken to obtain a complete separation structure when a complete separation technique using an anodization method is applied to a pie-bola denomination chair.

First, as shown in FIG. 2(A), a P-type silicon substrate 1
0 on the surface of the area where the transistor is to be formed? After forming the type buried diffusion layer 2, a V-type epitaxial layer 3 is formed on the entire surface. Furthermore, a buffer oxide film 4 is formed on the entire surface of the N'''' type epitaxial layer 3. A silicon nitride film (hereinafter referred to as nitride film) 5 is sequentially formed.

Next, as shown in FIG. 2(B), an opening 6 is formed in the silicon nitride film 5 and the buffer oxide film 4 by ordinary photolithography, and the opening 6 is completely passed through. A P+ type impurity is diffused into the type epitaxial layer 3 to completely form the door type diffusion layer 7. This P-type diffusion N7 needs to be diffused deeply until it reaches at least the P-type silicon substrate 1vC.

Next, as shown in FIG.
1 and 2 in a hydrofluoric acid aqueous solution 12 and a power supply 13t connected between them, anodizing treatment was performed in the hydrofluoric acid aqueous solution 12, as shown in FIG. 2(C). A porous silicon layer 8 as shown is formed. Here, the anodization reaction is a common phenomenon caused by an electrochemical reaction of silicon, and the reaction progresses selectively in the P-type silicon region due to the action of holes in the semiconductor. Therefore, (
When the anodization treatment is performed on the structure 14, the anodization reaction proceeds from the opening 6 into the P-type diffusion layer 7 and further spreads into the P-type silicon substrate 1 along the path of the anodization current. Here, anodization treatment is performed until the entire bottom surface of the N-type buried diffusion layer 2 is made porous.
The structure shown in FIG. 2(c) is obtained in which the + type diffusion layer 7 and the surface side of the P type silicon substrate 1 are converted into a porous silicon layer 8.

Thereafter, porous silicon layer 8 is oxidized using nitride film 5 as a mask to obtain porous silicon oxide film 9 as shown in FIG. 2(D). At this time, since the effective surface area of the porous silicon layer 8 is very large, the oxidation rate is extremely fast. Even the bottom surface of 2 can be easily converted into oxide film 9. In addition, by controlling the porous density during anodization treatment, it is possible to absorb the volume increase due to oxidation, and the shape before oxidation is preserved even after oxidation, eliminating the step difference that is usually a problem with selective oxidation. The occurrence of this can be completely avoided.

Thereafter, as shown in FIG. 2(D), the nitride film 5 and the buffer oxide film 4 are removed, and the furnace-type buried diffusion layer 2 and the N-type epitaxial layer thereon are removed. 3 is completely separated by the porous silicon oxide film 9, resulting in a completely isolated structure as shown in FIG. 2(D).

As described above, it can be said that the complete separation method using a porous silicon layer formed by anodization is an effective method with a relatively simple process.

(Problems to be Solved by the Invention) However, in the above-mentioned conventional technology, since the P+ type is completely diffused into the epitaxial layer 3 having a thickness of 1 to 3 μm, the lateral diffusion of the door-shaped diffusion layer 7 is large, and the photoetching Since it is necessary to form the N+ type buried diffusion layer 2 using the method, it is necessary to allow for mask alignment allowance when forming the opening 6 for P type diffusion.
However, there is a problem in that there is a limit to the reduction of the isolation region width.

The present invention is a semiconductor integrated circuit device that completely eliminates the problems of the conventional technology that it is difficult to miniaturize the isolation region as described above, and realizes a completely isolated structure with a simple process that is a feature of the anodization method. The purpose is to provide complete manufacturing methods.

(Means for Solving the Problems) The present invention provides a method for using a semiconductor integrated circuit device having a completely isolated structure.
After forming a groove that penetrates the N-type semiconductor layer and reaches the P-type semiconductor layer in a selected region of the type semiconductor layer, and filling the groove with the P-type semiconductor, the P-type semiconductor and the P-type semiconductor layer are formed. Anodization maturation 3t' is performed to convert the entire region of the P-type semiconductor and the P-type semiconductor layer immediately below the N-type semiconductor layer or the entire region of the P-type semiconductor layer into a porous semiconductor layer, and the porous semiconductor layer is converted into an oxide film.

(Function) In such a method, the width of the element isolation region is determined by the grooves formed in the N-type and P-type semiconductor layers. In addition, since the three-layered portion is removed by forming the groove, a buried diffusion layer can be formed as a part of the N-type semiconductor layer on the entire surface of the P-type semiconductor layer, and as a result, the above-mentioned There is no need to consider mask alignment allowance when forming grooves.

(Example of a Practical Hakama) Hereinafter, an embodiment of a method for advancing a semiconductor integrated circuit device according to the present invention will be described with reference to the drawings. Figure 1 (A) - (
G) is a process sectional view of one embodiment.

One example of this illustration is this F! Although the present invention is applied to a bipolar type semiconductor integrated circuit device, the scope of application of the present invention is not limited thereto, and can also be applied to MOS type and other semiconductor integrated circuit devices.

First, in FIG. 1(A), an N+ type buried diffusion layer 22 with a thickness of 1 to 2 μm is formed on the entire surface of a P type silicon substrate 21, and an N− type epitaxial layer 23 with a thickness of 1 to 3 μm is formed thereon. In addition, a buffer oxide film 24.10 with a thickness of 200 to 500 A is added.
Silicon nitride films (hereinafter referred to as nitride films) 25 having a thickness of 00 to 2000 Å are sequentially formed. Note that in order to facilitate the anodization treatment of the silicon substrate 21 in the subsequent process, N+
Before forming the type buried diffusion layer 22, a P+ type buried diffusion layer may be further formed on the entire surface as required (not shown in the figure).

In this case, the silicon substrate 21 is not limited to P type, but can also be N type.

Next, as shown in FIG. 1fB), an opening 26 with a width of 1 to 3 μm is formed in the nitride film 25 and the buffer oxide film 24 in the region to be the element isolation region by using the usual photolithography method. ,
Further, the opening 26 passes through the epitaxial layer 23 and the r-type buried diffusion layer 22 perpendicularly to the silicon substrate surface to a depth of 4 to 4000 to reach the p-type silicon substrate 21.
A groove 27 of 6 μm is formed.

Subsequently, as shown in FIG. 1C, a mP type polycrystalline silicon layer 28 is deposited thickly (2 to 4 μm) by adding boron, which is a P type impurity, to the entire surface as an embedding material. fill in. Thereafter, as shown in FIG. 1D, the polycrystalline silicon layer 28 is etched and packed using a known method, leaving the polycrystalline silicon layer 28 only inside the groove 27. At this time, the depth of the etch notches is set to an appropriate depth so that the element forming region and the element isolation region become flat in the final step. Note that the method of adding boron into the polycrystalline silicon layer is not limited to the method of adding boron during the vapor phase chemical growth of the polycrystalline silicon layer. After forming the polycrystalline silicon layer remaining only inside the groove 27 by etching, the boron is selectively diffused into the polycrystalline silicon layer by taking advantage of the high diffusion rate of boron in the polycrystalline silicon layer. All boron diffusion may be performed.

Subsequently, by performing anodization treatment in a hydrofluoric acid aqueous solution, P inside the groove 27 is removed, as shown in FIG.
N+ type polycrystalline silicon layer 28 and an element formation region
The P-type silicon substrate 21 under the bottom surface of the ya buried diffusion layer 22 is converted into a porous silicon layer 29. At this time, the anodization reaction proceeds selectively in the P-type silicon region and does not proceed to the N23 silicon region, which is eventually surrounded by the porous silicon layer 29! Mold embedded diffusion layer 22
An N-type element formation region 31 consisting of the N-type epitaxial layer 23 and N-type epitaxial layer 23 is formed in an island shape.

Next, thermal oxidation treatment is performed using the nitride film 25 as a mask to convert the porous silicon layer 29 into a porous silicon oxide film 30 as shown in FIG. 1(F).

Finally, as shown in FIG. 1(G), the nitride film 25 and the buffer oxide layer 24 are removed. An N-type element formation region 31 made of the N-type epitaxial layer 23 is obtained.

Note that in the above embodiment, ! P directly under the mold-embedded diffusion layer 22
Although only the P-type silicon substrate portion is made into a porous silicon layer 29 and further converted into a porous silicon oxide film 30, it is also possible to make the entire area of the P-type silicon substrate 21 into a porous silicon layer and further convert it into a porous silicon oxide film. good.

(Effect of the invention) As explained in detail above, according to the method of this invention,
Forming a trench in a selected region of a P-type semiconductor layer having an N-type semiconductor layer on the surface thereof, penetrating the N-type semiconductor layer and reaching the P-type semiconductor layer, and filling the trench with a P-type semiconductor; Since the anodic chemical reaction is allowed to proceed, the lateral inward expansion of P+ diffusion, which was a problem in the conventional method, can be prevented from expanding the chemical reaction region due to 9, and the chemical reaction region and, by extension, the element isolation region. is now accurately determined by the groove width, and as a result, it is possible to obtain a complete isolation structure having a fine isolation region width with almost no difference in nomiturn conversion.

However, according to this method, unnecessary parts are removed by the formation, so N is applied to the entire surface of the P-type semiconductor layer.
A buried diffusion layer can be formed as a part of the semiconductor layer, and as a result, a mask for buried diffusion is not required, so the process can be significantly shortened. Since there is no need to consider the margin, it is possible to further reduce the width of the isolation region. Furthermore, according to the method of the present invention, the surface can be made flat as in the conventional method.

As described above, according to the manufacturing method of the present invention, an ideal complete isolation structure with a flat surface and a fine isolation region width with almost no difference in pattern dimension conversion can be obtained, and as a result,
For example, if applied to a bipolar semiconductor integrated circuit device,
Not only can the parasitic capacitance and stray capacitance between the collector substrates be significantly reduced, but also the degree of integration can be improved by reducing the isolation area, and wiring delays can be reduced (by shortening the wiring length), so high-speed, high-speed It becomes possible to realize integrated non-polar devices.

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view showing an embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention, FIG. 2 is a process cross-sectional view showing an example of the prior art, and FIG. 3 is a wiring diagram of the anodizing process. be. 21...P-type silicon substrate, 22...! Type buried diffusion layer, 23... Y type epitaxial layer, 27... Groove,
28... P-type polycrystalline silicon layer, 29... Porous silicon layer, 30... Porous silicon oxide film. Patent applicant: Oki Electric Industry Co., Ltd. - 1. 37 3027' Figure 1

Claims (1)

[Scope of Claims] (a) A step of forming a groove in a selected region of a P-type semiconductor layer having an N-type semiconductor layer on the surface thereof, penetrating the N-type semiconductor layer and reaching the P-type semiconductor layer; , (b) filling the trench with a P-type semiconductor, and (c) performing an anodization treatment on the P-type semiconductor and the P-type semiconductor layer, so that the entire region of the P-type semiconductor and directly under the N-type semiconductor layer is (d) oxidizing the porous semiconductor layer to convert it into an oxide film; and (d) oxidizing the porous semiconductor layer to convert it into an oxide film. A method for manufacturing a semiconductor integrated circuit device.