JPH05152427A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH05152427A
JPH05152427A JP29679091A JP29679091A JPH05152427A JP H05152427 A JPH05152427 A JP H05152427A JP 29679091 A JP29679091 A JP 29679091A JP 29679091 A JP29679091 A JP 29679091A JP H05152427 A JPH05152427 A JP H05152427A
Authority
JP
Japan
Prior art keywords
silicon
silicon substrate
substrate
silicon oxide
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP29679091A
Other languages
Japanese (ja)
Inventor
Itaru Namura
至 名村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP29679091A priority Critical patent/JPH05152427A/en
Publication of JPH05152427A publication Critical patent/JPH05152427A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To form a dielectric isolation structure without causing a crystal defect regarding the manufacturing method of a semiconductor device which is provided with the dielectric isolation structure using an SOI substrate. CONSTITUTION:An SOI substrate is provided with a structure where a silicon substrate 1 for support use, a silicon oxide film 2, a silicon nitride film 3 and a silicon substrate 4 for element formation use have been laminated in this order. By using the SOI substrate, a silicon nitride mask 5 is formed in a region, where an element is to be formed, on the silicon substrate 4 for element formation use; parts other than the region, where the element is to be formed, on the silicon substrate 4 for element formation are oxidized completely by a selective oxidation method; they are changed into a silicon oxide layer 6. Thereby, an element isolation layer is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、SOI基板を用いた誘
電体分離構造をもつ半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a dielectric isolation structure using an SOI substrate.

【0002】[0002]

【従来の技術】素子の底面と周囲側面を完全に絶縁膜で
分離する誘電体分離構造は、半導体装置、特に、半導体
集積回路装置の耐圧を向上し、寄生容量を低減する点で
大きな利点を有する。
2. Description of the Related Art A dielectric isolation structure in which a bottom surface and a peripheral side surface of an element are completely separated by an insulating film has a great advantage in improving a withstand voltage and reducing a parasitic capacitance of a semiconductor device, particularly a semiconductor integrated circuit device. Have.

【0003】図3は、従来の半導体装置の製造方法の工
程説明図である。この図において、21は支持用シリコ
ン基板、22は酸化シリコン膜、23は素子形成用シリ
コン基板、24は窒化シリコンマスク、25は酸化シリ
コン層である。
FIG. 3 is a process explanatory view of a conventional semiconductor device manufacturing method. In this figure, 21 is a supporting silicon substrate, 22 is a silicon oxide film, 23 is an element forming silicon substrate, 24 is a silicon nitride mask, and 25 is a silicon oxide layer.

【0004】この工程図によって従来の製造工程を説明
する。 第1工程(図3(A)参照) 支持用シリコン基板21の上に酸化シリコン膜22を介
して素子形成用シリコン基板23を貼り合わせたSOI
基板を形成する。
The conventional manufacturing process will be described with reference to this process chart. First step (see FIG. 3A) SOI in which an element forming silicon substrate 23 is bonded onto a supporting silicon substrate 21 with a silicon oxide film 22 interposed therebetween.
Form a substrate.

【0005】第2工程(図3(B)参照) 素子形成用シリコン基板23の上の素子形成予定領域に
窒化シリコンマスク24を形成する。
Second Step (See FIG. 3B) A silicon nitride mask 24 is formed on a device formation planned region on a device formation silicon substrate 23.

【0006】第3工程(図3(C)参照) 前工程で形成した窒化シリコンマスク24を耐酸化マス
クにして素子形成用シリコン基板23が完全に酸化シリ
コンになるまで熱酸化処理を加えて酸化シリコン層25
を形成する。その結果、窒化シリコンマスク24の下に
酸化シリコン層25によって囲まれた素子形成予定領域
23が残り、誘電体分離構造が完成する。
Third step (see FIG. 3C) The silicon nitride mask 24 formed in the previous step is used as an oxidation-resistant mask to perform thermal oxidation treatment until the silicon substrate 23 for element formation becomes completely silicon oxide. Silicon layer 25
To form. As a result, the element formation planned region 23 surrounded by the silicon oxide layer 25 remains under the silicon nitride mask 24, and the dielectric isolation structure is completed.

【0007】[0007]

【発明が解決しようとする課題】しかし、前記従来の製
造方法によって誘電体分離構造を形成しようとすると素
子形成用シリコン基板に結晶欠陥が発生しやすいという
問題があった。結晶欠陥が発生する原因を図3(C)に
よって説明する。
However, when the dielectric isolation structure is formed by the conventional manufacturing method, there is a problem that crystal defects are likely to occur in the element forming silicon substrate. The cause of the occurrence of crystal defects will be described with reference to FIG.

【0008】図3(C)に示すように、従来法で第3工
程の素子形成用シリコン基板23の酸化時に、素子形成
用シリコン基板23だけでなく、酸化シリコン膜22を
通して支持用シリコン基板21の表面のBの部分をも酸
化してしまう。シリコンが酸化されると、体積がおよそ
2倍に膨張するため、素子を形成する単結晶シリコンの
領域Aの周辺Cを上方に持ち上げるような力が働く。
As shown in FIG. 3C, when the element forming silicon substrate 23 is oxidized in the third step by the conventional method, not only the element forming silicon substrate 23 but also the supporting silicon substrate 21 through the silicon oxide film 22. The portion B on the surface of the will also be oxidized. When silicon is oxidized, its volume expands to about twice, so that a force acts to lift up the periphery C of the single crystal silicon region A forming the element.

【0009】その結果として単結晶シリコンの領域Aの
周辺Cの部分が湾曲し、素子を形成する単結晶シリコン
中に大きな応力が発生して結晶欠陥が発生する。そのた
め、上記従来の技術には実用化する上で困難が伴ってい
た。本発明は、結晶欠陥を発生することなく誘電体分離
構造を形成することができる半導体装置の製造方法を提
供することを目的とする。
As a result, a portion of the periphery C of the single crystal silicon region A is curved, and a large stress is generated in the single crystal silicon forming the element to cause a crystal defect. Therefore, the above-mentioned conventional technique has difficulties in practical use. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a dielectric isolation structure without generating crystal defects.

【0010】[0010]

【課題を解決するための手段】本発明にかかる半導体装
置の製造方法においては、支持用シリコン基板と、酸化
シリコン膜2、窒化シリコン膜と、素子形成用シリコン
基板をこの順序で積層した構造を有するSOI基板を用
い、該素子形成用シリコン板の素子形成予定領域以外を
選択酸化法によって酸化シリコン層に変換して素子分離
層を形成する工程を採用した。
In the method of manufacturing a semiconductor device according to the present invention, a structure in which a supporting silicon substrate, a silicon oxide film 2, a silicon nitride film, and an element forming silicon substrate are laminated in this order is adopted. A step of forming an element isolation layer by using the SOI substrate having the element and converting the silicon plate for element formation other than the element formation planned region into a silicon oxide layer by a selective oxidation method was adopted.

【0011】[0011]

【作用】図1は、本発明の半導体装置の製造方法の原理
説明図である。この図においては、1は支持用シリコン
基板、2は酸化シリコン膜、3は窒化シリコン膜、4は
素子形成用シリコン基板、5は窒化シリコンマスク、6
は酸化シリコン層である。
1 is an explanatory view of the principle of the method of manufacturing a semiconductor device according to the present invention. In this figure, 1 is a supporting silicon substrate, 2 is a silicon oxide film, 3 is a silicon nitride film, 4 is an element forming silicon substrate, 5 is a silicon nitride mask, and 6
Is a silicon oxide layer.

【0012】まず、支持用シリコン基板1と酸化シリコ
ン膜2と窒化シリコン膜3と素子形成用シリコン基板4
を積層したSOI基板を調製し、その表面の全面に窒化
シリコン膜をCVDによって形成し、フォトグラフィー
技術によって素子形成予定領域以外の部分を除去し、窒
化シリコンマスク5を残す(図1(A)参照)。
First, a supporting silicon substrate 1, a silicon oxide film 2, a silicon nitride film 3 and a device forming silicon substrate 4 are formed.
Is prepared, a silicon nitride film is formed on the entire surface of the SOI substrate by CVD, and the portion other than the element formation planned region is removed by the photolithography technique, leaving the silicon nitride mask 5 (FIG. 1A). reference).

【0013】つぎに、酸化性雰囲気中で高温に保つこと
によって酸化処理を加える。この酸化処理によって窒化
シリコンマスク5の外側に露出している素子形成用シリ
コン基板4は酸化されて厚さが2倍程度に膨張した酸化
シリコン層6が形成されるが、酸化シリコン膜2の上に
窒化シリコン膜3が形成されているため、酸化シリコン
膜2を通して支持用シリコン基板1の表面が酸化される
ことはなく、素子形成用シリコン基板4を持ち上げる力
が働かないから、窒化シリコンマスク5の下の素子形成
予定領域に残った素子形成用シリコン基板4に結晶欠陥
が生じない(図1(B)参照)。その後の素子形成工程
は従来技術と同じである。
Next, an oxidation treatment is added by keeping the temperature at a high temperature in an oxidizing atmosphere. By this oxidation treatment, the element forming silicon substrate 4 exposed on the outside of the silicon nitride mask 5 is oxidized to form a silicon oxide layer 6 having a thickness doubled. Since the silicon nitride film 3 is formed on the silicon nitride film 3, the surface of the supporting silicon substrate 1 is not oxidized through the silicon oxide film 2, and the force for lifting the element forming silicon substrate 4 does not work. Crystal defects do not occur in the element formation silicon substrate 4 remaining in the element formation planned region below (see FIG. 1B). The subsequent element forming process is the same as that of the conventional technique.

【0014】[0014]

【実施例】図2は、実施例の半導体装置の製造方法の製
造工程説明図である。この図において、11は支持用シ
リコン基板、12は酸化シリコン膜、13は素子形成用
シリコン基板、14は窒化シリコン膜、15は酸化シリ
コン膜、16は窒化シリコンマスク、17は酸化シリコ
ン層である。
FIG. 2 is an explanatory view of manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment. In this figure, 11 is a supporting silicon substrate, 12 is a silicon oxide film, 13 is an element forming silicon substrate, 14 is a silicon nitride film, 15 is a silicon oxide film, 16 is a silicon nitride mask, and 17 is a silicon oxide layer. ..

【0015】この製造工程説明図によってこの実施例の
製造方法を説明する。 第1工程(図2(A)参照) 表面上に酸化シリコン膜12を堆積した支持用シリコン
基板11と、表面に窒化シリコン膜14と酸化シリコン
膜15を堆積した素子形成用シリコン基板13を、周知
のウェハ貼りつけ技術によって接着する。
The manufacturing method of this embodiment will be described with reference to the manufacturing process explanatory drawings. First step (see FIG. 2 (A)) A supporting silicon substrate 11 having a silicon oxide film 12 deposited on its surface, and an element forming silicon substrate 13 having a silicon nitride film 14 and a silicon oxide film 15 deposited on its surface, Bonding is performed by a well-known wafer bonding technique.

【0016】第2工程(図2(B)参照) つぎに、研磨(ポリッシュ)または化学エッチングによ
って、素子形成用シリコン基板13を例えば0.5μm
に薄膜化する。そして、その表面に窒化シリコン膜を形
成した後、パターニングして、素子形成予定領域に窒化
シリコンマスク16を形成する。
Second Step (See FIG. 2B) Next, the silicon substrate 13 for element formation is, for example, 0.5 μm by polishing (polishing) or chemical etching.
Thin. Then, after forming a silicon nitride film on the surface, patterning is performed to form a silicon nitride mask 16 in the element formation planned region.

【0017】第3工程(図2(C)参照) 窒化シリコンマスク16をマスクにして露出している素
子形成用シリコン基板13を完全に酸化して厚さ約1μ
mの酸化シリコン層17を形成し、素子形成予定領域を
酸化シリコン層17によって周囲を完全に包囲する誘電
体分離構造が完成する。それ以降は通常の集積回路製造
工程によって素子形成用シリコン基板13中に適宜素子
を形成する。
Third step (see FIG. 2 (C)) The exposed silicon substrate 13 for element formation is completely oxidized by using the silicon nitride mask 16 as a mask to have a thickness of about 1 μm.
A silicon oxide layer 17 having a thickness of m is formed, and a dielectric isolation structure in which the device formation planned region is completely surrounded by the silicon oxide layer 17 is completed. After that, appropriate elements are formed in the element forming silicon substrate 13 by a normal integrated circuit manufacturing process.

【0018】[0018]

【発明の効果】以上説明したように、本発明によれば素
子形成予定領域に結晶欠陥を含まない誘電体分離構造の
形成が可能であり、半導体集積回路装置の性能向上に寄
与するところが大きい。
As described above, according to the present invention, it is possible to form a dielectric isolation structure that does not include crystal defects in the element formation planned region, which greatly contributes to the performance improvement of the semiconductor integrated circuit device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製造方法の原理説明図で
ある。
FIG. 1 is a diagram illustrating the principle of a method for manufacturing a semiconductor device according to the present invention.

【図2】実施例の半導体装置の製造方法の製造工程説明
図である。
FIG. 2 is a manufacturing process explanatory diagram of the semiconductor device manufacturing method according to the embodiment.

【図3】従来の半導体装置の製造方法の工程説明図であ
る。
FIG. 3 is a process explanatory view of a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 支持用シリコン基板 2 酸化シリコン膜 3 窒化シリコン膜 4 素子形成用シリコン基板 5 窒化シリコンマスク 6 酸化シリコン層 1 silicon substrate for support 2 silicon oxide film 3 silicon nitride film 4 silicon substrate for element formation 5 silicon nitride mask 6 silicon oxide layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 支持用シリコン基板(1)と、酸化シリ
コン膜(2)と、窒化シリコン膜(3)と、素子形成用
シリコン基板(4)をこの順序で積層した構造を有する
SOI基板を用い、該素子形成用シリコン板(4)の素
子形成予定領域以外を選択酸化法によって酸化シリコン
層(6)に変換して素子分離層を形成する工程を含むこ
とを特徴とする半導体装置の製造方法。
1. An SOI substrate having a structure in which a supporting silicon substrate (1), a silicon oxide film (2), a silicon nitride film (3) and a device forming silicon substrate (4) are laminated in this order. And a step of forming a device isolation layer by converting a region other than a device formation planned region of the device forming silicon plate (4) into a silicon oxide layer (6) by a selective oxidation method. Method.
JP29679091A 1991-11-13 1991-11-13 Manufacture of semiconductor device Withdrawn JPH05152427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29679091A JPH05152427A (en) 1991-11-13 1991-11-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29679091A JPH05152427A (en) 1991-11-13 1991-11-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05152427A true JPH05152427A (en) 1993-06-18

Family

ID=17838168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29679091A Withdrawn JPH05152427A (en) 1991-11-13 1991-11-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05152427A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5427971A (en) * 1994-02-01 1995-06-27 Goldstar Electron Co., Ltd. Method for fabrication of semiconductor elements
US5780352A (en) * 1995-10-23 1998-07-14 Motorola, Inc. Method of forming an isolation oxide for silicon-on-insulator technology
US6566712B2 (en) * 1999-04-26 2003-05-20 Oki Electric Industry Co., Ltd. SOI structure semiconductor device and a fabrication method thereof
US6627511B1 (en) * 1995-07-28 2003-09-30 Motorola, Inc. Reduced stress isolation for SOI devices and a method for fabricating

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5427971A (en) * 1994-02-01 1995-06-27 Goldstar Electron Co., Ltd. Method for fabrication of semiconductor elements
US6627511B1 (en) * 1995-07-28 2003-09-30 Motorola, Inc. Reduced stress isolation for SOI devices and a method for fabricating
US5780352A (en) * 1995-10-23 1998-07-14 Motorola, Inc. Method of forming an isolation oxide for silicon-on-insulator technology
US6566712B2 (en) * 1999-04-26 2003-05-20 Oki Electric Industry Co., Ltd. SOI structure semiconductor device and a fabrication method thereof

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