JPS5875845A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5875845A
JPS5875845A JP17395681A JP17395681A JPS5875845A JP S5875845 A JPS5875845 A JP S5875845A JP 17395681 A JP17395681 A JP 17395681A JP 17395681 A JP17395681 A JP 17395681A JP S5875845 A JPS5875845 A JP S5875845A
Authority
JP
Japan
Prior art keywords
film
thin film
silicon
bird
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17395681A
Other languages
Japanese (ja)
Inventor
Hidetoshi Ishiwari
石割 秀敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17395681A priority Critical patent/JPS5875845A/en
Publication of JPS5875845A publication Critical patent/JPS5875845A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To suppress the production of a bird beak by surrounding the side of a mask layer with an Si3N4 film and then selectively oxidizing it. CONSTITUTION:A thin SiO2 film 2 and a thin silicon oxynitride (SixNyOz) film 3 are sequentially formed on a silicon substrate 1, are photolithographically patterned, thereby removing the SiO2 film and the SixNyOz film except on an element forming region 5. Then, an Si3N4 film 4 is formed by a CVD method on the overall surface. Then, the region 5 is removed, the film 4 is removed, and the film is allowed to remain only at the periphery of a laminated mask. Thereafter, a selective oxidation is performed, thereby forming an isolating oxidized film 6. In this manner, lateral oxidation is suppressed, thereby preventing the productin of a bird beak.

Description

【発明の詳細な説明】 本発明はバードビークの発生を抑制した半導体装置の製
造方法に関する◎ MOS・ICなどの半導体装置において各半導体素子は
シリコン基板上に同一工程により多数同時に製造される
が、この際6半導体素子は1〜2声溝の厚い酸化皮膜層
によシ分離されている〇こ\でこの酸化膜は分離用酸化
膜或はフィールド酸化膜と呼ばれ、酸化雰囲気中にて形
成されている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device that suppresses the occurrence of bird's beak. In semiconductor devices such as MOS and IC, a large number of semiconductor elements are simultaneously manufactured on a silicon substrate by the same process. 6 Semiconductor elements are separated by a thick oxide film layer with 1-2 grooves.This oxide film is called an isolation oxide film or field oxide film, and is formed in an oxidizing atmosphere. ing.

さて半導体素子例えばMOS)ランジスタの場合、この
素子形成領域には結晶欠陥を防止する目的などのため厚
さ約5oolの酸化皮膜が予め形成されているが、分離
用酸化膜の形成に際して素子形成領域端の酸化皮膜も同
時に成長し、これはその領域にソース、ドレインおよび
ゲートを形成する際の障害となる。
Now, in the case of a semiconductor element (for example, a MOS transistor), an oxide film with a thickness of approximately 5 oool is formed in advance in the element formation region for the purpose of preventing crystal defects. An oxide film at the edges also grows at the same time, which becomes an obstacle when forming sources, drains, and gates in those regions.

この分離用酸化膜形成の際、素子形成領域に横方向酸化
によって生ずる酸化物層はバードビーク(鳥の嘴)と言
われ半導体装置製造の妨げとなっている。
During the formation of this isolation oxide film, the oxide layer produced in the element formation region by lateral oxidation is called a bird's beak and is an hindrance to the manufacture of semiconductor devices.

本発明の目的は半導体装置の製造に際してバードビーク
の発生を抑制するに17、その方法として酸化シリコン
/シリコンオキシナイトライドの積層パターンよシなる
半導体素子形成領域を窒化シリコンで被覆したる後分離
用酸化膜を形成することによシ横方向酸化を抑制するも
のである。
An object of the present invention is to suppress the occurrence of bird's beaks during the manufacture of semiconductor devices17, and as a method for this purpose, a semiconductor element forming area having a laminated pattern of silicon oxide/silicon oxynitride is coated with silicon nitride, and then oxidation for isolation is performed. By forming a film, lateral oxidation is suppressed.

発明者は特願昭55−138316(昭55.10.3
出願)にてシリコン基板の上に形成された酸化シリコン
/シリコンオキシナイトライド/窒化シリコンの3層よ
りなるパターンを半導体素子形成領域上に形成し、これ
を加湿し九酸素雰囲気中で熱酸化することによ〕、分離
用酸化膜を形成する方法を出願中であるが本発明はこれ
を更に進展させたものである。
The inventor filed a patent application No. 55-138316 (October 3, 1982).
A pattern consisting of three layers of silicon oxide/silicon oxynitride/silicon nitride formed on a silicon substrate is formed on a semiconductor element formation area, and this is humidified and thermally oxidized in an oxygen atmosphere. In particular, a method for forming an isolation oxide film is currently pending, and the present invention is a further development of this method.

以下本発明を図面によ〉前出願と比較して説明する。第
1図は前出願に係る工程図、第2図はこの際発生するバ
ードビークの説明図、第3図は本発明にか\る工程図で
ある。
The present invention will be explained below with reference to the drawings in comparison with the previous application. FIG. 1 is a process diagram according to the previous application, FIG. 2 is an explanatory diagram of the bird's beak that occurs at this time, and FIG. 3 is a process diagram according to the present invention.

第1図はシリコン基板の上に半導体素子を一形成する工
程図でありてシリコン基板1を1000℃の乾燥酸素雰
囲気中で熱処理して約500xの酸化シリコン(以下S
low)薄膜2を形成する(A図)。
FIG. 1 is a process diagram for forming a semiconductor element on a silicon substrate, in which the silicon substrate 1 is heat-treated in a dry oxygen atmosphere at 1000°C to form a silicon oxide (hereinafter referred to as S) of approximately 500×.
low) Form a thin film 2 (Figure A).

次に化学気相成長法(以下CVD法)によシこの上に厚
さ0.2層諷以上のシリコンオΦシナイトライド(以下
81 x Ny Oz )薄膜3を形成する(B図)。
Next, a thin film 3 of silicon oxide nitride (hereinafter referred to as 81 x Ny Oz) having a thickness of 0.2 or more layers is formed on this film by chemical vapor deposition (hereinafter referred to as CVD method) (Figure B).

このS i x Ny Oz 463の形成が前出願の
特徴であって従来の工程ではか\る薄膜は設けられてい
ない。
This formation of S i x Ny Oz 463 is a feature of the previous application, and no thin film is provided in the conventional process.

との8 i x Ny Os薄膜3は次に行われる窒化
シリコン(以下811N4)の薄膜形成と同一の装置を
用い類似のガス組成で行われるものであって、モノシラ
ン(giH番)、アンモニア(NHs ) s酸素(0
1)。
The 8 i x Ny Os thin film 3 is formed using the same equipment and similar gas composition to the next thin film formation of silicon nitride (hereinafter referred to as 811N4). ) s oxygen (0
1).

窒素(N鵞)の混合ガス但し、酸素とモノシランの流量
比がO,S以上(0,: 81H,≧0.3)としたも
のを約800℃に加熱した装置内に導くことによりシリ
コン基板1上に成長させ丸亀のである。
By introducing a mixed gas of nitrogen (N) in which the flow rate ratio of oxygen and monosilane is O, S or higher (0,: 81H, ≧0.3) into a device heated to approximately 800°C, silicon substrates can be melted. The one in Marugame is made to grow to the top.

こ−で滲さ0.2s@以上と言う制限はMOB):It
ンジスタを製造する際のゲートS iO雪膜の耐圧向上
と関係があ〕、従来のMOS)?ンジスタのゲート耐圧
不良が分離用酸化膜形成工程中に7jC&5isN+薄
膜とが反応して生じ九NHs s NOxなどの窒素化
合物が81jN番薄膜および5ins薄膜中をシリコン
基板にまで拡散してこれと反応し、シリコン窒化物を生
成すること\関係があることから5ilN4薄膜と5l
ot薄膜との間に0.2層謬以上の厚さをもつS 1 
x NyOz薄膜をバッフ1として設けたものである。
There is a limit of 0.2 seconds or more of blurring (MOB): It
Is this related to the improvement in voltage resistance of the gate SiO snow film when manufacturing transistors (conventional MOS)? The defective gate breakdown voltage of the transistor is caused by the reaction between the 7jC and 5isN+ thin films during the process of forming the isolation oxide film.Nitrogen compounds such as 9NHs NOx diffuse into the 81jN thin film and the 5ins thin film and react with them. , 5ilN4 thin film and 5l because of the relationship between producing silicon nitride.
S1 with a thickness of 0.2 layers or more between the ot thin film
x NyOz thin film was provided as the buffer 1.

次にCVD法によシ従来の方法でS 1 s N4薄膜
4を形成しく0図)、次に半導体素子形成領域5上の5
isNa4膜4をホトレジストで被覆後フレオンガス(
CF4)などの反応性ガスを用いるドライエツチング法
によりパターンユングを行う(D図)0次に加湿しfc
酸素雰凹気中で900〜1100℃の温度中で加熱する
ことによシ半導体素子形成領域5を除いて選択酸化が行
われて厚さ0.8〜2声賜のstowからなる分離用酸
化膜6が形成される(E図)。
Next, a S 1 s N4 thin film 4 is formed using a conventional CVD method (Fig.
After coating the isNa4 film 4 with photoresist, freon gas (
Pattern etching is performed by dry etching using a reactive gas such as CF4) (Figure D).
By heating at a temperature of 900 to 1100° C. in an oxygen atmosphere, selective oxidation is performed except for the semiconductor element forming region 5, resulting in an isolating oxidation layer consisting of a stow with a thickness of 0.8 to 2 mm. A film 6 is formed (Figure E).

第2図は第1図(E図)において、パターンユングのマ
スクとして働いた8 i x N y Oz薄膜3と8
11Nm薄膜4からなる積層膜を除いたもの一部分断面
拡大図であって、半導体素子形成領域5のシリコン基板
1上には厚さ約50OAの5i(h薄膜2があシ、その
周囲は厚い分離用酸化膜6によシ分離されているが、こ
の境界部のSiO雪薄膜2は選択酸化の際にこの影響を
受は鳥の嘴状に幅Xの酸化膜が周辺部で成長するバード
ビークの現象が見られる。
Figure 2 shows the 8 i x N y Oz thin films 3 and 8 that served as pattern Jung masks in Figure 1 (Figure E).
This is an enlarged partial cross-sectional view of a laminated film consisting of a 11 Nm thin film 4, with a 5i (h thin film 2) having a thickness of about 50 OA on the silicon substrate 1 in the semiconductor element formation region 5, and a thick isolation layer around it. However, the SiO snow thin film 2 at this boundary is affected by this during selective oxidation, resulting in a bird's beak shape in which an oxide film with a width of X grows around the periphery. A phenomenon can be seen.

この現象は従来の半導体装置の製造に際して必ず生じて
いるもので、発明者の先の出願においては半導体素子の
ゲート耐圧は向上したがこのバードビークの現象につい
ては従来法と比較し九場合、大幅に低減されてはいるが
取シ除くことはできなかった。
This phenomenon always occurs during the manufacturing of conventional semiconductor devices, and although the gate breakdown voltage of semiconductor devices has improved in the inventor's previous application, this bird's beak phenomenon has significantly improved in nine cases compared to the conventional method. Although it has been reduced, it has not been possible to eliminate it.

然し、このバードビークが存在すると半導体素子形成領
域5にソース、ドレインなどを形成する際その実効面積
が設計面積と異なシ、従って集積回路の微細化を困11
Kしていた。
However, if this bird's beak exists, the effective area will be different from the design area when forming sources, drains, etc. in the semiconductor element forming region 5, which will make it difficult to miniaturize the integrated circuit.
I was playing K.

本発明は先に出願し九8 i x Ny Oz薄膜を中
間層として用いる半導体装置の製造方法に関連し、バー
ドビークを抑制する製造方法に係るものである。
The present invention relates to a previously filed method for manufacturing a semiconductor device using a 98xNyOz thin film as an intermediate layer, and relates to a manufacturing method for suppressing bird's beak.

第3図は本発明に係る工程であってシリコン基板1への
810重薄膜2の形成(A図)および、この上への81
1N、OS薄膜3の形成(B図)は先の工程と変らない
FIG. 3 shows the process according to the present invention, including the formation of an 810-thick thin film 2 on a silicon substrate 1 (Figure A), and the formation of an 810-thick film 2 on the silicon substrate 1 (Figure A).
The formation of the 1N, OS thin film 3 (Figure B) is the same as the previous step.

次に全面にホトレジストを塗布後写真蝕刻技術(ホトリ
ソグラフィ)によシ半導体素子形成領域5を除いてBl
otおよび81 xNyOz g gを除去しく0図)
、次にCVD法によシ全面にSlsNm薄膜4を形成し
くD図)、次に写真蝕刻技術により半纏・体素予形成領
域5を除いて811N4薄膜4を除去する(E図)0こ
の場合は5ins薄膜2の上に5iXNyO2薄膜3が
積層したパターンがあシ、これがBig!’ta薄膜4
により覆われておシ、そのためS10!薄膜2は大気と
は遮断されている。
Next, after coating the entire surface with photoresist, photolithography is applied to remove the semiconductor element forming area 5 and remove the Bl.
ot and 81 x NyOz g (Fig. 0)
Next, a SlsNm thin film 4 is formed on the entire surface by the CVD method (Fig. D), and then the 811N4 thin film 4 is removed except for the half-bond/body element preformation region 5 by photolithography (Fig. E). There is a pattern in which 5iXNyO2 thin film 3 is laminated on top of 5ins thin film 2. This is Big! 'ta thin film 4
It is covered by S10! The thin film 2 is isolated from the atmosphere.

次にこの状態で選択酸化を行うと分離用酸化膜6が基板
1上に成長するが半導体素子形成領域5は511N4薄
[4で覆われているために横方向酸化は抑制され、従っ
てバードビークは発生しない。
Next, when selective oxidation is performed in this state, an isolation oxide film 6 is grown on the substrate 1, but since the semiconductor element forming region 5 is covered with 511N4 thin [4], lateral oxidation is suppressed, and therefore bird's beak is prevented. Does not occur.

本発明はバードビークを抑制した半導体装置の製造方法
に関するもので、MO8φICなどの半導体素子のゲー
ト耐圧を数置した出願中の素子構造を用いて製造方法を
説明したが、これに限定されるものはない。
The present invention relates to a method for manufacturing a semiconductor device that suppresses bird's beak, and the manufacturing method has been explained using a pending device structure in which the gate breakdown voltage of a semiconductor device such as an MO8φ IC is set to several values, but the method is not limited to this. do not have.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(4)〜(ト)は前出願に係る半導体装置の製造
工恨説明図、第2図はバードビークの説明図、第3図囚
〜(ト)は本発明にか−る半導体装置の製造工程睨明図
である。 図において、1はシリコン基板、2はS i Oを薄脆
3は81xNyOx薄膜、4は5lsN+薄膜、5は半
導体素子形成領域、6は分離用酸化膜。 第2図
1(4) to (G) are explanatory diagrams of the manufacturing process of the semiconductor device according to the previous application, FIG. 2 is an explanatory diagram of a bird beak, and FIGS. It is a perspective view of the manufacturing process. In the figure, 1 is a silicon substrate, 2 is a thin brittle SiO film, 3 is an 81xNyOx thin film, 4 is a 5lsN+ thin film, 5 is a semiconductor element formation region, and 6 is an isolation oxide film. Figure 2

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上の半導体素子形成領域Kl*シリコンの
酸化膜とシリコンオキシナイトライド膜とを選択的に積
層してパターン形成したる後、鋏パメーン部を選択的に
窒化シリコン膜で被覆し、次に該窒化シリコン膜を!ス
フとしてシリコン基板を選択酸化して分離用酸化膜を形
成する仁とを特徴とする半導体装置の製造方法。
Semiconductor element formation area Kl on silicon substrate * After selectively laminating a silicon oxide film and a silicon oxynitride film to form a pattern, the scissors frame portion is selectively covered with a silicon nitride film, and then The silicon nitride film! 1. A method for manufacturing a semiconductor device, comprising: forming an isolation oxide film by selectively oxidizing a silicon substrate.
JP17395681A 1981-10-30 1981-10-30 Manufacture of semiconductor device Pending JPS5875845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17395681A JPS5875845A (en) 1981-10-30 1981-10-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17395681A JPS5875845A (en) 1981-10-30 1981-10-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5875845A true JPS5875845A (en) 1983-05-07

Family

ID=15970164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17395681A Pending JPS5875845A (en) 1981-10-30 1981-10-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5875845A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5154378A (en) * 1974-11-07 1976-05-13 Fujitsu Ltd Handotaisochino seizohoho
JPS55165637A (en) * 1979-06-11 1980-12-24 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5154378A (en) * 1974-11-07 1976-05-13 Fujitsu Ltd Handotaisochino seizohoho
JPS55165637A (en) * 1979-06-11 1980-12-24 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor integrated circuit

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