JPS6076138A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6076138A
JPS6076138A JP18529083A JP18529083A JPS6076138A JP S6076138 A JPS6076138 A JP S6076138A JP 18529083 A JP18529083 A JP 18529083A JP 18529083 A JP18529083 A JP 18529083A JP S6076138 A JPS6076138 A JP S6076138A
Authority
JP
Japan
Prior art keywords
film
insulating film
oxide film
forming
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18529083A
Other languages
Japanese (ja)
Inventor
Kunihiko Asahi
旭 国彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP18529083A priority Critical patent/JPS6076138A/en
Publication of JPS6076138A publication Critical patent/JPS6076138A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To suppress encroachment of a field region and to form a fine insulation isolating region by a method wherein a second insulating film is formed at overhang parts only on the peripheral edge parts of a first insulating film pattern formed on the surface of the semiconductor substrate. CONSTITUTION:An SiO2 film 2 is grown on an Si substrate 1, an Si3N4 film 3' is deposited and parts other than the programming parts for forming active regions are removed by performing an etching and channel stopper regions 15 are formed by ion-implanting boron. A thermal oxide film 16 is formed at the isolating region forming parts, the film 16 is removed by performing an etching and parts just below the peripheral edge parts of the Si3N4 film pattern 3' are respectively formed in an overhang state. A thermal oxide film 19 is formed at field forming regions 18, an Si3N4 film 20 is grown on the whole surface and a selective etching is performed, and an Si3N4 film 20' is left at the overhang lower parts only. A wet oxidation is performed and a thick field oxide film 21 is selectively grown. According to such a way, the lateral diffusion of an oxidizing agent, which is performed through the thermal oxide film 19, is suppressed, thereby enabling to lessen the bird's beak.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法に関し、詳しくは、I
C,LSI、VLSIfiどの半導体装置の製造工程に
おける素子間分離技術の改良に係る。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device.
This invention relates to improvements in isolation technology between elements in the manufacturing process of semiconductor devices such as C, LSI, and VLSI fi.

従来例の構成とその問題点 従来、半導体装置、特にMO8LSIの製造工程での素
子間分離方法としては選択酸化法と呼ばれる酸化膜分離
技術が一般的に用いられている。
Conventional Structures and Problems Conventionally, an oxide film isolation technique called selective oxidation has been generally used as a method for isolating elements in the manufacturing process of semiconductor devices, particularly MO8LSIs.

この方法t−n−チャンネルMO8LSIi例にして以
下工程順に説明する。
This method will be explained step by step using a tn-channel MO8LSI as an example.

まず、第1図(a)に示すように、(100)結晶面を
もつP型シリコン(Si)基板1上に二酸化シリコン(
5iOz )膜2を熱酸化により成長させ、更に、この
SiO2膜2上に窒化シリコン(Si3N4)膜3を堆
積する。つづいて同図(b)のように、写真蝕刻法によ
り活性領域形成部にフォトレジスト膜4を形成し、これ
をマスクとして活性領域形成部の5isNa膜3をエツ
チング除去し、このマスク4と同形パターンの5lsN
a膜3′ヲ形成し、その後、例えばボロンのイオン注入
を行なって、フィールド部にチャンネルストッパー領域
としてのP+領域6を形成する。次に、同図(0)のよ
うに、フォトレジスト膜4を除去後、513N4膜パタ
ーン3′をマスクとして周知の選択酸化法に したがっ
てウェット酸化全施し、選択的に厚いフィールド酸化膜
6金成長させる。これらの過程で形成されるP+領域6
およびフィールド酸化膜6が素子間分離領域となる。O
・きつづき、同図(d)のように、Si3N4膜パター
ン3′ および5102膜2をエツチング除去してフィ
ールド酸化膜6で分離されたSi基板1の表面、すなわ
ち活性領域7全形成する。次いで、第1図(e)に示す
ように、この活性領域7にゲート酸化膜8を介して多結
晶シリコンからなるゲート電極9を形成し、さらに、セ
ルファライン法によって、例えば、砒素を拡散して、ソ
ース、ドレインとしてのn+領域10.11f6:形成
する。最後に、同図(f)のように、層間絶縁膜として
のSiO2膜12全12とえばCvDにより堆積し、さ
らに、n+領域10,11、および、ゲート電極9土を
おおうSiO2膜12部分にコンタクトホール13を開
孔した後、A/配線16を形成してnチャンネルMO3
素子および分離領域を製造する。
First, as shown in FIG. 1(a), silicon dioxide (
5iOz) film 2 is grown by thermal oxidation, and then a silicon nitride (Si3N4) film 3 is deposited on this SiO2 film 2. Subsequently, as shown in FIG. 4B, a photoresist film 4 is formed in the active region forming part by photolithography, and using this as a mask, the 5isNa film 3 in the active region forming part is removed by etching, and the same shape as this mask 4 is formed. 5lsN of pattern
After forming the a film 3', ions of boron, for example, are implanted to form a P+ region 6 as a channel stopper region in the field portion. Next, as shown in the same figure (0), after removing the photoresist film 4, using the 513N4 film pattern 3' as a mask, wet oxidation is carried out according to the well-known selective oxidation method, and a thick field oxide film of 6 gold is selectively grown. let P+ region 6 formed through these processes
And field oxide film 6 becomes an element isolation region. O
・Continuing, as shown in FIG. 4(d), the Si3N4 film pattern 3' and the 5102 film 2 are removed by etching to form the entire surface of the Si substrate 1 separated by the field oxide film 6, that is, the active region 7. Next, as shown in FIG. 1(e), a gate electrode 9 made of polycrystalline silicon is formed on this active region 7 via a gate oxide film 8, and further, for example, arsenic is diffused by the self-line method. Then, n+ regions 10.11f6 as sources and drains are formed. Finally, as shown in FIG. 3(f), the entire SiO2 film 12 as an interlayer insulating film is deposited by, for example, CvD, and the SiO2 film 12 covering the n+ regions 10, 11 and the gate electrode 9 is further deposited. After opening the contact hole 13, the A/wiring 16 is formed and the n-channel MO3
Fabricate elements and isolation regions.

しかしながら、上述の従来方式では、次に示すような種
々の問題点があった。第2図は、前記第1図(C)に示
す活性領域形成用の5i5N4膜パターン3′ヲマスク
にして、フィールド酸化膜6全形成した時の隣接する2
つの活性領域との関係で詳しく描いたものである。一般
に選択酸化法ではフィールド酸化膜6がA、Fの分布領
域をもち、特にSi sN a膜パターン3′下の周縁
部に喰い込んで成長して、同図中のF領域全形成するこ
とが知られている。これは、フィールド酸化中に酸化剤
がSi3N4膜パターン3′下周縁部の薄い5i02膜
2全通して拡散していくために酸化膜が形成される部分
り、いわゆる、バーズビークと、フィールド酸化膜6の
厚い部分が横方向に、もぐり込んだ部分Eとから成る。
However, the conventional method described above has various problems as shown below. FIG. 2 shows the adjacent two when the entire field oxide film 6 is formed using the 5i5N4 film pattern 3' for forming the active region shown in FIG. 1(C) as a mask.
This is a detailed depiction of the relationship between the two active regions. In general, in the selective oxidation method, the field oxide film 6 has distribution regions A and F, and in particular grows into the peripheral portion under the Si sNa film pattern 3', forming the entire F region in the figure. Are known. This is because the oxidizing agent diffuses through the thin 5i02 film 2 at the lower peripheral edge of the Si3N4 film pattern 3' during field oxidation, so the oxide film is formed in the so-called bird's beak and the field oxide film 6. It consists of a thick part E and a hollow part E in the lateral direction.

前記F領域の長さは、たとえばSi 3N a膜パター
ン3′の厚さが1200人、その下のSiO2膜2が6
00人の条件で1μmの膜厚のフィールド酸化膜6を成
長させた場合、約1μmに達する。このためフィールド
領域の全幅距離CはSi sN a膜パターン3′間の
距離ムを2μmとすると、前記F領域が1μmであるか
ら4μm以下に小さくできずLSI素子の高集積化にと
って大きな妨げとなる。このようなことから最近、51
5Na膜パターン3′の膜厚を厚くシ、この下のSiO
2膜2’e薄<I、て、バーズビークを抑制する方法が
試みられている。これは、S i s II 4膜厚を
厚くすることによって5isN4膜端部が屈曲しKくく
なり、これによりバーズビークが小さくなるものである
。また、5i3Na膜下の5102膜厚を薄くすること
により5102膜断面積金小さくし酸化剤の横方向への
拡散を、おさえたものである。
The length of the F region is such that, for example, the thickness of the Si 3 Na film pattern 3' is 1200 mm, and the thickness of the SiO 2 film 2 below it is 6 mm.
When a field oxide film 6 with a thickness of 1 μm is grown under the conditions of 0.00 people, the thickness reaches approximately 1 μm. For this reason, if the distance C between the Si sNa film patterns 3' is 2 μm, the total width distance C of the field region cannot be reduced to 4 μm or less since the F region is 1 μm, which is a major hindrance to high integration of LSI devices. . Due to this, recently 51
The thickness of the 5Na film pattern 3' is made thicker, and the SiO layer underneath is made thicker.
A method of suppressing bird's beak has been attempted in which 2 films 2'e thin<I. This is because by increasing the thickness of the S i s II 4 film, the edges of the 5 is N 4 film are bent and K becomes difficult, thereby reducing the bird's beak. Furthermore, by reducing the thickness of the 5102 film below the 5i3Na film, the cross-sectional area of the 5102 film is reduced, thereby suppressing the lateral diffusion of the oxidizing agent.

しかし、曲名では、フィールド酸化膜の周縁部における
Si 3N a膜のクラックを生じ、後者では、活性領
域の周辺を中心に、シリコン表面に、ストレスが加わり
、転位の発生があるなどの問題があった。
However, in the title of the song, cracks occur in the Si 3N a film at the periphery of the field oxide film, and in the latter case, stress is applied to the silicon surface mainly around the active region, causing dislocations. Ta.

発明の目的 本発明は、上述の従来例にみられた問題点を解消するも
のであり、選択酸化法による、フィールド領域の喰い込
みを抑制することのできる半導体装置の製造方法を提供
するものである。
OBJECTS OF THE INVENTION The present invention solves the problems seen in the above-mentioned conventional examples, and provides a method for manufacturing a semiconductor device that can suppress the digging into the field region by selective oxidation. be.

発明の構成 本発明は、要約すると、半導体基板表面に酸化膜および
第1の絶縁膜全形成する工程、前記第1の絶縁膜および
前記酸化膜の所定領域に開口部を形成する工程、前記開
口部を通じて前記学導体基板を選択酸化して、バーズビ
ーク状の選択酸化膜を形成する工程、同選択酸化膜を前
記バーズビーク部に及んでエツチング除去して、前記第
1の絶縁膜開口部周縁部下にオーバーハング状開口を形
成する工程、前記開口に露出した半導体基板表面に薄い
酸化膜を形成する工程、全面をおおって、第2の絶縁膜
を形成する工程、前記第2の絶縁膜全異方性にエツチン
グして、前記第1の絶縁膜下周縁部の前記オーバーハン
グ状部分にのみ前記第2の絶縁膜金銭し、他部の前記第
2の絶縁膜を除去する工程、前記第1の絶縁膜開口部を
埋める選択的熱酸化工程をそなえた半導体装置の製造方
法であり、これにより、酸化剤の横方向拡散を抑制し、
バーズビークを小さくするものである。
Structure of the Invention To summarize, the present invention includes a step of completely forming an oxide film and a first insulating film on the surface of a semiconductor substrate, a step of forming an opening in a predetermined region of the first insulating film and the oxide film, and the opening. a step of selectively oxidizing the conductor substrate through the opening to form a bird's beak-shaped selective oxide film, and etching and removing the selective oxide film extending over the bird's beak to form a portion below the periphery of the first insulating film opening. a step of forming an overhang-shaped opening, a step of forming a thin oxide film on the surface of the semiconductor substrate exposed in the opening, a step of forming a second insulating film covering the entire surface, and a step of forming the second insulating film with full anisotropy. etching the second insulating film only on the overhang-like portion of the lower peripheral edge of the first insulating film and removing the second insulating film in other parts; This is a method for manufacturing a semiconductor device that includes a selective thermal oxidation process that fills insulating film openings, thereby suppressing lateral diffusion of the oxidizing agent,
It makes the bird's beak smaller.

実施例の説明 以下、nチャンネルMO8LSIの製造方法を例にあげ
て、本発明の詳細な説明する。
DESCRIPTION OF EMBODIMENTS The present invention will be described in detail below, taking a method of manufacturing an n-channel MO8LSI as an example.

まず第3図(2L)に示すように、(100)結晶面を
もつP型Si基板1上に5iOz膜2を熱酸化により成
長させる。次に、このSiO2i2上に5j−3ea膜
3を堆積する。つづいて第3図fb)のように、写真蝕
刻法により活性領域予定部に、レジスト膜4を形成し、
これをマスクとして活性領域予定部用外のSi3N4膜
3ff:エツチング除去する。その後ボロンのイオン注
入を全面に行なってフィールド部分にチャネルス)ツバ
領域16を形成する。次にレジスト膜4を除去後、5i
sNa膜・くターン3′全マスクとして、活性領域以外
のSi基板表面すの熱酸化膜16をエツチング除去する
。この時、熱酸化膜16は、バーズビーク17を形成し
ていたため、5i5N4膜パターン3′の周縁部直下は
、オーバーハング状になる。次にフィールド形成領域1
BのSi表表面熟熱酸化100人程度の薄い熱酸化膜1
9を形成し、つづいて、減圧cvn法によpsi3N4
膜20を全膜面0成長する(同図(d))。この5is
Na膜20の膜厚は厚すぎるとフィールド選択酸化のと
きSi3N4膜20とSi 基板1との熱膨張率の差に
より発生する応力のためSi基板1に欠陥を発生させる
。このことから5i5N4膜20の膜厚としては100
0Å以下が望ましい。
First, as shown in FIG. 3 (2L), a 5iOz film 2 is grown by thermal oxidation on a P-type Si substrate 1 having a (100) crystal plane. Next, a 5j-3ea film 3 is deposited on this SiO2i2. Subsequently, as shown in FIG. 3 fb), a resist film 4 is formed in the intended active region by photolithography,
Using this as a mask, the Si3N4 film 3ff outside the intended active region is removed by etching. Thereafter, boron ions are implanted over the entire surface to form a channel brim region 16 in the field portion. Next, after removing the resist film 4, 5i
The thermal oxide film 16 on the surface of the Si substrate other than the active region is removed by etching, using the entire sNa film/cutan 3' as a mask. At this time, since the thermal oxide film 16 had formed a bird's beak 17, an overhang was formed immediately below the peripheral edge of the 5i5N4 film pattern 3'. Next, field forming area 1
A thin thermal oxidation film of about 100 people on the Si surface of B
9 and then psi3N4 by reduced pressure CVN method.
The film 20 is grown on the entire film surface (FIG. 2(d)). This 5is
If the Na film 20 is too thick, defects will occur in the Si substrate 1 due to stress caused by the difference in coefficient of thermal expansion between the Si3N4 film 20 and the Si substrate 1 during field selective oxidation. From this, the thickness of the 5i5N4 film 20 is 100
The thickness is preferably 0 Å or less.

次に、リアクティブイオンエツチング技術による異方性
エツチング方法により、第2の5isNa膜2Off:
選択エツチングし、第3図(el)のようにF3i、s
Na膜パターン3′ 周縁部オー/(−/1ング下方部
にのみ第2の5i−3N4膜20’ を残す。ここで第
2の5isNa膜20のエツチング過程において、前工
程で第1の5isN4膜)(ターン3′の周縁部は、オ
ーバーハング状態にしであるため、第2のSi sea
膜20も第3図(el)に示すように、オーツ(−/)
ング状態に堆積されておシ、この状態で、異方性エツチ
ングにより、第2の5isN4膜20をその膜厚分たけ
エツチングすれば、第18i3N4ノくターフ3′周縁
部のオーバI・ンダ下方部に第2の5i5N4膜20”
i確実に残せる6次に、第3図(幻のように、第1の5
13Na膜パターン3′および第2の513N4膜20
′をマスクとしてウェット酸化をき、第1のS i ’
3 N a膜パターン3′ 周縁部は、第2のSi s
N a膜20’の膜厚に対する下層の熱酸化膜19の膜
厚の比率が小さいため、熱酸化膜19を通しての酸化剤
の横拡散が抑制され、したがって、バーズビークが小さ
くなるものである。こうして、フィールド酸化膜を形成
した後、第3図(q)のように、第1の5isN4膜パ
ターン3′および、第2のSi 5N 4膜20′ヲ除
去し、ついで、活性領域予定部の薄い熱酸化膜2を除去
する。その後、フィールド領域で分離された活性領域に
MOS。
Next, the second 5isNa film 2Off:
Selective etching and F3i, s as shown in Figure 3 (el)
The second 5i-3N4 film 20' is left only at the lower part of the peripheral edge of the Na film pattern 3'. membrane) (The peripheral edge of the turn 3' is in an overhanging state, so the second Si sea
The film 20 is also oat (-/) as shown in FIG. 3 (el).
In this state, if the second 5isN4 film 20 is etched by the thickness of the second 5isN4 film 20 by anisotropic etching, the 18i3N4 film 20 will be etched under the periphery of the 18i3N4 turf 3'. A second 5i5N4 film 20”
I can definitely leave 6 Next, Figure 3 (like an illusion, the first 5
13Na film pattern 3' and second 513N4 film 20
′ as a mask, wet oxidation is performed, and the first S i ′
3 Na film pattern 3' peripheral portion is the second Si s
Since the ratio of the thickness of the underlying thermal oxide film 19 to the thickness of the Na film 20' is small, lateral diffusion of the oxidant through the thermal oxide film 19 is suppressed, and the bird's beak is therefore reduced. After forming the field oxide film in this way, as shown in FIG. 3(q), the first 5isN4 film pattern 3' and the second Si5N4 film 20' are removed, and then the area where the active region is to be formed is removed. The thin thermal oxide film 2 is removed. After that, the MOS is placed in the active region separated by the field region.

バイポーラ等の能動素子を形成して半導体装置を製造す
る。第3図では、この能動素子の形成工程全省略したが
、これは、従来の形成工程に準じて行なえばよい。
A semiconductor device is manufactured by forming active elements such as bipolar. In FIG. 3, the entire process of forming the active element is omitted, but this step may be performed according to the conventional forming process.

発明の効果 以上のように、本発明によれば、第15isNa膜パタ
一ン周縁部に第2のS工sN4膜を選択的に形成するこ
とによって、高精度確実に・く−ズビーク抑制領域を形
成できるため、微細な絶縁分離領度の半導体装置の製造
に大きく寄与する。
Effects of the Invention As described above, according to the present invention, by selectively forming the second S-sN4 film on the periphery of the 15th isNa film pattern, the cod beak suppression region can be reliably formed with high precision. Since it can be formed, it greatly contributes to the manufacture of semiconductor devices with fine insulation isolation areas.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(0は、従来の選択酸化法を用いたnチ
ャンネルMO8LSIの製造工程を示す構造断面図、第
2図は、前記工程の選択酸化後の基板状Tμを示す拡大
断面図、第3図(a)〜(q)は、本発明の一実施例全
説明するための、nチャンネルMO8LSIの製造工程
の一部を示す構造断面図である。 1・・・・・・P型シリコン基板、2・・・・・・Si
O2膜、3・・・・・・5isNa膜、4・・・・・・
フォトレジスト、6゜16・・・・・・チャンネルスト
ッパ、6.21・・・・・・フィールド酸化膜、17・
・・・・・オーバーハンダ、18・・・・・・フィール
ド形成領域、19・・・・・・SiO2膜、20・・・
・・・5isNa膜(第2)。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名3図
FIGS. 1(a) to (0) are structural cross-sectional views showing the manufacturing process of an n-channel MO8LSI using a conventional selective oxidation method, and FIG. 2 is an enlarged cross-sectional view showing the substrate shape Tμ after selective oxidation in the above process. 3(a) to 3(q) are structural cross-sectional views showing a part of the manufacturing process of an n-channel MO8LSI for fully explaining one embodiment of the present invention. 1... P-type silicon substrate, 2...Si
O2 film, 3...5isNa film, 4...
Photoresist, 6°16...Channel stopper, 6.21...Field oxide film, 17.
... Over solder, 18 ... Field formation region, 19 ... SiO2 film, 20 ...
...5isNa film (second). Name of agent: Patent attorney Toshio Nakao and one other person

Claims (1)

【特許請求の範囲】 (1)半導体基板表面に酸化膜および第1の絶縁膜を形
成する工程、前記第1の絶縁膜および前記酸化膜の所定
領域に開口部を形成する工程、前記開口部を通じて前記
半導体基板を選択酸化して、バーズビーク状の選択酸化
膜を形成する工程、同選択酸化膜を前記バーズビーク部
に及んでエツチング除去して、前記第1の絶縁膜開口部
周縁部下にオーバハング状開口を形成する工程、前記開
口に露出した半導体基板表面に薄い酸化膜全形成する工
程、全面をおおって、第2の絶縁膜を形成する工程、前
記第2の絶縁膜を異方性にエツチングして、前記第1の
絶縁膜下周縁部の前記オーバーハンダ部分にのみ前記第
2の絶縁膜を残し、他部の前記第2の絶縁膜を除去する
工程、前記第1の絶縁膜開口部を酸化膜で埋める選択的
熱酸化工程をそなえた半導体装置の製造方法。 に))第1の絶縁膜および第2の絶縁膜が窒化シリコン
でなる特許請求の範囲第1項に記載の半導体装置の製造
方法。 (3)第1の絶縁膜下部周縁部のバーズビークの長さを
第2の絶縁膜および同膜下部の薄い酸化膜のトータル膜
厚よりも大きく形成される特許請求の範囲第1項に記載
の半導体装置の製造方法。 (4)第2の絶縁膜が1000A以下でなる特許請求の
範囲第1項、第2項、寸たけ第3項いずれかに記載の半
導体装置の製造方法。
Scope of Claims: (1) A step of forming an oxide film and a first insulating film on the surface of a semiconductor substrate, a step of forming an opening in a predetermined region of the first insulating film and the oxide film, and the opening selectively oxidizing the semiconductor substrate through etching to form a bird's beak-shaped selective oxide film, etching and removing the selective oxide film to the bird's beak portion, and forming an overhang-like shape below the periphery of the first insulating film opening. a step of forming an opening, a step of completely forming a thin oxide film on the surface of the semiconductor substrate exposed in the opening, a step of forming a second insulating film covering the entire surface, and anisotropic etching of the second insulating film. and leaving the second insulating film only in the oversolder portion of the lower peripheral edge of the first insulating film and removing the second insulating film in other parts, the opening of the first insulating film A method for manufacturing a semiconductor device that includes a selective thermal oxidation process that fills the surface with an oxide film. 2)) The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are made of silicon nitride. (3) The method according to claim 1, wherein the length of the bird's beak at the lower peripheral edge of the first insulating film is larger than the total thickness of the second insulating film and the thin oxide film at the bottom of the first insulating film. A method for manufacturing a semiconductor device. (4) The method for manufacturing a semiconductor device according to any one of claims 1, 2, and 3, wherein the second insulating film has a thickness of 1000A or less.
JP18529083A 1983-10-03 1983-10-03 Manufacture of semiconductor device Pending JPS6076138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18529083A JPS6076138A (en) 1983-10-03 1983-10-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18529083A JPS6076138A (en) 1983-10-03 1983-10-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6076138A true JPS6076138A (en) 1985-04-30

Family

ID=16168261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18529083A Pending JPS6076138A (en) 1983-10-03 1983-10-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6076138A (en)

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