JPS5844735A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5844735A
JPS5844735A JP14238381A JP14238381A JPS5844735A JP S5844735 A JPS5844735 A JP S5844735A JP 14238381 A JP14238381 A JP 14238381A JP 14238381 A JP14238381 A JP 14238381A JP S5844735 A JPS5844735 A JP S5844735A
Authority
JP
Japan
Prior art keywords
polysilicon
film
groove
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14238381A
Other languages
Japanese (ja)
Other versions
JPS6359538B2 (en
Inventor
Toshihiko Fukuyama
福山 敏彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14238381A priority Critical patent/JPS5844735A/en
Publication of JPS5844735A publication Critical patent/JPS5844735A/en
Publication of JPS6359538B2 publication Critical patent/JPS6359538B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/763Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To improve the integration of a semiconductor device by forming a polysilicon film on a V-shaped groove surface fromed on an epitaxial layer on an Si substrate, oxidizing the polysilicon film, the epitaxial layer under the film and the surface of the substrate, thereby suppressing the formation of bird beak. CONSTITUTION:An N type epitaxial layer 2 is superposed on an P type Si substrate 1, an Si3N4 mask is coated on an SiO2 film 3, a V-shaped groove is formed, and the groove surface is covered by a CVD method with polysilicon 11. The polysilicon 11 and the surface of the epitaxial layer 2 under the polysilicon and the surface of the substrate 1 are thermally oxidized and are partly formed to SiO2 12. Since the oxidation of the polysilicon is fast, the bird beak formed at the V-shaped groove edge is less. Then, the V-shaped groove is completely filled with the polysilicon as the conventional method, is lapped to Si3N4 film 4, and the polysilicon 13 remains only in the groove. The surface of the polysilicon 13 is thermally oxidized to form a thick SiO2 14. Then, no large bird beak is produced. When the Si3N4 is etched, useless area due to the bird beak can be reduced, thereby improving the integration.

Description

【発明の詳細な説明】 本発明は、半導体装置、より詳細に述べるならば1V又
rtLl*?を多結晶シリコンで埋め次絶縁層分離構造
?有する半導体装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, more specifically, 1V or rtLl*? The next insulating layer separation structure filled with polycrystalline silicon? The present invention relates to a method of manufacturing a semiconductor device having the present invention.

半導体集積回路で・−1岡−基板内に多くの能動素子お
よび受動素子を作り込んで回路機能を構成し、これら素
子同士が相互に電気的な影響を受けないように分離(ア
イソレージ璽ン)する必要がある。この分離にはPN接
合分離、空気層分離、絶縁層分離やこれらの組合せによ
る分離などの方法がある。本発明に1これら分峻方法の
うちで、半導体基体に形成された■又はU溝内表面に絶
縁mt影形成、該絶縁膜上に多結晶シリコンを配設して
なる絶縁層分離、いわゆるV I P (V−groo
veIsolation Po1ycry9tal B
ackfムII )構造を用い次半導体装置に関する。
In semiconductor integrated circuits - 1 Oka - Many active and passive elements are built into a substrate to form a circuit function, and these elements are separated so that they are not affected electrically by each other (isolation). There is a need to. This separation includes methods such as PN junction separation, air layer separation, insulation layer separation, and separation using a combination of these. One of the methods of the present invention is to form an insulating mt shadow on the inner surface of a or U groove formed in a semiconductor substrate, and to separate an insulating layer by disposing polycrystalline silicon on the insulating film, so-called V I P (V-groo
veIsolation Polycry9tal B
ACKF II) relates to the next semiconductor device using the structure.

■IP構造を有する半導体装置は次のようにして製造さ
れている(第1図ないし第6図参照)0第1図に示し虎
ように例えばP型を有するシリコン単結晶基板1の上に
NWシリコンエピタキシャル成長層2(例えば厚さ2.
apwl)’tエピタキシャル成長装置内で形成する。
■ A semiconductor device having an IP structure is manufactured as follows (see Figures 1 to 6). As shown in Figure 1, for example, a NW Silicon epitaxial growth layer 2 (for example, thickness 2.
apwl)'t formed in an epitaxial growth apparatus.

そして、N型エビタ中シャル成長層20表面に熱酸化法
又はCVD(Chemicm’l Vapour i)
@position )法によって二酸化シリコン(8
402)膜3(例えば厚さ1500〔人〕)を形成し、
その上にCVD法によって窒化シリコン<5ksNa)
膜4(例えば厚さ2000(λ〕)を形成する。
Then, a thermal oxidation method or CVD (Chemical Vapor I) is applied to the surface of the N-type epitaxial growth layer 20.
Silicon dioxide (8
402) Forming a film 3 (for example, thickness 1500 [people]),
On top of that, silicon nitride <5ksNa) is applied by CVD method.
A film 4 (for example, thickness 2000 (λ)) is formed.

8輸N4  膜4の上にホトレジスト(図示せず)を塗
布し、所定パターンのマスク會通して露光・現儂する。
A photoresist (not shown) is coated on the N4 film 4, and exposed and developed through a mask having a predetermined pattern.

そして該ホトレジストtマスクとしてS i 3N、膜
4を選択エツチングする。この工i!はホトエツチング
と呼ばれるものである。続いて1Sム02膜5を選択エ
ツチングし、残っている8i02゛   膜3および5
A3N4膜4tマスクとしてエピタキシャル成長層2お
よび単結晶基板1會異方性エツチングして第2図に示し
九■溝【形成する。V溝の光電が基板1内に達するよう
K 5i5N4膜4會適切な穴サイズにエツチング除去
する。t+、V溝の代r)vcU@に等方性工、チング
にて形成することも可能でめる。
Then, the Si 3N film 4 is selectively etched as the photoresist t mask. This engineering! is called photoetching. Subsequently, 1S02 film 5 is selectively etched, and the remaining 8i02 film 3 and 5 are etched.
The epitaxial growth layer 2 and the single crystal substrate 1 are anisotropically etched using the A3N4 film 4t mask to form nine grooves as shown in FIG. The K5i5N4 film 4 is etched and removed to an appropriate hole size so that the photoconductor in the V-groove reaches the inside of the substrate 1. t+, V-groove margin r)vcU@ can also be formed by isotropic machining or ching.

次いで、熱酸化法によってV溝の表面を酸化して810
2膜5(例えば厚さ50口0〔人))1第5図のように
形成する。このとき、■溝の縁にノ(−ドビークロが:
3 i 5N4膜4′を押上げるように発生する。
Next, the surface of the V-groove is oxidized by thermal oxidation to form 810
2 membranes 5 (for example, thickness 50 mm) 1 are formed as shown in FIG. At this time, there is a ノ(-Dobikuro) on the edge of the groove.
3 i It occurs to push up the 5N4 film 4'.

次に、多結晶(ポリ)シリコン層@CVD法によってV
at完全に埋めるように全表面上に形成する。そして、
ポリシリコン層を813N4膜4tでラッピングして■
溝内−のみポリシリコン7(褐4図)會残す。
Next, V
At is formed on the entire surface so as to completely fill it. and,
Wrapping the polysilicon layer with 4t of 813N4 film ■
Polysilicon 7 (brown figure 4) is left only in the groove.

次いで、ポリシリコン70表面部分を熱酸化して厚いs
 i02膜8(例えば厚さ8000(人〕)を第5図の
ように形成する。このとき、先に生じたバードビークが
さらに大きなバードビーク9となってしまう。
Next, the surface portion of the polysilicon 70 is thermally oxidized to form a thick s
An i02 film 8 (for example, 8,000 mm thick) is formed as shown in FIG. 5. At this time, the bird's beak formed earlier becomes an even larger bird's beak 9.

そして、513Na膜4會エツチング除去しく第6図〕
、アイソレージ冒ン領域によってエビタ中シャル層2t
Cuiii定きれ九票子形成領域内に所定のトランジス
タ、抵抗などの素子(図示せず)管形成して半導体装W
/1(IC,L8I’等)k完成させる。
Then, the 513Na film was removed by etching 4 times (Figure 6).
, Evita middle layer 2t due to isolation area
Predetermined transistors, resistors, and other elements (not shown) are formed in the predetermined nine-chip formation region to form a semiconductor device W.
/1 (IC, L8I', etc.) k Complete.

上述した従来工程で半導体装置を製造すると、バードビ
ークが2fの酸化膜1!によって比較的大きく(1ない
し1.5〔2m3幅)なって集積回路の集積化を図るに
は妨げとなるむだな領域が出来てしまう。
When a semiconductor device is manufactured using the conventional process described above, an oxide film 1 with a bird's beak of 2f is produced! This results in a relatively large area (1 to 1.5 [2 m3 width)], creating a wasted area that hinders the integration of integrated circuits.

本発明の目的は、住じるバードビークtより小゛さく抑
えて集積度を高めることである。
The purpose of the present invention is to increase the degree of integration while keeping the size of the bird beak smaller than that of the resident bird beak.

本発明の別の目的は、絶縁層分離構造を形成する際にバ
ードビークを小さくすることのできる半導体装置の製造
方法を提供することである。
Another object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce bird's beak when forming an insulating layer isolation structure.

上述の目的に、半導体装置の絶縁層分離が工程(71〜
(,6: eF’lシリコン単結晶基板上にシリコンエ
ビタ呼シャル成長層を形成する工程;0)選択エツチン
グによってシリコン単結晶基板に達する■又はUill
lk形収する工程:(15)V又σU壽の表面部分を酸
什ルて5i02膜r形成する工程:に)■又はU溝内ポ
リシリコンにより埋める工程;および(9)溝内ポリシ
リコンの表面部分を酸化する工程;によって達成されて
いる半導体装置の製造方法におい′て、前述のV又rt
U#I形成工程の後に、この■又はU溝の表、#iJ上
にポリシリコン膜を形成し、次にこのポリシリコン膜と
その下のエピタキシャル成長層あ・よび単結晶基板のa
rkJ部分とt酸化して前述の酸化膜管形成することを
特徴とする半導体装置の製造方法によって達成される。
For the above purpose, insulating layer separation of semiconductor devices is performed in steps (71 to 71).
(, 6: Step of forming a silicon epitaxial growth layer on eF'l silicon single crystal substrate; 0) Reaching silicon single crystal substrate by selective etching ■ or Uill
(15) Process of forming a 5i02 film r with acid on the surface portion of V or σU: (2) Process of filling the inside of the groove with polysilicon; and (9) Filling the surface of the groove with polysilicon. In the method of manufacturing a semiconductor device achieved by the step of oxidizing the surface portion, the above-mentioned V or rt
After the U #I formation step, a polysilicon film is formed on the surface of this # or U groove, #iJ, and then this polysilicon film, the epitaxial growth layer underneath it, and the a of the single crystal substrate are formed.
This is achieved by a method for manufacturing a semiconductor device characterized by forming the aforementioned oxide film tube by t-oxidizing the rkJ portion.

■父はU#表面上のポリシリコン膜とその下のシリコン
溝表[fiO1分とを酸化して形成した5102膜は従
来工程の溝表面部の酸化によって形成した5i02膜に
対応するわけであり、従来よりも溝表面部分のエピタキ
シャル成長層および単結晶基板のν化される厚さか本発
明の方法では薄いのでI(−ドビークの発生が小さくて
すむ。例えば、8102膜の厚さl5ooo人にする場
合に、従来方赫ではエピタキシャル成長を曽および基板
の溝表面部分の酸化すべき厚さは2500人であるが、
本発明方法ではポリシリコン膜12ooo人厚さとして
成長層および基板の酸化すべき厚さ67500人となる
■The 5102 film formed by oxidizing the polysilicon film on the U# surface and the silicon trench surface [fiO1] below it corresponds to the 5i02 film formed by oxidizing the trench surface in the conventional process. Since the thickness of the epitaxial growth layer and the single crystal substrate on the surface of the groove is thinner in the method of the present invention than in the conventional method, the occurrence of I(-dobeek) can be reduced.For example, if the thickness of the 8102 film is 1500 In this case, in the conventional method, when epitaxial growth is performed, the thickness to be oxidized on the groove surface portion of the substrate is 2,500 mm.
In the method of the present invention, the thickness of the polysilicon film to be oxidized is 67,500 mm, assuming that the polysilicon film is 12 mm thick.

以下、本発明に係る半導体装置の製造方法を添付図面を
参照して詳細に説明−する− 例えばP型のシリコン単結晶基板上KN型シリコンエピ
タキシャル成長層%5i02JIおよびSム、N4 膜
を順次形成し、ホトエツチング法によってSi3N4 
膜と5i02膜を選択エツチングし、そしてこれらの絶
縁膜をマスクとしてNfiエピタキシャル成長層表面か
らP戯半導体基板に到達するV溝又はU#l4pt第2
囚のようにエツチング形成することは既に説明した従来
工程と同じである。
Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained in detail with reference to the accompanying drawings. , Si3N4 by photo-etching method
The film and the 5i02 film are selectively etched, and using these insulating films as a mask, a V-groove or U#l4pt second
The etching process is the same as the conventional process described above.

本発明によれば、■溝形成後に、第7図に示すようにポ
リシリコン膜11(例えば厚さ2000(A〕)tcV
D法によって単結晶基&1とエピタキシャル成長層2と
に設けた■溝の表面を含めた全面に形成する。
According to the present invention, (1) After the groove is formed, as shown in FIG.
It is formed on the entire surface including the surface of the groove (1) provided in the single crystal group &1 and the epitaxial growth layer 2 by method D.

次いで、熱酸化によってポリシリコン膜11を全て酸化
するだけでなくこのポリシリコン膜11Q、−下にある
エピタキシャル成長層の表面および単結晶基l&i表面
も一部(例えば厚さ500〔人〕)酸化して、@8図に
示すように8402膜12(厚さ5ooo(人〕)音形
成する。この熱酸化処理におい′″t[、yt’lシリ
コン膜11の被酸化速廖が大きなため、酸化処理時間に
短くて済みV溝の轍に発生するバードビークの発生量は
少ない。
Next, not only the entire polysilicon film 11 is oxidized by thermal oxidation, but also a portion (for example, 500 mm thick) of the polysilicon film 11Q, the surface of the underlying epitaxial growth layer, and the surface of the single crystal base 1&i are oxidized. Then, as shown in Figure @8, a 8402 film 12 (thickness 5 ooo) is formed. In this thermal oxidation process, the oxidation rate of the silicon film 11 is large; The processing time is short, and the amount of bird beaks that occur in the V-groove ruts is small.

次に〜従来工程と同じようにポリシリラン層tCVD法
によってV#を完全に埋めるように全表面上に形成する
。そして、ポリシリコン層t8i5Na 膜4までラフ
ピングして■溝内にのみポリシリコン13i残す(第9
図)。
Next, as in the conventional process, a polysililane layer is formed on the entire surface by tCVD so as to completely fill V#. Then, the polysilicon layer t8i5Na is roughed up to the film 4, leaving the polysilicon layer 13i only in the groove (9th layer).
figure).

次いで、■溝内のポリシリコン150表面部分を熱酸化
して厚い5iuz膜14(例えば厚さ8000 (A)
) k第10図のように形成する。この5102膜14
は、¥5図の8102膜8に相当するものである。この
とき、ポリシリコン13は・被酸什速饗が大きなため、
比較的短時間の酸化処理で所望の酸化か行なえ、バード
ビークはほとんど成長することなく大きなバードビーク
は発生しない。
Next, the surface portion of the polysilicon 150 in the trench is thermally oxidized to form a thick 5iuz film 14 (for example, 8000 mm thick).
) k Form as shown in Figure 10. This 5102 membrane 14
This corresponds to the 8102 film 8 in the ¥5 figure. At this time, since polysilicon 13 has a large oxidation rate,
The desired oxidation can be carried out in a relatively short oxidation treatment, and the bird's beak hardly grows and no large bird's beak is generated.

しがる後、、 5i5N4膜4tエツチング除去しく第
11図)、アイソレージ冒ン領域によってエピタキシャ
ル42に画定され九素子形成領域内に回路素子會公知の
方法で形成して半導体装置會完成させる。
After that, the 5i5N4 film 4t is removed by etching (FIG. 11), and the semiconductor device is completed by forming an epitaxial layer 42 defined by the isolation exposed region in the nine element forming regions by a method known in the art.

第11図から明らかなように本発明の方法に従って製造
するとバードビークは従来と比較してかなり小さい、シ
喪がって、バードビークのためにむだな領域となる面積
が従来よりも少なくなるので、集積度の向上が可能とな
る。
As is clear from FIG. 11, when the bird's beak is manufactured according to the method of the present invention, it is considerably smaller than the conventional method. It is possible to improve the degree of

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第6図は、従来方法による半導体装置製造
工程を説明する半導体装置の部分断面図であり、および
第7図ないし#!11図に本発ψ」の方法による半導体
装置製造工程を説明する半導体装置の部分断面図である
。 1−0・シリコン単結晶基板、  2@・・・シリコン
エビタ欅シャル成長層、  3・・O・8jOzl[,
4・・・・S轟sN4 膜、  5・・・・8 i02
膜、6 9・oI+ バードビーク、  7・0・ ホ
′リシリコン、 8@@1111犀い5i02膜、  
1111@@@  ポリシリコン膜、  12・・・・
b鳳02HAs   ”・・・・ ポリシリコン、  
14・・・・犀い8102膜。 特許出願人 富士通株式会社 特許出願代理人 弁理士  育  木    朗 弁理士  西  舘  和  之 弁理士  内  1) 幸  男 弁理士  山  口  昭  之 ビ     回    ロ ー          へ        の鰺   
  粉    瀞 巨    r−区 一、T        −0 軒    乏   粉 6     区 の        ■ ト 娘     粉    紐 〇− 耘
FIGS. 1 to 6 are partial cross-sectional views of a semiconductor device illustrating a semiconductor device manufacturing process by a conventional method, and FIGS. 7 to #! FIG. 11 is a partial sectional view of a semiconductor device illustrating a semiconductor device manufacturing process by the method of the present invention. 1-0.Silicon single crystal substrate, 2@...Silicon Ebitashal growth layer, 3..O.8jOzl[,
4...S Todoroki sN4 membrane, 5...8 i02
Membrane, 6 9・oI+ Birdbeak, 7・0・Polysilicon, 8@@1111Sai5i02 membrane,
1111@@@ Polysilicon film, 12...
b Otori 02HAs ”・・・Polysilicon,
14... Rhinoceros 8102 membrane. Patent applicant Fujitsu Ltd. Patent agent Akira Ikuki Kazuyuki Nishidate (patent attorney) 1) Yukio patent attorney Akira Yamaguchi (patent attorney)
Kona 瀞大 r-ku 1, T -0 Ken poor Kona 6 ward ■ To daughter Kona string 〇- 耘

Claims (1)

【特許請求の範囲】 半導体装置の絶縁層分離が下記工!!φ〜(示:(7)
 シリコン単結晶基板上にシリコンエピタキシャル成長
層を形成する工程; (1)選択エツチングによって前記シリコン単結晶基板
に達するV又はU#に形成する工程:(fA  前記V
又はU溝の表面部分を酸化して酸化膜音形成する工程; に)前記■又はU溝を多結晶シリコンにより埋める工程
; および (4)帥記−門の多結晶シリコンの表面部分を酸化する
工l!: によって達成されている半導体装置の製造方法において
、前記V又はU@形成工程の後に、との■又はU溝の表
面上に多結晶シリコン膜r形成し、次にこの多結晶シリ
コン膜とその下の帥記エピタキシャル取長層および単結
晶基板の表面部分とt酸化して前記酸化膜を形成する工
程を有することt%徴とする半導体装置の製造方法。
[Claims] Insulating layer separation of semiconductor devices is performed using the following process! ! φ~ (shown: (7)
Step of forming a silicon epitaxial growth layer on a silicon single crystal substrate; (1) Step of forming a V or U# that reaches the silicon single crystal substrate by selective etching: (fA the above V
or a step of oxidizing the surface portion of the U-groove to form an oxide film; 2) a step of filling the aforementioned ■ or U-groove with polycrystalline silicon; and (4) oxidizing the surface portion of the polycrystalline silicon of the gate. Engineering! : In the method of manufacturing a semiconductor device achieved by the method, after the V or U@ formation step, a polycrystalline silicon film r is formed on the surface of the (2) or U groove, and then this polycrystalline silicon film A method for manufacturing a semiconductor device comprising the step of oxidizing a lower epitaxial length layer and a surface portion of a single crystal substrate to form the oxide film.
JP14238381A 1981-09-11 1981-09-11 Manufacture of semiconductor device Granted JPS5844735A (en)

Priority Applications (1)

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JP14238381A JPS5844735A (en) 1981-09-11 1981-09-11 Manufacture of semiconductor device

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Application Number Priority Date Filing Date Title
JP14238381A JPS5844735A (en) 1981-09-11 1981-09-11 Manufacture of semiconductor device

Publications (2)

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JPS5844735A true JPS5844735A (en) 1983-03-15
JPS6359538B2 JPS6359538B2 (en) 1988-11-21

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4611386A (en) * 1982-12-27 1986-09-16 Fujitsu Limited Method of producing a semiconductor device
EP0245622A2 (en) * 1986-05-12 1987-11-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
EP0278159A2 (en) * 1986-11-19 1988-08-17 Plessey Overseas Limited Method of manufacturing a semiconductor device comprising an isolation structure
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit
KR100256813B1 (en) * 1993-12-28 2000-05-15 김영환 Semiconductor elenent isolation method
JP2005051225A (en) * 2003-07-10 2005-02-24 Internatl Rectifier Corp Method for forming thick oxide on silicon or silicon carbide for semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4611386A (en) * 1982-12-27 1986-09-16 Fujitsu Limited Method of producing a semiconductor device
EP0245622A2 (en) * 1986-05-12 1987-11-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
EP0278159A2 (en) * 1986-11-19 1988-08-17 Plessey Overseas Limited Method of manufacturing a semiconductor device comprising an isolation structure
EP0278159A3 (en) * 1986-11-19 1990-03-14 Plessey Overseas Limited Method of manufacturing a semiconductor device comprising an isolation structure
KR100256813B1 (en) * 1993-12-28 2000-05-15 김영환 Semiconductor elenent isolation method
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit
JP2005051225A (en) * 2003-07-10 2005-02-24 Internatl Rectifier Corp Method for forming thick oxide on silicon or silicon carbide for semiconductor device

Also Published As

Publication number Publication date
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