JPS5922344A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5922344A
JPS5922344A JP13266482A JP13266482A JPS5922344A JP S5922344 A JPS5922344 A JP S5922344A JP 13266482 A JP13266482 A JP 13266482A JP 13266482 A JP13266482 A JP 13266482A JP S5922344 A JPS5922344 A JP S5922344A
Authority
JP
Japan
Prior art keywords
film
window
polycrystalline silicon
silicon film
element isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13266482A
Other languages
Japanese (ja)
Inventor
Kazunori Imaoka
今岡 和典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13266482A priority Critical patent/JPS5922344A/en
Publication of JPS5922344A publication Critical patent/JPS5922344A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To reduce the generation of bird beaks at both the sides of an element isolation region, and to contrive to enhance the degree of integration of ICs by a method wherein after a window is opened in an Si3N4 film formed on a semiconductor substrate, a polycrystalline silicon film buried inside of the window is etched to make the polycrystalline silicon film to survive completely inside the window or only at the circumferential part in the window thereof. CONSTITUTION:The surface of a P type silicon substrate 1 is oxidized at a high temperature to form an SiO2 film 2, and the Si3N4 film 3 of 1,000Angstrom film thickness is adhered on the upper face thereof according to the CVD method. After a window is opened in an element isolation region forming region, boron ions are implanted. Then the window part is buried completely with the polycrystalline silicon film 10. Then the polycrystalline silicon film 10 is etched according to reactive ion etching to form the sectional construction left with polycrystalline silicon 10 only in the window. When the oxidatin treatment is performed at the high temperature of 900-100 deg.C, the polycrystalline silicon film 10 inside of the window and the silicon substrate 1 positioning thereunder are oxidized to form an SiO2 film 11 to act as the element isolation rgion, and the isolation region and having extremely little generation of bird beaks is obtained.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は半導体装置の製造方法のうち、特に二t′シ化
シリコン(Si20)脱力)らなる絶縁膜分離帯領域の
形成方法の改善に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming an insulating film isolation zone region made of dit' silicon silicide (Si20). .

(b)従来技術と問題点 周知のように半導体集積回路(IC)においては、同一
半導体基板」二に多数の素子が形成され、それらの素子
相互間を分離するための素子分離帯領域が形成される。
(b) Prior Art and Problems As is well known, in a semiconductor integrated circuit (IC), a large number of elements are formed on the same semiconductor substrate, and an element isolation band region is formed to separate the elements. be done.

このような六子分離帯領域の形成は、従前はPN接合分
離法が主体となっていたが、最近では寄生容R4を少、
なくして動作を高速化するため、絶縁体分離法が多く用
いられるようになってきた。それは窒化シリコン(Si
3N4)膜で素子領域をマスクし、高温酸化して選択的
に露出基板面上に5joz膜領域を形成し、この5lo
2膜力)らなる絶縁膜を素子分離帯領域とする方法であ
る。
Previously, the PN junction isolation method was the main method used to form such a hexagonal isolation zone region, but recently, methods have been developed to reduce the parasitic capacity R4.
Insulator separation methods have come into widespread use in order to speed up operation by eliminating these problems. It is silicon nitride (Si
Mask the element region with a 3N4) film and selectively form a 5joz film region on the exposed substrate surface by high-temperature oxidation.
This is a method in which an insulating film consisting of two films is used as an element isolation band region.

このような選択酸化による従来の絶縁体分離領域の形成
方法とその問題点を説明する。第1図ないし第3図はそ
の製造工程順図で、先づ第1図に示すようにPmシロコ
ン基板1の表11iiに膜厚500人の5iQ2膜2を
形成し、その上面に化学気相成長(OVD)法にて膜厚
1000〜I50〇へのS i BN4膜8を被着する
。次いで、第2図に示すように7、J−(イ門、、l−
’?l/”でl−X57klI凸AtfiJ<々−ゞノ
ニ1)々゛した後、四弗化カーボン(CF4 +フレオ
ン)ガスを用いて、露出したSi3N4膜3をエツチン
グ除去しブこ後、その上面力・ら硼素(Bつイオンを注
入する。この(llIII素イ珂ンの注入は5iOz@
分離帯領域の下に高濃度のP+型領域を形成するためで
、これはS 102膜丁曲に11型反転層が発生するこ
とを1(11止するチャネルストッパ層となるものであ
る。
A conventional method of forming an insulator isolation region using such selective oxidation and its problems will be explained. Figures 1 to 3 are sequential diagrams of the manufacturing process. First, as shown in Figure 1, a 5iQ2 film 2 of 500 thickness is formed on the surface 11ii of the Pm silicon substrate 1, and a chemical vapor phase film 2 is formed on the upper surface. A SiBN4 film 8 is deposited to a thickness of 1000 to I500 by an OVD method. Next, as shown in FIG.
'? After etching the exposed Si3N4 film 3 using carbon tetrafluoride (CF4 + freon) gas, the upper surface of the exposed Si3N4 film 3 is removed. Implantation of boron (B) ions.
This is to form a highly concentrated P+ type region under the separation zone region, and this serves as a channel stopper layer that prevents the generation of an 11 type inversion layer in the S102 film.

次いで、第3図に示すように約1000”Cの高温で長
時間加熱して、素子分離帯領域となる5102膜5を生
成する。図示のように、上記したP 型領域6がこの高
温熱処理によって同時に画>1!される。
Next, as shown in FIG. 3, heating is performed at a high temperature of about 1000"C for a long time to form a 5102 film 5 that will become an isolation zone region. As shown in the figure, the above-mentioned P type region 6 is exposed to this high temperature heat treatment. At the same time, the image>1!

ところで、このようにして形成されるS i O211
休5の分離帯領域は、IOの高集積化に伴って、その幅
も次第に狭くなり最近では1.5〜2μかj程度になっ
てきた。そうすれば、第8図に示しているようにバーズ
ビークと称する烏のくちばし状の5iOz+1’J B
がSi3N4膜パターンの下部にまわりこんでj1ン成
され、これが素子形成領域を圧迫し、素子分離帯領域を
大きくするから著しく集積度を阻害することになる。こ
のバーズビークの発生は5i02膜5の膜厚に非常に関
係が深く、例えば5iOz膜5の幅を2μm、膜厚を8
000八とすると、両側にそれぞれ6000人稈度0幅
のバーズビークが発生し、設A(上幅’lμtnの5j
O2[5(Q素子分離’に’、I領域を設けても、その
幅は2. μm+0.6ttntx 2=3.26mと
広いイ1y域が形成される。したがって、これを考慮に
入れて設d1°しなければならず、これは10の高集積
化にとって最大の問題点である。
By the way, S i O211 formed in this way
The width of the isolation zone region in the fifth section has gradually become narrower as IOs have become more highly integrated, and has recently become about 1.5 to 2 μm. Then, as shown in Figure 8, a crow's beak-shaped 5iOz+1'J B
is formed around the lower part of the Si3N4 film pattern, compressing the element formation area and enlarging the element isolation zone area, which significantly impedes the degree of integration. The occurrence of this bird's beak is very closely related to the thickness of the 5i02 film 5. For example, if the width of the 5iOz film 5 is 2 μm and the film thickness is 8 μm,
0008, a bird's beak with 6000 culms and 0 width will occur on both sides, and the configuration A (5j with upper width 'lμtn) will occur.
Even if an I region is provided in O2 [5 (Q element isolation), a wide I1y region is formed with a width of 2. μm + 0.6ttntx 2 = 3.26 m. Therefore, the design should take this into consideration. d1°, which is the biggest problem for high integration of 10.

(C)  発明の目的 本発明は上記のバーズビークの発生を極力抑制する形成
方法を提案するものである。
(C) Object of the Invention The present invention proposes a forming method that suppresses the above-mentioned bird's beak as much as possible.

(d)  発明のh′q成 その目的は、半導体基板上に形成したS+3N4j模を
選択的に窓あけした後、その上1rliに多結晶シリコ
ン膜を仮着して、上記膝内部を埋没する工程と、該多結
晶シリコン膜をエツチングし゛(%S i3N4膜上の
多結晶シリコン腺を除去し、上記苦、内部全面あるいは
該窓内の周縁1迅分にのみ多結晶シリコン膜を残存する
工程と、該多結晶シリコン膜ならびに窓内部の半導体基
板を高+2!酸化して絶縁11A分離帯を形成する工程
が含まれる製造方法によって達成することができる。
(d) H'q formation of the invention The purpose is to selectively open a window in the S+3N4j pattern formed on a semiconductor substrate, and then temporarily attach a polycrystalline silicon film to the 1rli to bury the inside of the knee. The process of etching the polycrystalline silicon film (removing the polycrystalline silicon glands on the Si3N4 film and leaving the polycrystalline silicon film only on the entire internal surface or just one part of the periphery within the window) This can be achieved by a manufacturing method that includes the step of oxidizing the polycrystalline silicon film and the semiconductor substrate inside the window to a high +2! value to form an insulating 11A isolation zone.

(e)  発明の実1ii[i例 ところで、このようなバーズビークはS I 3N4膜
3とシリコン基板1との間に介在する薄いS iOz膜
2をなくすれば、バーズビークは発生しにくく、またシ
ロ化しても非常に小さいものとなる。し力)しながら、
5lo2膜2をなくすれば、直1dsiaN4膜がシリ
コン基板に被着するため、シリコン基板を汚染したり機
械的なストレスをシリコン基板に与えたりする問題があ
り、更にSi3N4膜をエツチング除去する場合に、O
F4ガスを用いるドライエツチングによるとシリコン基
板との間にエツチングか択比が少ないのでシリコン基板
が傷められ、また+16 mを用いるウェットエツチン
グによると、燐(P)がシリコンl、(板に11宥し、
汚染きれるなどの問題かおこる。
(e) Practical Example 1ii [i Example] By the way, if the thin SiOz film 2 interposed between the S I 3N4 film 3 and the silicon substrate 1 is eliminated, the bird's beak will be less likely to occur, and the bird's beak will be less likely to occur. Even if it does, it will be very small. while)
If the 5LO2 film 2 is eliminated, the 1dsiaN4 film will adhere directly to the silicon substrate, which will cause problems such as contaminating the silicon substrate and applying mechanical stress to the silicon substrate.Furthermore, when removing the Si3N4 film by etching, , O
Dry etching using F4 gas damages the silicon substrate due to the low etching selectivity with the silicon substrate, and wet etching using +16 m shows that phosphorus (P) is exposed to silicon l, (11 m) on the board. death,
Problems such as contamination may occur.

したがって、゛本発明は5iOz膜2を介在させ、且つ
バーズビークの発生を極めて少なくする形成方法であり
、以下本発明を図面を跡1h:i して741’ j:
lllに説明する。第4図ないし第8図は一実施例の鯛
鮨工程順断面(9)を示しており、先づ第4図に示すよ
うにP型シリコン捕板10表面を室温酸化して8102
膜2を形成し、その上面にCVD法にて膜厚1000〜
1500 ”Cの5i3N41換3を仮着する。次いて
第5図に示すようにレジスト膜4をパターンニングし、
エツチングして素子分屏帯彫成領域を窓ありした後、硼
素をイオン注入する。こ\までは従来と同様の工程であ
るが、次いで第6図に示すようにその北面に厚い例えば
膜厚L〜2μmの多結晶シリコン膜lOをCVD法で仮
着する。このようにjワく多結晶シリコン膜10を仮着
すると、□□□月くのように窓部分も完全に埋め込まれ
る。
Therefore, the present invention is a forming method in which the 5iOz film 2 is interposed and the occurrence of bird's beak is extremely reduced.
Explain to lll. 4 to 8 show cross sections (9) in the order of the sea bream and sushi process of one embodiment. First, as shown in FIG. 4, the surface of the P-type silicon catch plate 10 is oxidized at room temperature and
A film 2 is formed, and a film thickness of 1000~
A 5i3N41 film 3 of 1500"C is temporarily attached. Next, as shown in FIG. 5, the resist film 4 is patterned,
After etching is performed to form a window in the region where the element dividing band is carved, boron ions are implanted. The steps up to this point are the same as those of the conventional method, but then, as shown in FIG. 6, a thick polycrystalline silicon film 1O having a thickness of L to 2 μm, for example, is temporarily deposited on the north surface by CVD. When the polycrystalline silicon film 10 is temporarily attached in this manner, the window portion is also completely buried as shown in □□□.

次いで、第7図に示すように0.1’4ガスを用いたり
アクティブイオンエッチ(ドライエツチングの一種)に
よって多結晶シリコン膜をエツチングして、窓内部にの
み多結晶シリコン膜10を残存させる。このリアクティ
ブイオンエッチすれば多結晶シリコン膜は垂直にエツチ
ングされて、Sj3N4j]【3か露出してくると、エ
ンチング装置tI′/のエツチング14号が支ってくる
ため、その時点でエツチングを中IJ二すれば、箇)7
図に示す窓内のみ多結晶シリコンをシ略シした吟r山1
構造とすることができる。この場合、別の方法として、
上記の多結晶シリコン膜1F+を11悼厚200〇八程
度にγ赤く被着させ、その上にレジスト膜を塗布する。
Next, as shown in FIG. 7, the polycrystalline silicon film 10 is etched using 0.1'4 gas or by active ion etching (a type of dry etching) to leave the polycrystalline silicon film 10 only inside the window. When this reactive ion etching is performed, the polycrystalline silicon film is etched vertically, and when Sj3N4j][3 is exposed, the etching No. 14 of the etching device tI'/ is supported, so etching must be stopped at that point. Middle IJ 2, clause) 7
Ginrzan 1 with polycrystalline silicon removed only within the window shown in the figure
It can be a structure. In this case, another method is
The above-mentioned polycrystalline silicon film 1F+ is deposited in gamma red to a thickness of about 11 mm, and a resist film is applied thereon.

レジスト膜は低粘度である力・ら流動して四部が埋めら
れ、平滑なレジスト膜面かえられる。し力)る後、スパ
ッタエツチングeこよってレジストIPj%ならびに多
結晶シリコン膜を同時にエツチングすると第7図に示す
ような窓内部のみを多結晶シリコン膜10で埋没した同
様の(荷造に形成することもできる。
The resist film has a low viscosity and flows, filling all four parts and creating a smooth resist film surface. Then, by sputter etching, the resist IPj% and the polycrystalline silicon film are etched at the same time, resulting in the formation of a similar (packaging material) in which only the inside of the window is buried with the polycrystalline silicon film 10, as shown in FIG. You can also do it.

吹いで、第8図に示すように900〜1100°Cの1
°、II濡度で酸化処理すれば、窓内部の多結晶シリコ
> 1+’A川およびその下のシリコン、!+(板lが
酸化きれて素子分離帯としての5j02膜11が形成さ
れ、それは極めてバーズビークの発生が少ないものとな
る。
1 at 900-1100°C as shown in Figure 8.
°, if oxidized at II wetness, the polycrystalline silicon inside the window >1+'A river and the silicon below,! +(The plate 1 is completely oxidized and a 5j02 film 11 is formed as an element isolation band, and the occurrence of bird's beaks is extremely small.

吹に、第9図ないし第11図は本シむ明に力)\る他の
実施例の倶造工稈順断面図である。E iil、!実施
例と同じ< 、S I 3N4 PIAをパターンニン
グして硼素イオンを注入しブこ(第4図および第5図参
照)後に、第9図に示すようにOVD法にて11441
%約1500人の多結晶シリコン膜伎を被着する。次い
で、第10図に示すように上記実1.布例と同様にして
OF4ガスを用いるリアクティブイオンエッチによって
3i3N4膜上の多結晶シリコン膜和をエツチング除去
すると、素子分離帯形成領域の窓部周縁部分は多結晶シ
リコン膜が厚く被着している力)ら、周縁部分のみに多
結晶シリコン膜12を残存させることができる。し力)
る後、高温酸化処理すれば、第11図に示すようにバー
ズビークの極めて少ない素子分離帯の5j02膜13を
形成することができる。
Specifically, FIGS. 9 to 11 are cross-sectional views of the folded culm of other embodiments of the present invention. E il,! After patterning the same S I 3N4 PIA as in Example and implanting boron ions (see Figures 4 and 5), 11441 was formed using the OVD method as shown in Figure 9.
Deposit a polycrystalline silicon film of approximately 1,500%. Next, as shown in FIG. When the polycrystalline silicon film on the 3i3N4 film is etched and removed by reactive ion etching using OF4 gas in the same manner as in the cloth example, a thick polycrystalline silicon film is deposited on the periphery of the window in the device isolation band formation region. The polycrystalline silicon film 12 can be left only in the peripheral portion due to the force applied thereto. power)
After that, by performing high-temperature oxidation treatment, it is possible to form a 5j02 film 13 as an isolation zone with extremely few bird's beaks, as shown in FIG.

このようにして形成すると、多結晶シリコン膜が酸化し
て5jOz膜が形成され、Si3N4膜3の下部の5i
o2膜2が露出していないので、酸素のまわり込みが少
なくなり、バーズビークの5C生が減少する。
When formed in this way, the polycrystalline silicon film is oxidized to form a 5jOz film, and the 5i under the Si3N4 film 3 is
Since the O2 film 2 is not exposed, the amount of oxygen passing around is reduced, and the generation of 5C in the bird's beak is reduced.

(f)  発明の効果 以」二の実1110例力)ら明らかなように、A()^
111jによれは゛素子分離帯領域の両側に/(−ズビ
ークσ)発生木 が少なくなり、ioの実梱度を著しく向」二さ・する効
果がある。
(f) As is clear from the effect of the invention, A()^
111j has the effect of reducing the number of /(-zbeak σ) generation trees on both sides of the device isolation zone region, and significantly improving the packing density of IO.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は従来の製造工程11:i ll+
而図面第4図ないし第8図は本発明にか−るtlW i
i’i: −c l+)顔出t i++i図、第9図な
いし第11図は本発明にか\る他の実1.1ii例の製
造工程順断面図である。 図中、■はシリコンJ^板、2はS I O2膜、8は
SI3N4瞑、4はレジスト膜、5 、11 、13は
5102脱力・らなる素子分1111「帯領域、](1
、12は多結晶シリコン膜、6はP+型領域を示す0 171 第1図 第2図 第3図 第4図 ]
Figures 1 to 3 show the conventional manufacturing process 11:i ll+
Figures 4 to 8 are according to the present invention.
i'i: -c l+) Face appearance t i++i Figures 9 through 11 are sectional views in the order of manufacturing steps of another example 1.1ii according to the present invention. In the figure, ■ is a silicon J^ board, 2 is a SIO2 film, 8 is an SI3N4 film, 4 is a resist film, 5, 11, and 13 are elements consisting of 5102 and 1111 band regions, ] (1
, 12 is a polycrystalline silicon film, 6 is a P+ type region 0 171 Fig. 1 Fig. 2 Fig. 3 Fig. 4]

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成した窒化シリコン膜に選択的に窓あ
けした後、その上面に多結晶シリコン膜をM、着して、
上記惹内部を埋没する工程と、該多結晶シリコン膜をエ
ツチングして、窒化シリコン膜上の多結晶シリコン膜を
除去し、L船窓内部全面あるいは該窓内の周縁部分にの
み多結晶シリコン膜を残存する工程と、該多結晶シリコ
ン膜ならびに窓内部の半導体基板を昂温酸化して絶縁膜
分離帯領域を形成する工程が含まれてなることを特徴と
する半導体装置の製造方法−
After selectively opening a window in a silicon nitride film formed on a semiconductor substrate, a polycrystalline silicon film M is deposited on the upper surface thereof,
The step of burying the inside of the window, and etching the polycrystalline silicon film to remove the polycrystalline silicon film on the silicon nitride film, deposit a polycrystalline silicon film on the entire inside of the L porthole or only on the peripheral part of the window. A method for manufacturing a semiconductor device, comprising a remaining step and a step of oxidizing the polycrystalline silicon film and the semiconductor substrate inside the window to form an insulating film separation zone region.
JP13266482A 1982-07-28 1982-07-28 Manufacture of semiconductor device Pending JPS5922344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13266482A JPS5922344A (en) 1982-07-28 1982-07-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13266482A JPS5922344A (en) 1982-07-28 1982-07-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5922344A true JPS5922344A (en) 1984-02-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP13266482A Pending JPS5922344A (en) 1982-07-28 1982-07-28 Manufacture of semiconductor device

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Country Link
JP (1) JPS5922344A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213143A (en) * 1986-03-13 1987-09-19 Sony Corp Manufacture of semiconductor device
JPS62273555A (en) * 1986-05-22 1987-11-27 Fuji Xerox Co Ltd Electrophotographic sensitive body
US4746625A (en) * 1986-06-09 1988-05-24 Kabushiki Kaisha Toshiba A method of manufacturing semiconductor elements-isolating silicon oxide layers
JPH0267728A (en) * 1988-09-01 1990-03-07 Mitsubishi Electric Corp Formation of element isolating oxide film
EP1094242A1 (en) 1999-10-21 2001-04-25 Honda Giken Kogyo Kabushiki Kaisha Method of and apparatus for manufacturing a belt for continuously variable transmission
JP2009204107A (en) * 2008-02-28 2009-09-10 Toyota Motor Corp Belt assembling jig and belt assembling method
JP2009204106A (en) * 2008-02-28 2009-09-10 Toyota Motor Corp Belt assembling tool and belt assembling method
US8337347B2 (en) 2006-08-28 2012-12-25 Toyota Jidosha Kabushiki Kaisha Driving belt, and device and method for assembling same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213143A (en) * 1986-03-13 1987-09-19 Sony Corp Manufacture of semiconductor device
JPS62273555A (en) * 1986-05-22 1987-11-27 Fuji Xerox Co Ltd Electrophotographic sensitive body
US4746625A (en) * 1986-06-09 1988-05-24 Kabushiki Kaisha Toshiba A method of manufacturing semiconductor elements-isolating silicon oxide layers
JPH0267728A (en) * 1988-09-01 1990-03-07 Mitsubishi Electric Corp Formation of element isolating oxide film
EP1094242A1 (en) 1999-10-21 2001-04-25 Honda Giken Kogyo Kabushiki Kaisha Method of and apparatus for manufacturing a belt for continuously variable transmission
US6684473B1 (en) 1999-10-21 2004-02-03 Honda Giken Kogyo Kabushiki Kaisha Method of and apparatus for manufacturing belt for continuously variable transmission
US8337347B2 (en) 2006-08-28 2012-12-25 Toyota Jidosha Kabushiki Kaisha Driving belt, and device and method for assembling same
JP2009204107A (en) * 2008-02-28 2009-09-10 Toyota Motor Corp Belt assembling jig and belt assembling method
JP2009204106A (en) * 2008-02-28 2009-09-10 Toyota Motor Corp Belt assembling tool and belt assembling method

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