JPH04336447A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPH04336447A JPH04336447A JP10783991A JP10783991A JPH04336447A JP H04336447 A JPH04336447 A JP H04336447A JP 10783991 A JP10783991 A JP 10783991A JP 10783991 A JP10783991 A JP 10783991A JP H04336447 A JPH04336447 A JP H04336447A
- Authority
- JP
- Japan
- Prior art keywords
- film
- trench
- mask
- semiconductor substrate
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000003647 oxidation Effects 0.000 claims abstract description 28
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 46
- 239000000377 silicon dioxide Substances 0.000 description 23
- 235000012239 silicon dioxide Nutrition 0.000 description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 11
- 238000009413 insulation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000011118 potassium hydroxide Nutrition 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は,バイポーラトランジス
タ等, 半導体基板の選択酸化による素子絶縁分離膜等
の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming element insulating isolation films, etc., by selective oxidation of semiconductor substrates, such as bipolar transistors.
【0002】近年の半導体装置においては,素子の高集
積化,微細化が要求されている。このため,従来の半導
体装置表面の素子絶縁分離膜等の占める割合も大きく,
これら素子絶縁分離膜を縮小する技術の開発が必要とな
る。[0002] In recent years, there has been a demand for higher integration and miniaturization of elements in semiconductor devices. For this reason, the proportion of element insulation isolation films on the surface of conventional semiconductor devices is large.
It is necessary to develop a technology to reduce the size of these element isolation films.
【0003】0003
【従来の技術】図4は従来例の説明図である。図におい
て,28はSi基板, 29は第1のSiO2膜,30
は第1の Si3N4膜,31は素子絶縁分離SiO2
膜,32は第2の Si3N4膜,33はレジスト膜,
34はトレンチ, 35は第2のSiO2膜,36は
ポリSi膜, 37は第3のSiO2膜である。2. Description of the Related Art FIG. 4 is an explanatory diagram of a conventional example. In the figure, 28 is a Si substrate, 29 is a first SiO2 film, and 30
is the first Si3N4 film, 31 is the element insulation isolation SiO2
32 is a second Si3N4 film, 33 is a resist film,
34 is a trench, 35 is a second SiO2 film, 36 is a poly-Si film, and 37 is a third SiO2 film.
【0004】従来の半導体装置, 例えば, バイポー
ラトランジスタにおいては, 図4に示すプロセスで素
子絶縁分離膜の形成を行っていた。即ち,図4(a)に
示すように,シリコン(Si)基板28の表面を薄く酸
化して第1の二酸化シリコン(SiO2)膜29を形成
後,その上に第1の窒化シリコン(Si3N4)膜30
を成長し,図示しないレジスト膜をマスクとして,第1
の Si3N4膜30をパタニングする。In a conventional semiconductor device, for example, a bipolar transistor, an element insulating isolation film is formed by a process shown in FIG. That is, as shown in FIG. 4(a), after thinly oxidizing the surface of a silicon (Si) substrate 28 to form a first silicon dioxide (SiO2) film 29, a first silicon nitride (Si3N4) film is formed thereon. membrane 30
was grown, and using a resist film (not shown) as a mask, the first
The Si3N4 film 30 is patterned.
【0005】次いで, 図4(b)に示すように,LO
COS(選択酸化法)によって,Si基板28を酸化し
て, 素子絶縁分離SiO2膜31を形成する。図4(
c)に示すように,第2の Si3N4膜を被覆し,レ
ジスト膜33をマスクとして第2の Si3N4膜32
をパターニングする。Next, as shown in FIG. 4(b), the LO
The Si substrate 28 is oxidized by COS (selective oxidation method) to form an element insulation isolation SiO2 film 31. Figure 4 (
As shown in c), the second Si3N4 film 32 is coated and the resist film 33 is used as a mask.
pattern.
【0006】図4(d)に示すように,第2の Si3
N4膜32をマスクとして, RIE 法による異方性
ドライエッチングにより, 素子絶縁分離SiO2膜3
1及びSi基板28をエッチングして, Si基板28
内にトレンチ(溝)34を形成する。As shown in FIG. 4(d), the second Si3
Using the N4 film 32 as a mask, the element insulation isolation SiO2 film 3 is etched by anisotropic dry etching using the RIE method.
1 and the Si substrate 28, the Si substrate 28 is etched.
A trench 34 is formed therein.
【0007】図4(e)に示すように,トレンチ34の
内壁を酸化して第2のSiO2膜を形成し,続いて,ト
レンチ34内に CVD法により多結晶シリコン(ポリ
Si)膜36を埋め込む。As shown in FIG. 4(e), the inner wall of the trench 34 is oxidized to form a second SiO2 film, and then a polycrystalline silicon (poly-Si) film 36 is formed in the trench 34 by CVD. Embed.
【0008】図4(f)に示すように,第2の Si3
N4膜32をマスクとして選択酸化法によりポリSi膜
36の表面を酸化して第3のSiO2膜37を形成し,
素子絶縁分離SiO2膜31とトレンチ34によるS
i基板28上のバイポーラトランジスタの素子分離が完
了する。As shown in FIG. 4(f), the second Si3
Using the N4 film 32 as a mask, the surface of the poly-Si film 36 is oxidized by selective oxidation to form a third SiO2 film 37.
S by the element insulation isolation SiO2 film 31 and the trench 34
Element isolation of the bipolar transistors on the i-substrate 28 is completed.
【0009】この方法では,Si基板28の選択酸化と
,トレンチ34内のポリSi膜36の表面の選択酸化と
, 二つの選択酸化法の工程があり,素子絶縁分離膜の
形成完了までの工程が長くなる。This method includes two selective oxidation steps: selective oxidation of the Si substrate 28 and selective oxidation of the surface of the poly-Si film 36 in the trench 34, and the steps up to the completion of the formation of the element insulation isolation film. becomes longer.
【0010】また,選択酸化膜のバーズビーク部からト
レンチ迄の距離に,ある程度の余裕が必要となり,素子
絶縁分離膜(フィールドSiO2膜)の占める割合が大
きくなる欠点がある。[0010] Furthermore, a certain amount of margin is required for the distance from the bird's beak portion of the selective oxide film to the trench, which has the disadvantage that the ratio occupied by the element insulating isolation film (field SiO2 film) becomes large.
【0011】[0011]
【発明が解決しようとする課題】従って,素子の微細化
が困難となっており,スループットも悪い。本発明は,
選択酸化膜形成のプロセスを減らし,かつ,余分な選択
酸化膜を作らずに微細なトランジスタを形成する方法を
提供することを目的とする。[Problems to be Solved by the Invention] Therefore, it has become difficult to miniaturize elements and the throughput is also poor. The present invention
It is an object of the present invention to provide a method of reducing the process of forming a selective oxide film and forming a fine transistor without forming an extra selective oxide film.
【0012】0012
【課題を解決するための手段】図1は本発明の原理説明
図である。図において,1は半導体基板,2は第1の絶
縁膜,3は耐酸化性膜,4は第1のレジスト膜,5はト
レンチ,6は第2の絶縁膜,7はポリSi膜,8は第2
のレジスト膜,9は素子分離絶縁膜である。[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a first insulating film, 3 is an oxidation-resistant film, 4 is a first resist film, 5 is a trench, 6 is a second insulating film, 7 is a poly-Si film, and 8 is the second
The resist film 9 is an element isolation insulating film.
【0013】上記の問題点を解決するためには, 従来
方法の半導体基板のLOCOSと,トレンチ内のポリS
i膜のLOCOSの両方で使用する耐酸化性の Si3
N4膜を兼用して,同時にLOCOSを形成することに
より達成できる。[0013] In order to solve the above problems, the conventional method of LOCOS of the semiconductor substrate and the poly-S in the trench are required.
Oxidation-resistant Si3 used in both LOCOS and i-film
This can be achieved by using the N4 film and forming LOCOS at the same time.
【0014】即ち, 本発明の目的は, 図1(a)に
示すように,半導体基板1上に第1の絶縁膜2,耐酸化
性膜3を順次被覆し, 第1のレジスト膜4をマスクと
して,該耐酸化性膜3をパターニングする工程と,図1
(b)に示すように,該耐酸化性膜3をマスクとして,
該半導体基板1にトレンチ5を形成する工程と,図1
(c)に示すように,該トレンチ5内壁に第2の絶縁膜
6を形成し, 該トレンチ5内にポリSi膜7を埋め込
む工程と,図1(d)に示すように,第2のレジスト膜
8をマスクとして,該耐酸化性膜3をパターニングして
, 図1(e)に示すように,素子分離膜形成領域の該
耐酸化性膜3をエッチング除去する工程と,図1(f)
に示すように,該半導体基板1を選択酸化法により酸化
して, 該半導体基板1上に素子分離絶縁膜9を形成す
る工程とを含むことにより達成される。That is, the object of the present invention is to sequentially coat a semiconductor substrate 1 with a first insulating film 2 and an oxidation-resistant film 3, and then coat a first resist film 4 as shown in FIG. 1(a). A step of patterning the oxidation-resistant film 3 as a mask, and a step of patterning the oxidation-resistant film 3 as a mask.
As shown in (b), using the oxidation-resistant film 3 as a mask,
Steps of forming trenches 5 in the semiconductor substrate 1 and FIG.
As shown in FIG. 1(c), a second insulating film 6 is formed on the inner wall of the trench 5, and a poly-Si film 7 is embedded in the trench 5. As shown in FIG. 1(d), a second insulating film 6 is formed on the inner wall of the trench 5. The oxidation-resistant film 3 is patterned using the resist film 8 as a mask, and the oxidation-resistant film 3 in the element isolation film formation region is etched away as shown in FIG. 1(e). f)
As shown in FIG. 2, this is accomplished by including the steps of oxidizing the semiconductor substrate 1 by selective oxidation to form an element isolation insulating film 9 on the semiconductor substrate 1.
【0015】[0015]
【作用】本発明では, Si3N4膜を先ずトレンチエ
ッチングのマスク材として使用したあと,そのまま残し
て置き,次に,Si基板及びトレンチ内のポリSi膜の
両方の選択酸化膜を形成する部分のみ Si3N4膜を
パターニングエッチングして,選択酸化を行う。[Operation] In the present invention, the Si3N4 film is first used as a mask material for trench etching, then left as is, and then only the portions of the Si substrate and the poly-Si film in the trench where the selective oxide film is to be formed are etched. The film is patterned and etched and selectively oxidized.
【0016】これにより,2回必要であった Si3N
4膜成長,選択酸化法,及び Si3N4膜除去のプロ
セスが1回で済み,またトレンチと素子形成部の間の素
子分離絶縁膜をなくすことができ,素子絶縁分離領域の
占有面積を減らすことができる。[0016] As a result, the Si3N
The process of growing 4 films, selective oxidation, and removing the Si3N4 film is required only once, and the device isolation insulating film between the trench and the device forming area can be eliminated, reducing the area occupied by the device isolation region. can.
【0017】[0017]
【実施例】図2,図3は本発明の一実施例の工程順模式
断面図である。図において,10はSi基板, 11は
埋没拡散層, 12はエピタキシャル層, 13は第1
のSiO2膜,14は Si3N4膜, 15は第1の
レジスト膜,16はトレンチ, 17は第2のSiO2
膜,18はポリSi膜, 19は第3のSiO2膜,2
0は第2のレジスト膜,21は素子分離SiO2膜,
22はコレクタコンタクト拡散層, 23はベース拡散
層, 24はエミッタ拡散層, 25はエミッタ電極,
26はベース電極, 27はコレクタ電極である。Embodiment FIGS. 2 and 3 are schematic sectional views in order of steps of an embodiment of the present invention. In the figure, 10 is a Si substrate, 11 is a buried diffusion layer, 12 is an epitaxial layer, and 13 is a first layer.
, 14 is the Si3N4 film, 15 is the first resist film, 16 is the trench, and 17 is the second SiO2 film.
18 is a poly-Si film, 19 is a third SiO2 film, 2
0 is the second resist film, 21 is the element isolation SiO2 film,
22 is a collector contact diffusion layer, 23 is a base diffusion layer, 24 is an emitter diffusion layer, 25 is an emitter electrode,
26 is a base electrode, and 27 is a collector electrode.
【0018】本発明をバイポーラトランジスタの素子分
離領域形成に適用した位置実施例について説明する。図
2(a)に示すように,p型のSi基板10上にn+
型の埋没拡散層11を形成し, 更に,n型のエピタキ
シャル層12を成長する。An embodiment in which the present invention is applied to forming an element isolation region of a bipolar transistor will be described. As shown in FIG. 2(a), n+
A type buried diffusion layer 11 is formed, and an n-type epitaxial layer 12 is further grown.
【0019】図2(b)に示すように,Si基板10表
面を塩酸酸化法にて酸化し 200Åの厚さに第1のS
iO2膜13を形成し, 続いて, CVD 法により
Si3N4膜14を 1,000Åの厚さに成長する
。As shown in FIG. 2(b), the surface of the Si substrate 10 is oxidized using a hydrochloric acid oxidation method, and a first S layer is deposited to a thickness of 200 Å.
An iO2 film 13 is formed, and then a Si3N4 film 14 is grown to a thickness of 1,000 Å by CVD.
【0020】そして, 1μmの厚さの第1のレジスト
膜15をマスクとして, Si3N4膜14をパター
ニングし, その後, 第1のレジスト膜15を除去す
る。図2(c)に示すように, Si3N4膜15をマ
スクとして, RIE 法により第1のSiO2膜14
, エピタキシャル層12, 埋没拡散層11を順次,
異方性ドライエッチングを行い, Si基板10に達す
るトレンチ16を形成する。Then, the Si3N4 film 14 is patterned using the 1 μm thick first resist film 15 as a mask, and then the first resist film 15 is removed. As shown in FIG. 2(c), using the Si3N4 film 15 as a mask, the first SiO2 film 14 is
, epitaxial layer 12 and buried diffusion layer 11 in sequence,
Anisotropic dry etching is performed to form a trench 16 that reaches the Si substrate 10.
【0021】図2(d)に示すように,トレンチ16内
壁に第2のSiO2膜17を形成し, 続いて, CV
D 法によりポリSi膜18を成長し, 苛性カリを用
いたポリッシングにより,トレンチ16内にのみポリS
i膜18を埋め込む。As shown in FIG. 2(d), a second SiO2 film 17 is formed on the inner wall of the trench 16, and then CV
A poly-Si film 18 is grown by the D method, and by polishing with caustic potash, the poly-Si film 18 is grown only in the trench 16.
The i-film 18 is embedded.
【0022】続いて, 図3(e)に示すように,ポリ
Si膜18の表面を選択酸化して, 1,000Åの厚
さに第3のSiO2膜19を形成した後, 第2のレジ
スト膜20をマスクとして,図3(f)に示すように,
素子分離SiO2膜形成領域の Si3N4膜14をエ
ッチング除去する。Subsequently, as shown in FIG. 3(e), the surface of the poly-Si film 18 is selectively oxidized to form a third SiO2 film 19 with a thickness of 1,000 Å, and then a second resist film 19 is formed. Using the film 20 as a mask, as shown in FIG. 3(f),
The Si3N4 film 14 in the element isolation SiO2 film forming region is removed by etching.
【0023】図3(g)に示すように, Si3N4膜
14をマスクとして, Si基板10とトレンチ16内
のポリSi膜18を同時に, 選択酸化して, Si基
板10上, 並びにトレンチ16表面に素子分離SiO
2膜21を 6,000Åの厚さに形成する。As shown in FIG. 3(g), using the Si3N4 film 14 as a mask, the Si substrate 10 and the poly-Si film 18 in the trench 16 are selectively oxidized at the same time, so that the Si substrate 10 and the surface of the trench 16 are oxidized. Element isolation SiO
2 film 21 is formed to a thickness of 6,000 Å.
【0024】続いて, 通常の方法により, 不純物拡
散形成,各種成膜,パターニング,エッチング等の工程
を経て,図3(h)に示すようなバイポーラトランジス
タを形成する。Next, a bipolar transistor as shown in FIG. 3(h) is formed by a conventional method through steps such as impurity diffusion, various film formation, patterning, and etching.
【0025】[0025]
【発明の効果】以上説明したように, 本発明によれば
, Si3N4膜の成長ならびに除去,選択酸化法等
のプロセスが半減でき,またトレンチと素子形成部の間
の素子分離絶縁膜をなくすことができるので,チップサ
イズの小型化,及び信頼性向上に寄与するところが大き
い。[Effects of the Invention] As explained above, according to the present invention, processes such as growth and removal of the Si3N4 film, selective oxidation method, etc. can be halved, and the element isolation insulating film between the trench and the element forming part can be eliminated. This greatly contributes to reducing chip size and improving reliability.
【図1】 本発明の原理説明図[Figure 1] Diagram explaining the principle of the present invention
【図2】 本発明の一実施例の工程順模式断面図(そ
の1)[Fig. 2] Schematic sectional view of the process order of one embodiment of the present invention (Part 1)
【図3】 本発明の一実施例の工程順模式断面図(そ
の2)[Fig. 3] Schematic sectional view of the process order of one embodiment of the present invention (Part 2)
【図4】 従来例の説明図[Figure 4] Explanatory diagram of conventional example
1 半導体基板 2 第1の絶縁膜 3 耐酸化性膜 4 第1のレジスト膜 5 トレンチ 6 第2の絶縁膜 7 ポリSi膜 8 第2のレジスト膜 9 素子分離絶縁膜 10 Si基板 11 埋没拡散層 12 エピタキシャル層 13 第1のSiO2膜 14 Si3N4膜 15 第1のレジスト膜 16 トレンチ 17 第2のSiO2膜 18 ポリSi膜 19 第3のSiO2膜 20 第2のレジスト膜 21 素子分離SiO2膜 22 コレクタコンタクト拡散層 23 ベース拡散層 24 エミッタ拡散層 25 エミッタ電極 26 ベース電極 27 コレクタ電極 1 Semiconductor substrate 2 First insulating film 3 Oxidation-resistant film 4 First resist film 5 Trench 6 Second insulating film 7 Poly-Si film 8 Second resist film 9 Element isolation insulating film 10 Si substrate 11 Buried diffusion layer 12 Epitaxial layer 13 First SiO2 film 14 Si3N4 film 15 First resist film 16 Trench 17 Second SiO2 film 18 Poly-Si film 19 Third SiO2 film 20 Second resist film 21 Element isolation SiO2 film 22 Collector contact diffusion layer 23 Base diffusion layer 24 Emitter diffusion layer 25 Emitter electrode 26 Base electrode 27 Collector electrode
Claims (1)
(2),耐酸化性膜(3) を順次被覆し, 第1のレ
ジスト膜 (4) をマスクとして,該耐酸化性膜(
3) をパターニングする工程と,該耐酸化性膜(3)
をマスクとして, 該半導体基板(1) にトレンチ
(5) を形成する工程と,該トレンチ(5) 内壁に
第2の絶縁膜(6) を形成し, 該トレンチ(5)
内に多結晶シリコン膜(7) を埋め込む工程と,第2
のレジスト膜(8) をマスクとして該耐酸化性膜(3
) をパターニングして,素子分離膜形成領域の該耐酸
化性膜(3) をエッチング除去する工程と,該半導体
基板(1) を選択酸化法により酸化して, 該半導体
基板(1) 上に素子分離絶縁膜(9) を形成する工
程とを含むことを特徴とする半導体装置の製造方法。Claim 1: A first insulating film (2) and an oxidation-resistant film (3) are sequentially coated on a semiconductor substrate (1), and the oxidation-resistant film is coated using the first resist film (4) as a mask. (
3) The step of patterning the oxidation-resistant film (3)
forming a trench (5) in the semiconductor substrate (1) using as a mask, forming a second insulating film (6) on the inner wall of the trench (5);
The step of embedding a polycrystalline silicon film (7) inside the
Using the resist film (8) as a mask, the oxidation-resistant film (3
) and etching away the oxidation-resistant film (3) in the element isolation film formation region, and oxidizing the semiconductor substrate (1) by a selective oxidation method to form a layer on the semiconductor substrate (1). A method for manufacturing a semiconductor device, comprising the step of forming an element isolation insulating film (9).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10783991A JPH04336447A (en) | 1991-05-14 | 1991-05-14 | Fabrication of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10783991A JPH04336447A (en) | 1991-05-14 | 1991-05-14 | Fabrication of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04336447A true JPH04336447A (en) | 1992-11-24 |
Family
ID=14469359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10783991A Withdrawn JPH04336447A (en) | 1991-05-14 | 1991-05-14 | Fabrication of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04336447A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4340226A1 (en) * | 1993-11-25 | 1995-06-01 | Gold Star Electronics | Semiconductor element having reduced bird beak formation |
-
1991
- 1991-05-14 JP JP10783991A patent/JPH04336447A/en not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4340226A1 (en) * | 1993-11-25 | 1995-06-01 | Gold Star Electronics | Semiconductor element having reduced bird beak formation |
DE4340226C2 (en) * | 1993-11-25 | 2002-03-14 | Gold Star Electronics | Component with isolation region structure and method for producing the same |
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A300 | Application deemed to be withdrawn because no request for examination was validly filed |
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