JPS6161431A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6161431A
JPS6161431A JP18390384A JP18390384A JPS6161431A JP S6161431 A JPS6161431 A JP S6161431A JP 18390384 A JP18390384 A JP 18390384A JP 18390384 A JP18390384 A JP 18390384A JP S6161431 A JPS6161431 A JP S6161431A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
silicon film
etching
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18390384A
Other languages
Japanese (ja)
Inventor
Fujiki Tokuyoshi
徳吉 藤樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18390384A priority Critical patent/JPS6161431A/en
Publication of JPS6161431A publication Critical patent/JPS6161431A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To improve the flatness of the surface of a polycrytstalline silicon film in a groove by a method wherein a silica thin film is formed by spin coating after the formation of a polycrystalline silicon film, the silica thin film is subjected to etching foir the partial exposure of the surface of the polycrystalline silicon film, and then the polycrystalline silicon film, and then the polycrystalline silicon film is subjected to etching. CONSTITUTION:A polycrystalline silicon film 16 is formed on a silicon substrate 11 provided with a silicon oxide film 12, silicon nitride film 13, and a groove, whereafter a silica thin film 18 is formed by the spin coating mkethod. The silica thin film 18 is then subjected to anisotropic dry etching, for the exposure of the polycrystalline silicon 16 except in the groove. A process follows wherein the polycrystalline silicon film 16 is subjected to etching by anisotropic plasma IA. A relatively flat surface appears in the groove because at its center etching is less effective due to the remaining silica film 18. An element isolating region is formed when the remaining polycrystalline silicon film 16 is converted into a silicon oxide film 17 by thermal oxidation.

Description

【発明の詳細な説明】 (技術分野) 本発明は、半導体装置の製造方法に関し、特に素子分離
用の埋設多結晶シリコン膜の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a buried polycrystalline silicon film for element isolation.

(従来技術) 従来、素子絶縁分離用の埋設多結晶シリコン膜の形成方
法として、半導体基板表面に形成した溝を多結晶シリコ
ン膜で埋設し、活性領域上の多結晶シリコン膜をエツチ
ング除去し溝内にのみ多結晶シリコン膜を残存させる方
法が主に用いられている。この方法において、活性領域
上の多結晶シリコン膜をエツチングして除去する工程が
難かしく、種々の方法が提案されている。たとえば、多
結晶シリコン膜形成後に、溝内と活性領域上との該膜の
膜厚の差を利用して、全面エツチングによυ、溝内にの
み多結晶シリコン膜を残す方法がある。(参、TEDM
82,9−6)上記方法を第1図〜第4図によシ詳細に
説明する。
(Prior art) Conventionally, as a method for forming a buried polycrystalline silicon film for element isolation, a trench formed on the surface of a semiconductor substrate is filled with a polycrystalline silicon film, and the polycrystalline silicon film on an active region is removed by etching. A method is mainly used in which a polycrystalline silicon film remains only inside. In this method, the step of etching and removing the polycrystalline silicon film on the active region is difficult, and various methods have been proposed. For example, after forming a polycrystalline silicon film, there is a method of etching the entire surface, taking advantage of the difference in film thickness between the trench and the active region, leaving the polycrystalline silicon film only in the trench. (See, TEDM
82, 9-6) The above method will be explained in detail with reference to FIGS. 1 to 4.

第1図は、シリコン半導体基板11表面にシリコン酸化
膜12及びシリコン窒化膜13を形成した後に、フォト
プロセス法を用いて、部分的にシリコン窒化膜13、シ
リコン酸化M12及びシリコン基板11を順次エツチン
グし、基板表面に所望の深さを有する溝14を形成した
後に、熱酸化法によシ該溝14表面にシリコン酸化膜1
5を形成した所である。次に基板表面に多結晶シリコン
膜16を所望の膜厚にて形成する(第2図)。次にプラ
ズマエツチング法によシ、多結晶シリコン膜を部分的に
除去し、シリコン窒化膜13表面を露出させる。その結
果、溝内では実効的1/CM厚が厚い為に、溝が多結晶
シリコン膜で埋設される(第3図)。その後に多結晶シ
リコン膜表面を選択的に熱酸化し、シリコン酸化膜17
を形成する。
FIG. 1 shows that after a silicon oxide film 12 and a silicon nitride film 13 are formed on the surface of a silicon semiconductor substrate 11, the silicon nitride film 13, silicon oxide M12, and silicon substrate 11 are partially etched in sequence using a photo process method. After forming a groove 14 having a desired depth on the surface of the substrate, a silicon oxide film 1 is formed on the surface of the groove 14 by thermal oxidation.
This is where 5 was formed. Next, a polycrystalline silicon film 16 is formed on the substrate surface to a desired thickness (FIG. 2). Next, the polycrystalline silicon film is partially removed by plasma etching to expose the surface of the silicon nitride film 13. As a result, since the effective 1/CM thickness is thick in the trench, the trench is filled with a polycrystalline silicon film (FIG. 3). After that, the surface of the polycrystalline silicon film is selectively oxidized thermally to form a silicon oxide film 17.
form.

以上により、埋設多結晶シリコン膜が形成される(第4
図)。
Through the above steps, a buried polycrystalline silicon film is formed (fourth
figure).

上記従来の製造方法によると、溝内に残存する多結晶シ
リコン膜の表面形状は多結晶シリコン膜形成時の表面形
状がそのまま転写された形となシ、溝の周囲では平坦で
あっても、中央部では深くエツチングされた形状を有し
ている。この形状は、以後の素子形成工程においても変
化せず、素子形成工程におけるパターン切れ不良や、配
線工程における配線間シロート等の不良発生原因となる
など大きな問題となっている。
According to the above-mentioned conventional manufacturing method, the surface shape of the polycrystalline silicon film remaining in the groove is a direct copy of the surface shape when the polycrystalline silicon film was formed, and even if the surface shape around the groove is flat, The central part has a deeply etched shape. This shape does not change in the subsequent element forming process, and has become a major problem, such as causing defects such as pattern breakage in the element forming process and blanking between wires in the wiring process.

(発明の目的) 本発明の目的は、前記、欠点を無クシ、埋設された多結
晶シリコン膜表面を平坦にする新規な製造方法を提供す
ることである。
(Objective of the Invention) An object of the present invention is to provide a novel manufacturing method that eliminates the aforementioned defects and flattens the surface of the buried polycrystalline silicon film.

(発明の構成) 本発明の主たるところは、多結晶シリコン膜形成後に、
多結晶シリコン膜上にシリカ薄膜をスピンコーティング
法により形成する工程と、該シリカ薄膜を食該し、部分
的に多結晶シリコン膜表面を露出させる工程と、しかる
後に多結晶シリコン膜を食刻する工程を有することを特
徴としている。
(Structure of the Invention) The main feature of the present invention is that after forming a polycrystalline silicon film,
A step of forming a silica thin film on a polycrystalline silicon film by spin coating, a step of etching the silica thin film to partially expose the surface of the polycrystalline silicon film, and then etching the polycrystalline silicon film. It is characterized by having a process.

(発明の作用及び効果) 本発明の製造方法を用いると、溝部、多結晶シリコン膜
上にシリカ膜が存在している為に、該シリカ膜がエツチ
ングの部分的なマスク材として働き残存する多結晶シリ
コン膜表面を平坦にすることが可能となる。つま−υ、
多結晶シリコン膜とシリカ膜のエッチ速度の差はプラズ
マエツチング条件により任意に変えることが可能であシ
、このエッチ速度差を所望の値にすることによシ、溝部
中央での多結晶シリコン膜のエツチング量を少なくし、
平坦化を行なうことが可能となる。
(Operations and Effects of the Invention) When the manufacturing method of the present invention is used, since the silica film is present in the trench and on the polycrystalline silicon film, the silica film acts as a partial mask material for etching, and the remaining polycrystalline silicon film acts as a partial mask material for etching. It becomes possible to flatten the surface of the crystalline silicon film. Tsuma-υ,
The difference in etch rate between the polycrystalline silicon film and the silica film can be changed arbitrarily by changing the plasma etching conditions.By setting this etch rate difference to a desired value, the polycrystalline silicon film at the center of the groove can be Reduce the amount of etching,
It becomes possible to perform flattening.

又、シリカ膜と多結晶シリコン膜の選択比を大きくシ、
多結晶シリコン膜を異方性プラズマエッチと等方性プラ
ズマエッチの組み合わせによシエッチングしても平坦化
が可能でちる。
In addition, the selection ratio between the silica film and the polycrystalline silicon film can be increased.
Planarization can also be achieved by etching a polycrystalline silicon film by a combination of anisotropic plasma etching and isotropic plasma etching.

これらの結果溝内での多結晶シリコン膜表面が平坦とな
シ、以後の素子形成工程における加工精度の向上及び、
配線工程における断線不良の大幅な減少が可能となシ、
ひいては大幅な歩留向上が可能となる。
As a result, the surface of the polycrystalline silicon film within the groove is not flat, which improves the processing accuracy in the subsequent element forming process.
A system that can significantly reduce disconnection defects in the wiring process.
As a result, it becomes possible to significantly improve yield.

(実施例) 次に実施例により詳細に説明する。(Example) Next, it will be explained in detail using examples.

シリコン基板上に多結晶シリコン、膜を形成する工程迄
は従来の製造方法(第1,2図)と同一である(第5図
)。その次にシリカ薄膜18をスピン・コーティング法
により形成する。シリカ濃度6J%程度の溶液を回転数
300Or、p−mで塗布するとその膜厚は平坦部で約
soo!、溝中央部で約2soo!租度となる(第6図
)。その後、異方性ドライエッチを用いて、シリカ月気
のエツチングを行なう。CF、とH!の混合ガスによる
プラズマエッチを使用し、1分間エツチングする。する
とシリカ膜が約5ooAの厚さ迄エツチングされ、港部
以外の多結晶シリコン表面が露出する(第7図)。
The process up to the step of forming polycrystalline silicon and a film on a silicon substrate is the same as the conventional manufacturing method (FIGS. 1 and 2) (FIG. 5). Next, a silica thin film 18 is formed by spin coating. When a solution with a silica concentration of about 6 J% is applied at a rotational speed of 300 Orr and pm, the film thickness on the flat part is approximately so! , about 2 soo at the center of the groove! It becomes a tax (Figure 6). Thereafter, the silica film is etched using anisotropic dry etching. CF, and H! Etching is performed for 1 minute using plasma etching using a mixed gas. Then, the silica film is etched to a thickness of about 50A, and the polycrystalline silicon surface other than the ports is exposed (FIG. 7).

次に多結晶シリコン膜を異方性プラズマ1.Aによ)エ
ツチングする。このとき多結晶シリコン膜とシリカ膜の
選択比を3〜4程度とし、シリカ膜のエツチング速度を
多結晶シリコン膜のエツチング速度゛よりも遅くする。
Next, the polycrystalline silicon film is coated with anisotropic plasma 1. A) Etching. At this time, the selectivity ratio between the polycrystalline silicon film and the silica film is set to about 3 to 4, and the etching rate of the silica film is made slower than the etching rate of the polycrystalline silicon film.

たとえばCC4F +0. (10%)のエツチングガ
スを使用し真空度0.4〜0.6Torvの条件が適し
ている。すると溝中央部ではシリカ膜により、エツチン
グ量が、他所よりも少なくなる為に第8図に示す様にな
めらかな、比較的に平坦な形状となる。この後に、残存
、多結晶シリコン膜表面を熱酸化し、シリコン酸化膜1
7を形成することによシ素子分離領域が形成されたこと
となる(第9図)。
For example, CC4F +0. (10%) etching gas and a vacuum degree of 0.4 to 0.6 Torv are suitable. As a result, the amount of etching in the central part of the groove is smaller than that in other parts due to the silica film, resulting in a smooth and relatively flat shape as shown in FIG. After this, the remaining polycrystalline silicon film surface is thermally oxidized, and the silicon oxide film 1
By forming 7, an element isolation region is formed (FIG. 9).

(発明のまとめ) 以上詳細に説明した様に本発明によると、シリコン基板
表面に素子分離用の溝を形成した後に、溝表面に絶縁膜
を形成し、その後に1基板表面に該溝埋設用の多結晶シ
リコン膜を形成し、該多結晶シリコン膜上の該溝の中央
附近にシリカ膜パターンを形成する。その彼に、多結晶
シリコン膜をエツチングするととくよシ、溝を多結晶シ
リコン膜によシ埋設する。
(Summary of the Invention) As described in detail above, according to the present invention, after forming a trench for element isolation on the surface of a silicon substrate, an insulating film is formed on the surface of the trench, and then a trench embedding film is formed on the surface of one substrate. A polycrystalline silicon film is formed, and a silica film pattern is formed near the center of the groove on the polycrystalline silicon film. Then, when the polycrystalline silicon film is etched, a groove is filled in with the polycrystalline silicon film.

これによシ、埋設された溝内の多結晶シリコン膜表面の
平坦性が改善され、以後の素子形成工程が容易とな)、
配線工程における断線不良も大幅に低減することが可能
とな夛、シいては歩留向上が期待できる。
This improves the flatness of the surface of the polycrystalline silicon film within the buried trench, facilitating the subsequent device formation process).
It is also possible to significantly reduce disconnection defects in the wiring process, and it is therefore expected to improve yield.

説明は、シリカ膜を使用する方法について行なったが、
代わ#)VCレジスト膜を用いても同様の効果が期待で
きる。又、溝の代わシに孔が形成されていても同様の結
果がイ!Jられることは容易に推測される。
The explanation was about the method of using silica membrane, but
Alternative #) A similar effect can be expected by using a VC resist film. Also, the same result can be obtained even if holes are formed in place of grooves! It is easy to guess that he will be rejected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図は従来技術による製造方法を示す断面図
であシ、第5図〜第9図に本発明の実施例による製造方
法の主たる工程の断面図を示す。 11・・・・・・半導体基板、12,15.17・・・
・・・シリコン酸化膜、13・・・・・・シリコン窒化
膜、14・・・・・・溝、16・・・・・・多結晶シリ
コン膜、18・・団・シリカ膜。
1 to 4 are cross-sectional views showing a manufacturing method according to the prior art, and FIGS. 5 to 9 are cross-sectional views showing main steps of a manufacturing method according to an embodiment of the present invention. 11...Semiconductor substrate, 12,15.17...
... silicon oxide film, 13 ... silicon nitride film, 14 ... groove, 16 ... polycrystalline silicon film, 18 ... group silica film.

Claims (1)

【特許請求の範囲】 1 半導体基板表面に溝又は孔を形成する工程と、該半
導体基板の表面に多結晶シリコン膜を形成する工程と、
該多結晶シリコン膜を食刻し、該溝又は孔内に多結晶シ
リコン膜を残存させる工程とを有する半導体装置の製造
方法において、前記多結晶シリコン膜を食刻する工程の
前に、該多結晶シリコン膜上にシリカ薄膜をスピンコー
ティング法により形成する工程と、該シリカ薄膜を食刻
し部分的に該多結晶シリコン膜の表面を露出させる工程
とを有することを特徴とする半導体装置の製造方法。 2 シリカ薄膜の代わりにフォトレジスト膜を用いるこ
とを特徴とする特許請求の範囲第(1)項記載の半導体
装置の製造方法。
[Claims] 1. A step of forming a groove or a hole on the surface of a semiconductor substrate, a step of forming a polycrystalline silicon film on the surface of the semiconductor substrate,
In the method for manufacturing a semiconductor device, the method includes the step of etching the polycrystalline silicon film and leaving the polycrystalline silicon film in the groove or hole, before the step of etching the polycrystalline silicon film. Manufacturing a semiconductor device comprising the steps of: forming a silica thin film on a crystalline silicon film by spin coating; and etching the silica thin film to partially expose the surface of the polycrystalline silicon film. Method. 2. A method of manufacturing a semiconductor device according to claim (1), characterized in that a photoresist film is used in place of the silica thin film.
JP18390384A 1984-09-03 1984-09-03 Manufacture of semiconductor device Pending JPS6161431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18390384A JPS6161431A (en) 1984-09-03 1984-09-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18390384A JPS6161431A (en) 1984-09-03 1984-09-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6161431A true JPS6161431A (en) 1986-03-29

Family

ID=16143826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18390384A Pending JPS6161431A (en) 1984-09-03 1984-09-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6161431A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008309805A (en) * 2008-09-26 2008-12-25 Fujifilm Corp Light measuring instrument and light measuring method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55154743A (en) * 1979-05-22 1980-12-02 Fujitsu Ltd Semiconductor device and method of fabricating the same
JPS5664453A (en) * 1979-10-31 1981-06-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5763843A (en) * 1980-08-22 1982-04-17 Ibm Method of forming recess dielectric region on silicon substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55154743A (en) * 1979-05-22 1980-12-02 Fujitsu Ltd Semiconductor device and method of fabricating the same
JPS5664453A (en) * 1979-10-31 1981-06-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5763843A (en) * 1980-08-22 1982-04-17 Ibm Method of forming recess dielectric region on silicon substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008309805A (en) * 2008-09-26 2008-12-25 Fujifilm Corp Light measuring instrument and light measuring method

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