JPS6262464B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel method for forming an isolation insulating layer between semiconductor elements.

Conventionally, the VIP format has been known as a technique for separating and insulating elements in integrated circuits using semiconductor elements. The VIP format uses an insulator to isolate elements, so unlike isolation using a PN junction, it has the advantage that, for example, the base region can be brought into direct contact with the isolation layer, allowing semiconductor elements to be formed in a small area. It is possible to form
This is effective for increasing speed.

However, the surface of a semiconductor device using the VIP format is limited to the (100) crystal plane, and the etching speed of the (100) crystal plane is particularly faster when using an alkaline etching solution than other crystal planes.
This type of property is related to the number of atoms on the crystal plane, and it also affects the diffusion process.Semiconductor devices with (100) crystal planes that can adopt the VIP format are , the diffusion rate is faster than in semiconductor devices having other crystal planes. Therefore, if a large number of shallow junctions (shallow diffusion layers) are used as in the first example, it is difficult to control the diffusion process, resulting in the disadvantage that, for example, emitter-base short circuits are likely to occur.

The purpose of the present invention is to form an isolation insulating layer similar to the VIP type on a semiconductor substrate having a crystal plane where such problems are unlikely to occur, that is, an arbitrary crystal plane where diffusion can be easily controlled, such as a (111) crystal plane. ,
Before or after exposing the surface of the photoresist deposited on the semiconductor substrate to form a pattern for forming the element isolation insulating layer, a chlorobenzene solution is infiltrated and the photoresist is developed to form the area for forming the element isolation insulating layer. is removed to form a photoresist pattern with a reverse tapered periphery, followed by reactive sputter etching to form an etched groove with tapered sides in the semiconductor substrate; The method is characterized in that it includes a step of burying an insulator inside the insulator.

Hereinafter, in order to better understand the present invention, one embodiment will be described using cross-sectional views in the order of steps.

As shown in FIG. 1, a silicon oxide film 3 is formed on the surface of an epitaxial layer 2 of a different conductivity type on a silicon substrate 1, a silicon nitride film 4 is deposited on the upper surface, and a positive type photo film is further deposited on the upper surface. Apply resist 5.

Next, as shown in FIG. 2, a resist pattern 6 is formed on the photoresist 5 using a known photolithography technique, but when it is immersed in a chlorobenzene solution and developed before or after the exposure process, the periphery of the resist pattern 6 is The cross section is formed in a reverse tapered shape. This occurs because the portion of the resist penetrated by the chlorobenzene solution has a slow dissolution rate during the development process.

Next, as shown in FIG. 3, the silicon nitride film 4, the silicon oxide film 3, the epitaxial layer 2, and the silicon substrate 1 are etched to form an etching groove 7. When reactive sputter etching using carbon tetrachloride (CCl ₄ ) gas or the like is used as an etching method, in the initial stage of etching, the silicon substrate immediately below the resist opening is etched to the width of the opening above the resist.

As etching continues, the resist is also ashed, so the width of the opening at the top of the resist increases.
As the silicon substrate is etched deeply, etching also progresses in the lateral direction. This reactive sputter etching does not depend on the crystal plane and results in a tapered cross section as shown in the figure. Reactive sputter etching is a method of etching with high precision, and is used to form etching grooves 7 for the above-mentioned reverse tapered resist pattern 6.
The bottom surface is directly sputtered to form a deep groove, and the side surface is tapered.

Next, as shown in FIG. 4, after the resist pattern 6 is removed, a silicon oxide film 3' is formed on the inner surface of the etching groove 7 by heat treatment in an oxygen stream.

Next, as shown in FIG. 5, a polycrystalline silicon layer 8 is deposited by the CVD method to form the etched grooves 7.
Then, by polishing, the polycrystalline silicon layer deposited on the silicon nitride film 4 outside the etching groove is removed.

Next, as shown in FIG. 6, heat treatment is performed again in an oxygen stream to form a silicon oxide film 3'' on the surface of the polycrystalline silicon layer in the etched groove.Finally, the silicon nitride film 4 protecting the surface is removed. When removed by etching, the isolation insulating layer included in the silicon oxide films 3' and 3'' is finished.

When the isolation insulating layer is formed in this way, the surface of the insulating layer is covered with a silicon oxide film with a gentle plane. When reactive sputter etching is performed on the peripheral edge, the sides of the etched groove 7 become vertical.
When the polycrystalline silicon layer 8 is deposited, there are unburied portions, and when it is polished and finished, a crack 10 appears at the center of the etched groove, as shown in FIG. 7, and the surface is not flat. Therefore, if a wiring layer is formed on the upper surface, there is a risk of accidents such as disconnection.

Therefore, as in the present invention, it is essential to make the periphery of the resist pattern inversely tapered and to perform reactive sputter etching.By using such a manufacturing method, the semiconductor substrate surface is limited to the (100) crystal plane. It is possible to form a separation layer made of an insulator without disconnection accidents on the semiconductor substrate on all crystal planes.

As described above, the present invention selects an arbitrary crystal plane and
Since semiconductor elements can be formed in a shallow junction in a small occupied area, it is possible to integrate high-speed integrated circuits at high density, and moreover, it is possible to obtain integrated circuits with high reliability.

[Brief explanation of the drawing]

1 to 6 are cross-sectional views in the order of steps of an embodiment of the present invention, and FIG. 7 is a cross-sectional view for explaining one reason for the present invention. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Epitaxial layer, 3, 3', 3'',...Silicon oxide film, 5...
Photoresist, 6...Resist pattern, 7...
...Etched groove, 8...Polycrystalline silicon layer.

Claims (1)

[Claims] 1 Before or after exposing the surface of the photoresist deposited on the semiconductor substrate to form a pattern for forming the element isolation insulating layer, a chlorobenzene solution is infiltrated and the photoresist is developed to form the element isolation insulating layer. A photoresist pattern having an inverted tapered periphery is formed by removing the formation region of the formation layer, and then reactive sputter etching is performed to form an etched groove with tapered sides in the semiconductor substrate, and then A method of manufacturing a semiconductor device, comprising the step of later burying an insulator inside the etching groove to form the separation insulating layer.