JPS5965447A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5965447A JPS5965447A JP17572582A JP17572582A JPS5965447A JP S5965447 A JPS5965447 A JP S5965447A JP 17572582 A JP17572582 A JP 17572582A JP 17572582 A JP17572582 A JP 17572582A JP S5965447 A JPS5965447 A JP S5965447A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- etching
- recess
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法、特に半導体装置の素子
分離領域の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation region of a semiconductor device.
従来例の構成とその問題点
従来、半導体装置の製造における素子分離領域の形成方
法として、素子分離領域となるべき部分をエツチングし
て凹部を形成した後、凹部内に多結晶シリコンを埋め込
み素子分離領域を形成するという方法がある。その従来
技術の一例を第１図により説明する。Conventional structure and its problems Conventionally, as a method for forming element isolation regions in the manufacture of semiconductor devices, the area that should become the element isolation region is etched to form a recess, and then polycrystalline silicon is buried in the recess for element isolation. There is a method of forming regions. An example of the prior art will be explained with reference to FIG.
シリコン酸化膜（ＳｉＯβ）２及びシリコン窒化膜（８
１３Ｎ４膜）３が形成されたＰ形半導体基板（Ｓｔ 基
板）１上にホトリソ技術により所望の分離パターン巾を
有するホトレジストパターン４を形成する。このホトレ
ジストパターン４をエツチングマスクにしてＳｉ３Ｎ４
膜３及び５ｌｏ２膜２をエツチングした後、異方性ドラ
イエツチングにより８１基板１を目標の深さだけエツチ
ングして凹部５を形成する。そして、チャネルストッパ
ー用のボロンイオン注入を行ない凹部５底面にイオン注
入領域６を形成する（第１図ａ）。Silicon oxide film (SiOβ) 2 and silicon nitride film (8
A photoresist pattern 4 having a desired separation pattern width is formed by photolithography on a P-type semiconductor substrate (St 2 substrate) 1 on which a 13N4 film 3 has been formed. Using this photoresist pattern 4 as an etching mask, Si3N4
After etching the films 3 and 5lo2 films 2, the 81 substrate 1 is etched to a targeted depth by anisotropic dry etching to form the recesses 5. Then, boron ions for a channel stopper are implanted to form an ion implantation region 6 on the bottom surface of the recess 5 (FIG. 1a).
次にホトレジストパターン４を除去し、加熱酸化法によ
り凹部５表面にＳｔ○２膜７を形成する。Next, the photoresist pattern 4 is removed, and an St○2 film 7 is formed on the surface of the recess 5 by a thermal oxidation method.
その後、Ｐｏ ｌ ｙＳ ｉ膜８を形成する（第１図ｂ
）。Thereafter, a PolySi film 8 is formed (Fig. 1b).
).
次に、ドライエツチングあるいはウェットエツチング法
等により５ｉ３Ｎ＝膜３上のＰｏ１ｙＳｉ膜８を除去す
ることによって四部５内にＰｏ１ｙＳｉ膜８ａを残す（
第１図Ｃ）。Next, the Po1ySi film 8a on the 5i3N film 3 is removed by dry etching or wet etching, leaving the Po1ySi film 8a in the four parts 5 (
Figure 1C).
次に、Ｐｏ １ ｙＳ ｉ膜８ａを酸化し、５ＩＯ２膜
９を形成する。その後、Ｓｉ３Ｎ４膜３及びＳ １０２
膜２を除去することによって、第１図ｄの如く、四部６
０犬部分がＰｏ１ｙＳｉ膜８ａで埋−まっている構造を
有する素子分離領域を形成することができる。Next, the Po 1 yS i film 8a is oxidized to form a 5IO2 film 9. After that, Si3N4 film 3 and S102
By removing the membrane 2, the four parts 6 are removed as shown in FIG. 1d.
It is possible to form an element isolation region having a structure in which the zero dog portion is buried with the Po1ySi film 8a.
しかし、上記方法におもては、５ｉ３ｈ４膜３上のＰｏ
１ｙＳｉ膜８をエツチング除去した際、凹部５の領域上
に形成されたＰｏ ｌ ｙＳ ｉ膜８も同じエツチング
レートでエツチングされてし１う゛。そのため、凹部５
内に残存するＰｏ１ｙＳｉ膜８ａには、段差が生じ、Ａ
ＩＶ 配線の断線の原因になるという問題がある。さら
に、凹部５のパターン巾がいろいろと異なっている半導
体装置の場合には、上記の方法を使用することが困難で
ある。なぜならば、比較的微細なパターン巾を有する凹
部で、しかも、パターン巾が一定ならばＳｉ３Ｎ４膜３
上と凹部６上のＰｏ１ｙＳｉ膜の厚さの差によって凹部
６内にＰｏ１ｙＳｉ膜８ａを残存させることができる。However, in the above method, Po on the 5i3h4 membrane 3
When the 1ySi film 8 is etched away, the PolySi film 8 formed on the region of the recess 5 is also etched at the same etching rate. Therefore, the recess 5
A step is formed in the Po1ySi film 8a remaining within the A
IV There is a problem in that it causes disconnection of the wiring. Furthermore, in the case of semiconductor devices in which the pattern widths of the recesses 5 are different, it is difficult to use the above method. This is because the concave portion has a relatively fine pattern width, and if the pattern width is constant, the Si3N4 film 3
Due to the difference in thickness between the Po1ySi film above and the recess 6, the Po1ySi film 8a can remain in the recess 6.
しかし、凹部５のパターン巾が広いと５１３Ｎ４膜上と
凹部上のＰｏ ｌ ｙＳ ｉ膜の厚さが同じ程度になる
ため、５１３Ｎ４膜上のＰｏ１ｙＳｉ膜をエツチングし
た際、凹部５内のＰｏ ｌ ｙＳ ｉ膜も同様に工１．
チングされてしまうだめ、細部内にＰｏ１ｙＳｉが残存
しないという問題点がある。However, if the pattern width of the recess 5 is wide, the thickness of the PolyS i film on the 513N4 film and the recess will be approximately the same, so when the PoIySi film on the 513N4 film is etched, the PolyS in the recess 5 will be Similarly, the i-membrane was processed in step 1.
There is a problem in that Po1ySi does not remain in the details unless it is etched.
また、特開昭５０−１０７８７７号公報には、凹部にホ
トレジストを残存させ、ホトレジストをマスクにして埋
込物質をエツチングし、溝中にのみ埋込物質を残存させ
るという提案がされている。Further, Japanese Patent Application Laid-Open No. 50-107877 proposes leaving photoresist in the recesses, etching the buried material using the photoresist as a mask, and leaving the buried material only in the grooves.
しかしながら上記の例でも、四部の巾が広いとホトレジ
ストが残存しないので、エツチングマスクの役目を果さ
ず、溝中に埋込物質を残存させることができないという
問題点がある。However, even in the above example, there is a problem that if the width of the four parts is wide, no photoresist remains, so the photoresist does not function as an etching mask, and the buried material cannot remain in the groove.
ところで、本発明者らの検削によれば、拡散領域の半導
体膜のエツチングレートが拡散していない領域の半導体
膜のエツチングレートに比べて１０〜２０倍程度速いこ
とを見い出し、その結果、所望領域以外の半導体膜に選
択拡散をした後、選択エッチすれば拡散されていない所
望領域の半導体膜のみが残存することが判明しだ０
発明の目的
本発明はこのような従来の問題に鑑み、半導体膜のパタ
ーンの形成においてエツチングマスクを用いることなく
選択的に形成できる半導体装置の製造方法を提供するこ
とを目的とする。そして、本発明の他の目的は、素子分
離領域となる凹部内に凹部のパターン巾に依存すること
なく、選択的に半導体膜を残存させることによって半導
体基板表面とほぼ同じ高さを有する素子分離領域を精度
良く形成できる半導体装置の製造方法を提供することで
ある。By the way, according to the inspection carried out by the present inventors, it was found that the etching rate of the semiconductor film in the diffusion region is about 10 to 20 times faster than the etching rate of the semiconductor film in the non-diffused region. It has been found that if selective etching is performed after selectively diffusing the semiconductor film outside the region, only the semiconductor film in the desired region that has not been diffused remains. An object of the present invention is to provide a method for manufacturing a semiconductor device that can selectively form a pattern of a semiconductor film without using an etching mask. Another object of the present invention is to selectively leave a semiconductor film in the recesses serving as element isolation regions, without depending on the pattern width of the recesses, so that the element isolation region can be formed at almost the same height as the surface of the semiconductor substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device that can form regions with high precision.
発明の構成
本発明は、半導体基板上に不純物を含んだ堆積被膜（例
えばＰＳＧ膜、Ａｓ ドープｌ’ Ｓ １０２膜）の
パターンを形成した後、堆積被膜の表面層をエツチング
し、半導体膜（例えばＰｏＬｙＳｉ膜、アモルファスＳ
ｔ 膜）を形成し熱処理により堆積被膜パターンから選
択的に半導体膜中へ不純物を拡散して不純物拡散領域を
形成する。その後エツチングレートの差によって選択的
にエツチングレートの速い不純物拡散領域の半導体膜は
除去し、エツチングレートの遅い不純物の拡散されてい
ない領域の半導体膜は残存させるという独特の方法を用
いていることを特徴とするものである。すなわち、素子
分離領域形成において、素子分離領域となる凹部領域以
外の半導体基板表面に不純物を含む堆積被膜を形成し、
その表面層をエツチングしておく。そうすれば、半導体
膜形成後、熱処理により凹部内以外の半導体膜に選択的
に不純物を拡散することができる。選択拡散後、エツチ
ングレートの差によって選択エッチすれば、凹部内の不
純物の拡散されていない半導体膜のみが残存するという
ものである。Structure of the Invention The present invention involves forming a pattern of a deposited film containing impurities (e.g., PSG film, As-doped l' S 102 film) on a semiconductor substrate, etching the surface layer of the deposited film, and etching the semiconductor film (e.g., PoLySi film, amorphous S
t film) is formed, and impurities are selectively diffused from the deposited film pattern into the semiconductor film by heat treatment to form an impurity diffusion region. Then, based on the difference in etching rates, the semiconductor film in the impurity diffusion region where the etching rate is fast is selectively removed, while the semiconductor film in the region where the impurity is not diffused and where the etching rate is slow is left. This is a characteristic feature. That is, in forming an element isolation region, a deposited film containing impurities is formed on the surface of the semiconductor substrate other than the recessed region that will become the element isolation region,
The surface layer is etched. In this way, after the semiconductor film is formed, impurities can be selectively diffused into the semiconductor film other than the inside of the recess by heat treatment. After selective diffusion, if selective etching is carried out based on the difference in etching rate, only the semiconductor film in the recesses in which the impurities have not been diffused remains.
実施例の説明
第２図は半導体膜を埋込み、素子分離領域を形成する本
発明の第１の実施例を示す。DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows a first embodiment of the present invention in which a semiconductor film is buried to form an element isolation region.
Ｐ形Ｓｉ 基板１ｏ上に厚さｏ 、 ｏｓ μｍのＳ
ｉ０２膜１１、約０．１μｍのＳｉ３Ｎ４膜１２及び約
ｏ、２１ＩｒＱの厚さを有する不純物を含んだ堆積被膜
例え°ばＰＳＧ膜１３を形成する。Ｓ ’、３Ｎ４膜１
２は膜化２散防止膜となる。そして、ホトリソ技術によ
り分離領域以外の領域上にホトレジストノくターフ１４
を形成する（第２図ａ）。S with a thickness o and os μm is deposited on a P-type Si substrate 1o.
An i02 film 11, a Si3N4 film 12 of about 0.1 .mu.m, and a deposited film containing impurities, such as a PSG film 13, having a thickness of about 0.21 IrQ are formed. S', 3N4 membrane 1
2 becomes a film to prevent dispersion. Then, using photolithography technology, a photoresist turf 14 is formed on the area other than the separation area.
(Figure 2a).
次に、ホトレジストパターン１４をマスクにしてＰＳＧ
膜１３．Ｓｉ３Ｎ４膜１２．Ｓｉ○２膜１１及びＳｉ
基板１ｏを所望の深さまでエツチングする。Next, using the photoresist pattern 14 as a mask, the PSG
Membrane 13. Si3N4 film 12. Si○2 film 11 and Si
The substrate 1o is etched to a desired depth.
例えば、ＰＳＧ膜１３，５ｉ３Ｎ４１２，５ｉ０２膜１
１のエツチングは、反応性スノくツタエツチング法でエ
ツチングガスとしてＣ２Ｆ６．Ｃ３Ｆ８．Ｃ４Ｆ８゜Ｃ
Ｆ４（Ｓｉ３Ｎ４膜エッチの場合）のいずれかを用いて
行なう。−１：た、Ｓｉ 基板１ｏのエツチングは、反
応性スパンタエッチング法あるいは反応性イオンビーム
エツチング法等のドライエツチング技術で工、）チング
ガスとしてＣＦ４．ＣＣｌ４．ＣＦ２Ｃｌ２゜ＳＦ６の
いずれかを用いてＳｉ 基板１ｏの表面から所望の深さ
までＳＬ をエツチングし、凹部１５を形成する。その
後、Ｓｉ基板１０の導電形と同じ導電形を有する例えば
ボロ／をイオン注入し、凹部１５の底部にチャネルスト
ッパーとなるイオン注入領域１６を形成する（第２図ｂ
）。For example, PSG film 13, 5i3N412, 5i02 film 1
Etching No. 1 was carried out using a reactive slat etching method using C2F6. C3F8. C4F8°C
F4 (in the case of Si3N4 film etching) is used. -1: Etching of the Si substrate 1o was carried out using a dry etching technique such as a reactive spanner etching method or a reactive ion beam etching method.) CF4. CCl4. SL is etched from the surface of the Si substrate 1o to a desired depth using either CF2Cl2°SF6 to form a recess 15. Thereafter, ions of, for example, Boro/, which have the same conductivity type as that of the Si substrate 10, are implanted to form an ion-implanted region 16 that will serve as a channel stopper at the bottom of the recess 15 (FIG. 2b).
).
次に、ホトレジストパターン１４を除去した後、加熱酸
化法により凹部１６表面に絶縁性の薄膜例えば厚さ約０
．１μｍの８１０２膜１７を形成する。Next, after removing the photoresist pattern 14, an insulating thin film, for example, approximately 0 thick, is applied to the surface of the recess 16 by a thermal oxidation method.
．． An 8102 film 17 of 1 μm is formed.
このとき、加熱酸化によりＰＳＧ膜１３０表面層１３ａ
のリン濃度が下がる（第２図Ｃ）。At this time, the surface layer 13a of the PSG film 130 is
phosphorus concentration decreases (Figure 2C).
次にリン濃度の下がっだＰＳＧ膜１３０表面層 ７１３
ａ例えば０．０６μｍ程度をエツチング除去し、リン濃
度の高いＰＳＧ膜１３の表面を露出する（第２図ｄ）。Next, the PSG film 130 surface layer with reduced phosphorus concentration 713
a, for example, about 0.06 μm is removed by etching to expose the surface of the PSG film 13 with a high phosphorus concentration (FIG. 2d).
次ニ、半導体基板上Ｉｄ Ｐｏ ｌ ｙＳ ｉ膜１８を
ＣＶＤ法、蒸着法、スハノタ法等のいずれかの方法によ
り形成する。その後、熱処理を例えば１０００°Ｃで＠
０分間施す。この時、ＰＳＧ膜１膜上３上’ｏｌｙｓｉ
膜１８ａはＰＳＧ膜１膜上３リンが拡散され、凹部１５
内のＰｏ ｌ ｙＳ ｉ膜１８には拡散されない（第２
図ｅ）。Next, an IdPolySi film 18 is formed on the semiconductor substrate by any one of the CVD method, vapor deposition method, Suhanota method, and the like. After that, heat treatment is performed at 1000°C, for example.
Apply for 0 minutes. At this time, 'olysi on PSG film 1 and 3 is
In the film 18a, 3 phosphorus is diffused on the PSG film 1, and the recess 15
It is not diffused into the PolyS i film 18 inside (second
Figure e).
次に、Ｐｏ１ｙＳｉ膜１８ａを兎ノチングする。エツチ
ング液としては、例えば硝酸と弗化水素酸と酢酸か、ら
なる四合液を用いて行なう。この・易合、ＰＳＧ膜１膜
上３りリンが拡散されているＰｏ ｌ ｙＳ ｉ膜１８
ａは、凹部１５内の拡散されていないＰｏ ｌ ｙＳ
ｉ膜１８に比べて１０〜２Ｑ倍程度エツチングレートが
速い。したがって、凹部１５内のＰｏ ｌ ｙＳ ｉ膜
１８をほとんどエツチングすることなく、ＰＳ（４膜１
３上のＰｏ ｌ ｙＳ ｉ膜１８ａを１ノチングするこ
とができ、凹部１５内にはＰｏ ｌ ｙＳ ｉ膜１８が
残存する（第２図ｆ）。Next, the Po1ySi film 18a is notched. As the etching solution, for example, a mixture of nitric acid, hydrofluoric acid, and acetic acid is used. In this case, a PolyS i film 18 in which phosphorus is diffused on the PSG film 1 is used.
a is the undiffused PolyS in the recess 15
The etching rate is about 10 to 2Q times faster than that of the i-film 18. Therefore, the PS (4 films 1
The PolyS i film 18a on the polysilicon layer 3 can be notched one time, and the PolyS i film 18 remains in the recess 15 (FIG. 2f).
次に、ＰＳＧ膜１膜上３ツチング除去する。エツチング
液としては、例えば弗化水素酸と水の混合液あるいは弗
化水素酸と弗化アンモニウムの混合液を用いて行なう。Next, three portions on one PSG film are removed. As the etching solution, for example, a mixed solution of hydrofluoric acid and water or a mixed solution of hydrofluoric acid and ammonium fluoride is used.
その後、Ｓｉ３Ｎ４膜１２を酸化防止マスクにしてＰｏ
１ｙＳｉ膜１８を例えば９００〜１０６０ ”Ｃ、、６
−１０Ａｉｌ ／ ｃｒｌの加圧水蒸気中で酸化し、ｂ
ｚ ０２膜１９を形成する（第２図ｑ）。After that, using the Si3N4 film 12 as an oxidation prevention mask, Po
For example, the 1ySi film 18 has a temperature of 900 to 1060"C, 6
- Oxidized in pressurized steam of 10Ail/crl, b
A Z02 film 19 is formed (FIG. 2q).
次に、Ｓ ｉ３””４膜１２ ＋ ５１０２ 膜１１
、 及ヒ５１０２膜１９の表面層をエツチングすること
によって、第２図りの如＜ Ｓｌ基板１ｏの表面とほぼ
平担なＳｉ○２膜１９膜面９表面る素子分離領域を形成
することができる。Next, S i3""4 film 12 + 5102 film 11
By etching the surface layer of the 5102 film 19, it is possible to form an element isolation region on the surface of the Si○2 film 19, which is almost flat with the surface of the Sl substrate 1o, as shown in the second figure. .
以上、第１の実施例によれば、５ｉｏ２膜１７を形成後
、加熱酸化にょシリン濃度の下がったＰＳＧ膜１膜上３
面層１３ａをエツチング除去し、リン濃度の高いＰＳＣ
ｉ膜１３の表面を露出しておくことにより、Ｐｏ１ｙＳ
ｉ膜１８ａへのリンの拡散が容易になった。それによっ
て、リンを拡散したＰｏ ｌ ｙＳ ｉ膜１８ａと拡散
していないＰｏ ｌ ｙＳ ｉ膜１８とのエツチングレ
ートの差が大きくなり、四部１５内に選択的に、しかも
容易にＰｏ ｌ ｙＳ ｉ膜１８を残存させることがで
きる。As described above, according to the first embodiment, after forming the 5io2 film 17, the heating oxidized phosphoric acid concentration on the PSG film 1 is reduced.
The surface layer 13a is removed by etching to form a PSC with a high phosphorus concentration.
By exposing the surface of the i-film 13, Po1yS
The diffusion of phosphorus into the i-film 18a became easy. As a result, the difference in etching rate between the PolySi film 18a in which phosphorus is diffused and the PolySi film 18 in which phosphorus is not diffused increases, and the PolySi film 18a is selectively and easily etched into the four parts 15. 18 can remain.
次に、本発明の第２の実施例について第３図を用いて説
明する。Next, a second embodiment of the present invention will be described using FIG. 3.
本発明の第１の実施例である第２図ａかち第２図ｄの工
程と同様な方法により、第２図ｄと同様な構造を有する
第３図ａの構造を得る。第３図ａにオイテ、１ｏはＳｉ
基板、１１はＳ １０２膜、１２はＳｉ３Ｎ４膜、１
３はＰＳＧ膜、１５は凹部、１６はイオン注入領域、１
７はＳ ｉ０２膜である。The structure shown in FIG. 3a, which has the same structure as that shown in FIG. 2d, is obtained by a method similar to the steps shown in FIGS. 2a to 2d, which are the first embodiment of the present invention. Figure 3a shows Oite, 1o shows Si
Substrate, 11 is S102 film, 12 is Si3N4 film, 1
3 is a PSG film, 15 is a recess, 16 is an ion implantation region, 1
7 is an Si02 film.
次に、半導体膜例えばＰｏ１ｙＳｉ膜１８をＣＶＤ法、
蒸着法、スパッタ法等のいずれかの方法により形成する
。その後、Ｐｏ１ｙＳｉ膜１８上に外方拡散防止膜とな
る保護膜例えばＳｉＯ２膜２０全２０Ｄ法、加熱酸化法
等のいずれかの方法により形成する（第３図ｂ）。Next, a semiconductor film such as the Po1ySi film 18 is deposited using a CVD method.
It is formed by a method such as a vapor deposition method or a sputtering method. Thereafter, a protective film to serve as an out-diffusion prevention film is formed on the Po1ySi film 18, for example, a SiO2 film 20 by any method such as the full 20D method or the thermal oxidation method (FIG. 3b).
次に、熱処理を例えば１０００°Ｃで３０分間施す（第
３図Ｃ）。このとき、ＰＳＧ膜１膜上３上ｏ ｌ ｙＳ
ｉ膜１８ａはＰＳＧ膜１膜上３リンが拡散され、凹部
１６内のＰｏ１ｙＳｉ膜１８には拡散されない。しかも
、Ｐｏ ｌ ｙＳ ｉ膜１８ａ表面が５ｉ０２膜２ｏに
より保護されているため、ＰＳＧ膜１膜上３Ｐｏ１ｙＳ
ｉ膜１８ａ中に拡散されたリンがＰｏ１ｙＳｉ膜１８ａ
の表面から外方拡散せず、Ｐｏ１ｙＳｉ膜１８ａの表面
濃度が低下しない。Next, heat treatment is performed at, for example, 1000° C. for 30 minutes (FIG. 3C). At this time, olyS on PSG film 1 and film 3 is
In the i film 18a, 3 phosphorus is diffused onto the PSG film 1, but not into the Po1ySi film 18 in the recess 16. Moreover, since the surface of the PolyS i film 18a is protected by the 5i02 film 2o, the 3PolyS i film 18a on the PSG film 1
The phosphorus diffused into the i film 18a is
does not diffuse outward from the surface of the Po1ySi film 18a, and the surface concentration of the Po1ySi film 18a does not decrease.
次に、ＳｉＯ２膜２０全２０した後、第１の実施例であ
る第２図ｆからｈの工程と同様な方法によって、第２図
りと同様な構造を有する素子分離領域を形成することが
できる。Next, after the entire SiO2 film 20 is formed, an element isolation region having a structure similar to that shown in the second diagram can be formed by the same method as the steps shown in FIG. 2 f to h in the first embodiment. .
以上、第２の実施例によれば、Ｐｏ ｌ ｙＳ ｉ膜１
８上にＳ ＩＱ２膜２ｏを形成しているため、熱処理の
際、Ｐｏ ｌ ｙＳ ｉ膜１８−８表面からリンが外方
拡散しないので、Ｐｏ１ｙＳｉ膜１８ａの表面濃度が低
下しない。しだがって、Ｐｏ１ｙＳｉ膜１Ｂ＆を選択エ
ツチングした際、Ｐｏ１ｙＳｉ膜１８ａ表面のリン濃度
低下によるエツチングレートの低下がなく、拡散してい
ないＰｏ ｌ ｙＳ ｉ膜１８とのエツチングレート−
の差が大きくなり、凹部１５内に選択的に、しかも容易
にＰｏ１ｙＳｉ膜１８を残存させることができる０
なお、第１及び第２の実施例において不純物を 。As described above, according to the second embodiment, the PolySi film 1
Since the SiQ2 film 2o is formed on the PolySi film 18-8, phosphorus does not diffuse outward from the surface of the PolySi film 18-8 during heat treatment, so the surface concentration of the PolySi film 18a does not decrease. Therefore, when selectively etching the PolySi film 1B&, there is no decrease in the etching rate due to a decrease in the phosphorus concentration on the surface of the PolySi film 18a, and the etching rate is lower than that of the PolySi film 18 which is not diffused.
The difference between the impurities becomes large, and the Po1ySi film 18 can be selectively and easily left in the recess 15.
含んだ堆積被膜１３としてＰＳＧ膜を用いて説明したが
、ＡＳ ドープドＳ １０２膜でもよい。Although the PSG film has been described as the deposited film 13, an AS doped S 102 film may also be used.
また、第１及び第２の実施例において半導体膜１Ｂとし
てＰｏ ｌ ｙＳ ｉ膜を用いて説明したが、アモルフ
ァスＳｉ 膜でもよいことは言う捷でもない。Furthermore, although the first and second embodiments have been described using a PolySi film as the semiconductor film 1B, it is needless to say that an amorphous Si film may also be used.
さらに、第２の実施例において保護膜２ｏとしてＳ １
０２膜を用いて説明したが、ｉ：１１３Ｎ ４膜あるい
はプラズマＳｉ３Ｎ４膜でもよい。Furthermore, in the second embodiment, S 1 is used as the protective film 2o.
Although the explanation has been made using the 02 film, an i:113N4 film or a plasma Si3N4 film may be used.
発明の効果
以上のように、本発明によれば、除去したい領域の半導
体膜に半導体膜下に形成した不純物を含む堆積被膜から
、選択的に不純物の拡散ができ、しかも、不純物の拡散
されている領域の半導体膜のエツチングレートの差によ
って選択的に不純物の拡散されている領域をエツチング
除去することができる。このことにより、素子分離領域
となる凹部内に容易に、しかも、素子分離領域のパター
ン巾に依存することなく半導体膜を残存させることがで
きる。しだがって、本発明は、素子間分離領域のパター
ン巾が凹部中によって決するため、凹部中以上に素子間
分離領域が広がることがなく、しかも、凸部の少ない素
子間分離領域が形成でき、高密ＩＷな半導体装置の製造
に大きく寄与するものである。Effects of the Invention As described above, according to the present invention, it is possible to selectively diffuse impurities from the deposited film containing impurities formed under the semiconductor film into the semiconductor film in the region to be removed, and moreover, Due to the difference in etching rate of the semiconductor film in the region, the region where the impurity is diffused can be selectively removed by etching. As a result, the semiconductor film can be easily left in the concave portion serving as the element isolation region without depending on the pattern width of the element isolation region. Therefore, in the present invention, since the pattern width of the element isolation region is determined by the inside of the recess, the element isolation region does not spread beyond the inside of the recess, and furthermore, an element isolation region with fewer convex parts can be formed. This will greatly contribute to the production of high-density IW semiconductor devices.
第１図ａ−ｄは従来の素子間分離領域の製造工程断面図
、第２図ａ−ｈは本発明の一実施例にかかる素子間分離
領域の製造工程断面図、第３図ａ〜Ｃは本発明の他の実
施例にかかる素子間分離領域の製造途中工程断面図であ
る。
１０・・・・・・Ｓｔ 基板、１１，１７，１９，２０
・・・・・・５ＩＯ２膜、１２・・・・・・Ｓｉ３Ｎ４
膜、１３・・・・・・ＰＳＧ膜、１５・・・・・・凹部
、１８・・・・・・Ｐｏ１ｙＳｉ膜、１６・・・・・・
イオン注入領域。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第２
図
Ｇ１７
第２図
ｆ６ ／７1A to 1D are cross-sectional views of the manufacturing process of a conventional isolation region, FIGS. 2A to 2H are sectional views of the manufacturing process of an isolation region of the present invention, and FIGS. 3A to C FIG. 2 is a cross-sectional view of an inter-element isolation region in the middle of manufacturing process according to another embodiment of the present invention. 10...St substrate, 11, 17, 19, 20
...5IO2 film, 12...Si3N4
Film, 13...PSG film, 15...Concave portion, 18...PolySi film, 16...
Ion implantation area. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure G17 Figure 2 f6 /7
Claims (9)
る工程と、前記酸化拡散防止膜上に不純物を含む堆積被
膜を形成する工程と、前記堆積被膜及び前記酸化拡散防
止膜の所定の領域をエツチングし、さらに前記半導体基
板を所望の深さまでエツチングし凹部を形成する工程と
、前記凹部表面に薄膜を形成する工程と、前記堆積被膜
の表面層をエツチングする工程と、前記半導体基板上に
半導体膜を形成する工程と、熱処理により１′４ｑ記堆
積被膜から前記半導体膜に不純物を拡散し、不純物拡散
領域を形成する工程と、前記半導体膜を選択的にエツチ
ングし、エツチングレートの速い前記不純物拡散領域の
半導体膜は除去し、エツチングレートの遅い不純物の拡
散されていない凹部内の半導体膜を残存させる工程とを
有することを特徴とする半導体装置の製造方法。(1) A step of forming an oxidation diffusion prevention film on one main surface of a semiconductor substrate, a step of forming a deposited film containing an impurity on the oxidation diffusion prevention film, and a predetermined formation of the deposited film and the oxidation diffusion prevention film. a step of etching the semiconductor substrate to a desired depth to form a recess; a step of forming a thin film on the surface of the recess; a step of etching a surface layer of the deposited film; a step of forming a semiconductor film thereon; a step of diffusing impurities from the deposited film described in 1'4q into the semiconductor film by heat treatment to form an impurity diffusion region; and a step of selectively etching the semiconductor film to increase the etching rate. 1. A method for manufacturing a semiconductor device, comprising the step of removing the semiconductor film in the impurity diffusion region where the etching rate is high, and leaving the semiconductor film in the recess where impurities with a slow etching rate are not diffused.
る特許請求の範囲第１項に記載の半導体装置の製造方法
。(2) The method for manufacturing a semiconductor device according to claim 1, wherein a PSG film is used as the deposited film.
徴とする特許請求の範囲第１項に記載の半導体装置の製
造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein a Po1ySi film is used as the semiconductor film.
と硝酸と酢酸の混合液を用いることを特徴とする特許請
求の範囲第１項に記載の半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein a mixed solution of hydrofluoric acid, nitric acid, and acetic acid is used in the selective etching of the semiconductor film.
る工程と、前記酸化拡散防止膜上に不純物を含む堆積被
膜を形成する工程と、前記堆積被膜及び前記酸化拡散防
止膜の所定の領域をエツチングし、さらに前記半導体基
板を所望の深さまでエツチングし凹部を形成する工程と
、前記凹部表面に薄膜を形成する工程と、前記堆積被膜
の表面層をエツチングする工程と、前記半導体基板上に
半導体膜を形成する工程と、前記半導体膜上に保護膜を
形成する工程と、熱処理により前記堆積被膜がら前記半
導体膜に不純物を拡散し、不純物拡散領域を形成する工
程と、前記保護膜をエツチングする工程と、前記半導体
膜を選択的にエツチングし、半導体膜は除去し、エツチ
ングレートの遅い不純物の拡散されていない凹部内の半
導体膜を残存させる工程とを有することを特徴とする半
導体装置の製造方法。(5) forming an oxidation diffusion prevention film on one principal surface of a semiconductor substrate; forming a deposited film containing impurities on the oxidation diffusion prevention film; and predetermined formation of the deposited film and the oxidation diffusion prevention film. a step of etching the semiconductor substrate to a desired depth to form a recess; a step of forming a thin film on the surface of the recess; a step of etching a surface layer of the deposited film; a step of forming a semiconductor film on the semiconductor film; a step of forming a protective film on the semiconductor film; a step of diffusing impurities from the deposited film into the semiconductor film by heat treatment to form an impurity diffusion region; and a step of selectively etching the semiconductor film, removing the semiconductor film and leaving the semiconductor film in the recess where impurities with a slow etching rate are not diffused. Method of manufacturing the device.
る特許請求の範囲第５項に記載の仝１〈導体装置の製造
方法。(6) A method for manufacturing a conductor device according to claim 5, characterized in that a PSG film is used as the deposited film.
とを特徴とする特許請求の範囲第５項に記載の半導体装
置の製造方法。(7) The method for manufacturing a semiconductor device according to claim 5, wherein a PolySi film is used as the semiconductor film.
と硝酸と酢酸の混合液を用いることを特徴とする特許請
求の範囲第６項に記載の半導体装置の製造方法。(8) The method of manufacturing a semiconductor device according to claim 6, wherein a mixed solution of hydrofluoric acid, nitric acid, and acetic acid is used in the selective etching of the semiconductor film.
る特許請求の範囲第５項に記載の半導体装置の製造方法
。(9) The method for manufacturing a semiconductor device according to claim 5, characterized in that a 3102 film is used as the protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17572582A JPS5965447A (en) | 1982-10-06 | 1982-10-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17572582A JPS5965447A (en) | 1982-10-06 | 1982-10-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5965447A true JPS5965447A (en) | 1984-04-13 |
Family
ID=16001138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17572582A Pending JPS5965447A (en) | 1982-10-06 | 1982-10-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5965447A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4554728A (en) * | 1984-06-27 | 1985-11-26 | International Business Machines Corporation | Simplified planarization process for polysilicon filled trenches |
| US4767722A (en) * | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
-
1982
- 1982-10-06 JP JP17572582A patent/JPS5965447A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4554728A (en) * | 1984-06-27 | 1985-11-26 | International Business Machines Corporation | Simplified planarization process for polysilicon filled trenches |
| US4767722A (en) * | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
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