JPS58213444A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58213444A JPS58213444A JP9640182A JP9640182A JPS58213444A JP S58213444 A JPS58213444 A JP S58213444A JP 9640182 A JP9640182 A JP 9640182A JP 9640182 A JP9640182 A JP 9640182A JP S58213444 A JPS58213444 A JP S58213444A
- Authority
- JP
- Japan
- Prior art keywords
- film
- groove
- semiconductor
- etching
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、そのうち特に、
半導体装置の素子分離領域の形成方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular,
The present invention relates to a method of forming an isolation region of a semiconductor device.
従来、半導体装置の製造における素子分離領域の形成方
法として、素子分離領域となるべき部分をエツチングし
て溝を形成した後、溝内に多結晶／リコンを埋め込み分
離領域を形成するという方法がある。その従来技術の一
例を第１図により説明する。Conventionally, as a method for forming element isolation regions in the manufacture of semiconductor devices, there is a method of etching the part to become the element isolation region to form a groove, and then burying polycrystalline/licon in the groove to form the isolation region. . An example of the prior art will be explained with reference to FIG.
シリコン酸化膜（Ｓｉ０２膜）２及びシリコン窒化膜（
ＳｉｓＮ４膜）３が形成されたＰ形半導体基板（Ｓｉ基
板）１上にホトリソ技術により所望の分離ハターン巾ヲ
有−ｔ−るホトレジスＩ・パターン４を形成する。この
ホトレジストパターン４をエツチングマスクにしてＳｉ
３Ｎ４膜３及び５ｉ０２膜２を工・ツチングした後、異
方性ドライエツチングによりＳｉ基板１を目標の深さだ
けエツチングして溝６を形成する。そして、チャネルス
トッパ用のポロンイオン注入を行ないイオン注入領域６
を形成する（第１図ａ）。Silicon oxide film (Si02 film) 2 and silicon nitride film (
A photoresist I pattern 4 having a desired separation pattern width is formed by photolithography on a P-type semiconductor substrate (Si substrate) 1 on which a SisN4 film 3 has been formed. Using this photoresist pattern 4 as an etching mask, Si
After processing and etching the 3N4 film 3 and the 5i02 film 2, the Si substrate 1 is etched to a target depth by anisotropic dry etching to form a groove 6. Then, poron ions for the channel stopper are implanted into the ion implantation region 6.
(Figure 1a).
次に、ホトレジストパターン４を除去し、加熱酸化法に
より溝６部に５ｉ０２膜７を形成する。そして、ＣＶＤ
法、蒸着法、スパッタ法等によりＰｏ１ｙＳｉ膜βを形
成する（第１図ｂ）。Next, the photoresist pattern 4 is removed and a 5i02 film 7 is formed in the groove 6 by a thermal oxidation method. And CVD
A Po1ySi film β is formed by a method such as a method, a vapor deposition method, a sputtering method, etc. (FIG. 1b).
次に、ドライエツチングあるいはウェットエツチング法
等により、５ｉｓＮ４膜３上のＰｏ１ｙＳｉ膜８を除去
することによって溝５内にＰｏ１ｙＳｉ膜８′を残す（
第１図Ｃ）。Next, the Po1ySi film 8 on the 5isN4 film 3 is removed by dry etching or wet etching, leaving the Po1ySi film 8' in the groove 5 (
Figure 1C).
次に、９００〜ｂ
加圧水蒸気中でＰｏ１ｙＳｉ膜８′を酸化し、ＳｉＯ２
膜９を形成する。その後、Ｓｉ ３Ｎ ａ膜３及びＳｉ
Ｏ２膜２を除去することによって、第１図ｄの如く、溝
６の大部分がＰｏ１ｙＳｉ膜８′で埋まっている構造を
有する素子分離領域を形成することができる。Next, the Po1ySi film 8' is oxidized in 900-b pressurized steam, and the SiO2
A film 9 is formed. After that, the Si 3N a film 3 and the Si
By removing the O2 film 2, it is possible to form an element isolation region having a structure in which most of the groove 6 is filled with the Po1ySi film 8', as shown in FIG. 1d.
しかし、上記方法においては、Ｓｔ、Ｎ４膜３上のＰｏ
１ｙＳｉ膜８をエツチング除去した際、溝６の領域上に
形成されたＰｏ１ｙＳｉ膜８も同じエツチングレートで
エツチングされてしまう。そのだめ、溝６内に残存する
Ｐｏ１ｙＳｉ膜８′には、凹部状のｉ差が生じ、Ａ／配
線の断線の原因になるという問題がある。さらに、溝６
のパターン巾がいろいろと異なっている半導体装置の場
合には、上記方法を使用することが困難である。なぜな
らば、比較的微細な溝で、しかも、溝巾が一定ならば５
ｉ３Ｎａ膜上と溝上のＰｏ１ｙＳｉ膜の厚さの差によっ
て溝内にＰｏ１ｙＳｉ膜を残存させることができる。し
かし、溝巾が広いとＳｉ ５Ｎ ４膜上と溝上のＰｏ１
ｙＳｉ膜の厚さが同じ程度になるため５Ｌ３Ｎ４膜３上
のＰｏ１ｙＳｉ膜８をエツチングした際、溝５内のＰｏ
１ｙＳｉ膜８も同様にエツチングされてしまうため、溝
６内にＰｏ１ｙＳｉ膜が残存しないという問題がある。However, in the above method, the Po on the St, N4 film 3
When the 1ySi film 8 is removed by etching, the Po1ySi film 8 formed on the region of the groove 6 is also etched at the same etching rate. However, there is a problem in that the Po1ySi film 8' remaining in the groove 6 has a concave i difference, which may cause disconnection of the A/wiring. Furthermore, groove 6
It is difficult to use the above method in the case of semiconductor devices whose pattern widths vary. This is because if the groove is relatively minute and the groove width is constant, 5
The difference in thickness between the Po1ySi film on the i3Na film and the Po1ySi film on the groove allows the Po1ySi film to remain in the groove. However, when the groove width is wide, Po1 on the Si 5N 4 film and on the groove
Since the thickness of the ySi films is approximately the same, when the Po1ySi film 8 on the 5L3N4 film 3 is etched, the Po1ySi film in the groove 5 is
Since the 1ySi film 8 is also etched in the same way, there is a problem that no Po1ySi film remains in the groove 6.
そこで、本発明の目的は、多結晶シリコンあるいは無定
形シリコン等の半導体膜のパターンがエツチングマスク
を用いることなく選択的に形成できる半導体装置の製造
方法を提供することである。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which a pattern of a semiconductor film such as polycrystalline silicon or amorphous silicon can be selectively formed without using an etching mask.
そして、本発明の他の目的は、素子分離領域となる溝内
に、溝巾に依存することなく選択的に半導体膜を残存さ
せることによって半導体基板表面とほぼ同じ高さを有す
る素子分離領域を精度良く形成できる半導体装置の製造
方法を提供することである。Another object of the present invention is to form an element isolation region having approximately the same height as the surface of the semiconductor substrate by selectively leaving a semiconductor film in the trench that will become the element isolation region without depending on the trench width. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be formed with high precision.
すなわち、本発明は、拡散した領域の半導体膜のエツチ
ングレートが拡散していない領域の半導体膜のエツチン
グレートに比べて速いことをセルファライン的に用いる
ことによって、素子間分離領域となる溝内に半導体膜を
選択的に残存させ、素子間分離領域を形成することを特
徴とする半導体装置の製造方法である。That is, the present invention utilizes the fact that the etching rate of the semiconductor film in the diffused region is faster than the etching rate of the semiconductor film in the non-diffused region in a self-aligned manner. This is a method of manufacturing a semiconductor device characterized by selectively leaving a semiconductor film to form an isolation region between elements.
以下、本発明について実施例を用いて詳細に説明する。Hereinafter, the present invention will be explained in detail using examples.
第２図は、Ｐｏ１ｙＳｉ膜を埋め込み素子間分離領域を
形成する本発明の第１の実施例を示す。FIG. 2 shows a first embodiment of the present invention in which a Po1ySi film is embedded to form an isolation region between elements.
Ｐ形Ｓｉ基板１ｏ上に厚さ０．０６μｍのＳｉＯ２膜１
１、約０．１ μｍのＳｉ３Ｎ４膜１２及び約０．２．
ｃｚｍの厚さを有する不純物を含んだ堆積被膜例えばＰ
ＳＧ膜１３を形成する。そして、ホトリソ技術により分
離領域以外の領域上にホトレジストパターン１４を形成
し、溝巾ｌを例えば１．６μｍとする（第２図ａ）。SiO2 film 1 with a thickness of 0.06 μm on a P-type Si substrate 1o
1. Si3N4 film 12 of about 0.1 μm and about 0.2.
An impurity-containing deposited film having a thickness of czm, e.g.
An SG film 13 is formed. Then, a photoresist pattern 14 is formed on the region other than the isolation region by photolithography, and the groove width l is set to, for example, 1.6 μm (FIG. 2a).
次に、ホトレジストパターン１４をマスクニジてスパッ
タエツチングする。例えば、０４ＦＢガスを導入し、約
０．０７ Ｔｏｒｒ、 ２００Ｗでプラスマスバッタ
エツチングを行なう。そうすると、ＰＳＧ膜１３、Ｓｉ
、５Ｎ４膜１２、ＳｉＯ２膜１１が除去される。さらに
、例えばＣＦ４ 、００ｔａ 、 ＣＦ２Ｃ７２等のガ
スを導入し、約０．０５ Ｔｏｒｒ、 ａｏｏｗでプラ
ズマスパノタエソチすることによりＳｉ基板１０の表面
から約１．６μｍの深さまでのＳｉをエツチングし、凹
部状の溝１６を形成する（第２図ｂ）。Next, the photoresist pattern 14 is sputter etched using a mask. For example, 04FB gas is introduced and plasma grasshopper etching is performed at approximately 0.07 Torr and 200W. Then, the PSG film 13, Si
, 5N4 film 12, and SiO2 film 11 are removed. Further, by introducing a gas such as CF4, 00ta, CF2C72, etc., and performing plasma etching at about 0.05 Torr and AOOW, Si is etched from the surface of the Si substrate 10 to a depth of about 1.6 μm. A recessed groove 16 is formed (FIG. 2b).
次に、ＨＮＯｓ 、 ＨＦの混合液で溝１５の底面およ
び側面を０．１μｍエツチングし、プラズマスパッタエ
ツチング時に生じた結晶歪、汚染領域を除去する。そし
て、６０ＫｅＶ、約３×１０１５１０ｎＳ／ｃａのボロ
ンをイオン注入し、溝１６の底部にチャネルストッパー
となるイオン注入領域１６を形成する（第２図ｇ）。Next, the bottom and side surfaces of the trenches 15 are etched by 0.1 μm using a mixed solution of HNOs and HF to remove crystal distortion and contaminated areas generated during plasma sputter etching. Then, boron ions of 60 KeV and about 3×10 1510 nS/ca are implanted to form an ion implantation region 16 that will serve as a channel stopper at the bottom of the trench 16 (FIG. 2g).
次に、ホトレジストパターン１４を除去し、加熱酸化法
により溝１６部に絶縁性の薄膜例えば厚さ約０．１μｍ
のＳｉＯ２膜１７を形成する。そして、ＣＶＤ法、蒸着
法、スパッタ法等により、厚さ約０．６μｍのＰｏ１ｙ
Ｓｉ膜１８を形成する（第２図ｄ）。Next, the photoresist pattern 14 is removed, and an insulating thin film, for example, about 0.1 μm thick, is applied to the groove 16 by a thermal oxidation method.
A SiO2 film 17 is formed. Then, by CVD method, vapor deposition method, sputtering method, etc., Poly
A Si film 18 is formed (FIG. 2d).
次に、１０００℃、６０分の熱処理を施す。このとき、
−Ｐ Ｓ Ｇ膜１３上ノＰｏ１ｙＳｉ膜１Ｂ’はｐｓ
Ｇ膜１膜上３リンが拡散され、溝１６内のＰｏ１ｙＳｉ
膜１８は拡散されない。また、５ｉｓＮ＜膜１２が拡散
防止膜となり、８ｉ基板１ｏには拡散されない（第２図
０）。Next, heat treatment is performed at 1000° C. for 60 minutes. At this time,
-PS The Po1ySi film 1B' on the G film 13 is ps
The 3 phosphorus on the G film 1 is diffused, and the Po1ySi in the groove 16 is
Membrane 18 is not diffused. Further, the 5isN< film 12 serves as a diffusion prevention film and is not diffused into the 8i substrate 1o (FIG. 20).
次に、ＨＮＯ３，ＨＦ 、 ＣＨｓ（３００Ｈの混合液
でＰｏ１ｙＳｉ膜１８′をエツチング除去する。この場
合、ＰＳＧ膜１３によりリンが拡散されているＰｏ１ｙ
Ｓｉ膜１８′は、溝１６内の拡散されていないＰｏ１ｙ
Ｓｉ膜１８に比べて１０〜２０倍程度エツチングレート
が速い。したがって、溝１６内のＰｏ１ｙＳｉ膜１８を
ほとんどエツチングすることなく、ＰＳＧ膜１膜上３上
ｏ１ｙＳｉ膜１８′をエツチングすることができ、溝１
６内にＰｏ１ｙＳｉ膜１８が残存する（第２図ｆ）。Next, the Po1ySi film 18' is removed by etching with a mixed solution of HNO3, HF, and CHs (300H).
The Si film 18' covers the undiffused Po1y in the trench 16.
The etching rate is about 10 to 20 times faster than that of the Si film 18. Therefore, the olySi film 18' on the PSG film 1 can be etched without substantially etching the Po1ySi film 18 in the groove 16, and the o1ySi film 18' on the PSG film 1 can be etched.
The Po1ySi film 18 remains within the wafer 6 (FIG. 2f).
次に、ＨＦ 、 Ｈ２Ｏの混合液あるいはＨＦ、ＮＨｄ
Ｆの混合液でＰＳＧ膜１３をエツチングする。その後、
９００〜１０００℃、 −６〜１０ ＴＣｆ／、ｉ、の
加圧水蒸気中で酸化する。この場合、Ｐｏ１ｙ Ｓｉ膜
１８を酸化すると消費されたＳｉの厚さの約２倍のＳｉ
Ｏ２厚さになる。そこで、Ｐｏ１ｙＳｉ膜１８間の距離
Ｘが０，６μｍの場合、厚さ０．６μｍのＳｉＯ２膜を
形成する。そうすると、Ｐｏ１ｙＳｉ膜１８が０．２５
ｐｍ消費され、０．２６μｍ盛り上ってＳｉＯ２膜１
９で溝が埋まる（第２図ｇ）。Next, a mixture of HF and H2O or HF and NHd
The PSG film 13 is etched with a mixed solution of F. after that,
Oxidize in pressurized steam at 900-1000°C, -6-10 TCf/,i. In this case, when the PolySi film 18 is oxidized, the thickness of Si is approximately twice the thickness of the consumed Si.
It becomes O2 thickness. Therefore, when the distance X between the Po1ySi films 18 is 0.6 μm, a SiO2 film with a thickness of 0.6 μm is formed. Then, the Po1ySi film 18 becomes 0.25
pm is consumed and the SiO2 film 1 rises by 0.26 μm.
9 fills the groove (Fig. 2g).
次に、Ｓｉ３Ｎ ４膜１２ 、５ｉＯｚ膜１１及ヒ５ｉ
ｏ２膜１９の表面層をエツチングすることによって、第
２図りの如（Ｓｉ基板１ｏの表面とほぼ平坦な５ｉ０２
膜１９表面を有する素子間分離領域を形成することがで
きる。Next, Si3N4 film 12, 5iOz film 11 and
By etching the surface layer of the O2 film 19, the surface layer 5i02, which is almost flat with the surface of the Si substrate 1o, is etched as shown in the second diagram.
An element isolation region having the surface of the film 19 can be formed.
以上、第２図の方法によれば、溝１６内に選択的に、し
かも、容易にＰｏ１ｙＳｉ膜１８を残存させることがで
き、はぼ完全に溝１６内をＳｉＯ２膜１９で埋めること
ができる。As described above, according to the method shown in FIG. 2, the Po1ySi film 18 can be selectively and easily left in the trench 16, and the trench 16 can be almost completely filled with the SiO2 film 19.
次に、溝内の大部分をＰｏ１ｙＳｉ膜で埋める本発明の
他の実施例を第３図に従って説明する。Ｐ形Ｓ１基板２
ｏ上Ｋ ＳｉＯ２模２１．５ｊ−ｓｅａ膜２２、ＰＳＧ
膜２３を形成した後、ホトリソ技術により溝巾ｍ（例え
ば３μｍ）＋ｎ（例えば１，５μｍ）を有するホトレジ
ストパターン２４を形成する。そして、ホトレジストパ
ターン２４をマスクニジて、Ｐ Ｓ Ｇ膜２３ 、５ｉ
３Ｎａ膜２２，５ｉ０２膜２１及びＳｉ基板２０の表面
から約１．６μｍの深さまでＳｉ・をスパッタエツチン
グし、溝２６．２６を形成する。その後、ＨＮＯ３，Ｈ
Ｆの混合液で溝１６の底面及び側面をエツチングを０．
１μｍエツチングする。そして、６０ ＫｅＶ 、約’
３ Ｘ １ ｏ１３ｉｏｎｓ／ｃａのボロンをイオン注
入し、溝２５．２６の底部にチャネルストッパーとなる
イオン注入領域２７゜２８を形成する（第３図ａ）。Next, another embodiment of the present invention in which most of the trench is filled with a Po1ySi film will be described with reference to FIG. P type S1 board 2
o K SiO2 pattern 21.5j-sea film 22, PSG
After forming the film 23, a photoresist pattern 24 having a groove width m (for example, 3 μm)+n (for example, 1.5 μm) is formed by photolithography. Then, by masking the photoresist pattern 24, the PSG film 23, 5i
Si is sputter-etched from the surfaces of the 3Na film 22, 5i02 film 21 and Si substrate 20 to a depth of approximately 1.6 μm to form grooves 26 and 26. After that, HNO3, H
Etch the bottom and side surfaces of the groove 16 with a mixed solution of F.
Etch 1 μm. and 60 KeV, about'
Boron ions of 3×1 o13 ions/ca are ion-implanted to form an ion-implanted region 27° 28 serving as a channel stopper at the bottom of the groove 25.26 (FIG. 3a).
次に、ホトレジストパターン２４を除去し、加熱酸化法
により溝２５．２６部に厚さ約０．１μｍノ５ｉ０２膜
２９．３０を形成する。そして、ｃｖＤ法、蒸着法、ス
パッタ法等により、溝２６．２６の深さに相当する厚さ
約１゜６μｍのＰｏ１ｙＳｉ膜３１を形成する（第３図
ｂ）。Next, the photoresist pattern 24 is removed, and a 5i02 film 29.30 with a thickness of about 0.1 μm is formed in the groove 25.26 by a thermal oxidation method. Then, a Po1ySi film 31 having a thickness of approximately 1.6 μm, which corresponds to the depth of the grooves 26.26, is formed by CVD, vapor deposition, sputtering, or the like (FIG. 3b).
次に、１０００’Ｃ，６０分の熱処理を施す。このとき
、Ｐｏ１ｙＳｉ膜３１′はＰＳＧ膜２３によりリンが拡
散され、溝２５．２６内のＰｏ１ｙ８ｉ膜３１は拡散さ
れない（第３図ｇ）。Next, heat treatment is performed at 1000'C for 60 minutes. At this time, phosphorus is diffused in the Po1ySi film 31' by the PSG film 23, but not in the Po1y8i film 31 in the grooves 25.26 (FIG. 3g).
次ニ、ＨＮＯｓ 、 ＨＦ 、 ＣａＨｓ Ｃｏｏｌ
ノ混合液でＰｏ１ｙＳｉ膜３１′をエツチング除去する
。この場倫ＰＳＧ膜２３によりリンが拡散されているＰ
ｏ１ｙＳｉ膜３１′は、溝２５．２６内の拡散されてい
ないＰＯ１７Ｓｉ膜３１に比べて１０〜２０倍程度エッ
チングレートが速い。したがって溝２５．２６内のＰｏ
１ｙＳｉ膜３１はほとんどエツチングすることなく、Ｐ
ｏ１ｙＳｉ膜３１′をエツチングすることができ、溝２
５．２６内にＰｏ１ｙＳｊ、膜３１が残存する（第３図
ｄ）。Next, HNOs, HF, CaHs Cool
The Po1ySi film 31' is removed by etching with the mixed solution. P where phosphorus is diffused by the PSG film 23
The etching rate of the o1ySi film 31' is about 10 to 20 times faster than that of the undiffused PO17Si film 31 in the groove 25.26. Therefore Po in groove 25.26
The 1ySi film 31 is hardly etched and P
The o1ySi film 31' can be etched to form the groove 2.
5.26, Po1ySj and film 31 remain (FIG. 3d).
次に、ＨＦ 、 Ｈ２Ｏの混合液あるいは、ＨＦ。Next, a mixture of HF and H2O or HF.
ＮＨ４Ｆの混合液でＰＳＧ膜２３をエツチングする。The PSG film 23 is etched with a mixed solution of NH4F.
その後、９ｏＯ〜１０ｏＯ℃、θ〜１０ＫＦ ／ ｃＡ
の加圧水蒸気中で酸化し、厚さ０．３ ｔｌ ｍの５ｉ
０２膜３２．３３を形成する（第３図ｅ）。Then 9oO~10oO℃, θ~10KF/cA
5i with a thickness of 0.3 tl m.
02 films 32 and 33 are formed (FIG. 3e).
次に、Ｓｉ ３Ｎ ａ膜２２ 、 ＳｉＯ２膜２１及び
ＳｉＯ２膜３２の表面層をエツチングするととによって
、第３図ｆの如＜ Ｓｉ基板２０の表面とほぼ平坦なＳ
ｉＯ２膜３２．３３表面を有する素子間分離領域を形成
することができる。Next, by etching the surface layers of the Si 3 Na film 22, the SiO 2 film 21, and the SiO 2 film 32, as shown in FIG.
An interelement isolation region having the iO2 film 32, 33 surface can be formed.
以上、第３図の方法によれば、溝ｒｊＪの異なる溝２５
．２６内に選択的に、シかも、容易にＰｏ１ｙＳｉ膜３
１を残存させることができ、溝２５．２６の大部分をＰ
ｏ ｌｙ Ｓｉ膜３１で埋めることができる。As described above, according to the method shown in FIG. 3, the grooves 25 with different grooves rjJ
．． Po1ySi film 3 can be selectively and easily deposited within 26
1 can remain, and most of the grooves 25 and 26 can be
It can be filled with an o ly Si film 31.
、 上記第２図及び第３図においては、Ｆ３ｉ、ｓＮ
ａ膜のパターン巾とＰＳＧ膜のパターン巾を同一に形成
しているが、第４図に示す如く、５ｉ５Ｎ４膜４２のパ
ターン＋１−Ｊ ＹよりもＰＳＧ膜のパターン巾Ｚを広
く形成しても良い。すなわち、８１基板４０−」−にＳ
ｉＯ２膜４１ 、５ｉｓＮ＋膜４２．ＰＳＧ膜４３を形
成した後、ホトリソ技術によりパターン巾Ｙを有するホ
トレジストパタ、−７４４を形成する。そして、ホトレ
ジストパターン４４をマスクにし７てＰＳＧ膜４３ 、
５１３Ｎ４膜４２ 、５ｉ０２膜４１及びＳｉ基板４０
を所望の深さだけスパッタエツチングし溝４６を形成す
る。その後、ＨＦとＨ２Ｏの混合液でエツチングすれば
、ＰＳＯ膜４３のエツチングレートが速いだめ、ザイド
エソチングさＪ１パターン中が広がりＺとなる。このよ
うに、ＰＳＧ膜４３のバター／巾ＺをＳｉ、ｓＮ４膜の
パターン巾Ｙよりも広く形成しておけば、ＰＳＧ膜４３
によってＰｏ１ｙＳｉ膜へリン整拡散した際、溝４６内
に形成されているＰｏ１ｙＳｉ膜への拡散を少なくする
ことができる。, In FIGS. 2 and 3 above, F3i, sN
Although the pattern width of the a film and the pattern width of the PSG film are formed to be the same, as shown in FIG. good. That is, S on the 81 board 40-''-
iO2 film 41, 5isN+ film 42. After forming the PSG film 43, a photoresist pattern -744 having a pattern width Y is formed by photolithography. Then, using the photoresist pattern 44 as a mask, the PSG film 43 is removed.
513N4 film 42, 5i02 film 41 and Si substrate 40
A groove 46 is formed by sputter etching to a desired depth. After that, if etching is performed using a mixed solution of HF and H2O, the Zide etching pattern J1 will be expanded to form Z because the etching rate of the PSO film 43 is fast. In this way, if the butter/width Z of the PSG film 43 is formed wider than the pattern width Y of the Si, sN4 film, the PSG film 43
When phosphorus is uniformly diffused into the Po1ySi film, the diffusion into the Po1ySi film formed in the groove 46 can be reduced.
以上のように、本発明によれば、除去したい領域のＰｏ
１ｙＳｉ膜に選択的に不純物の拡散ができ、ｌ−かも、
不純物の拡散されている領域のＰｏ１ｙＳｊ、膜と不純
物の拡散きれていない領域のＰｏ１ｙＳｉ膜のエツチン
グレートの差によって選択的に不純物の拡散されている
領域をエツチング除去することができる。このことによ
り、素子間分離領域となる溝に容易にしかも、素子分離
領域のパターン巾に依存することな（Ｐｏ１ｙＳｉ膜を
残存させることができる。したがって、本発明は、素子
間分離領域のパターン巾が溝巾によって決まるため、溝
巾以上に素子間分離領域が広がることがなく、しかも、
凸部の少ない素子間分離領域が形成でき、高密度な半導
体装置の製造に大きく寄与するものである。As described above, according to the present invention, Po
Impurities can be selectively diffused into the 1ySi film, and l-
The region where the impurity is diffused can be selectively etched away due to the difference in etching rate between the Po1ySj film in the region where the impurity has been diffused and the Po1ySi film in the region where the impurity has not been diffused. This allows the Po1ySi film to be left easily in the groove that becomes the element isolation region without depending on the pattern width of the element isolation region. is determined by the groove width, so the isolation region between elements does not expand beyond the groove width.
It is possible to form an inter-element isolation region with fewer protrusions, which greatly contributes to the manufacture of high-density semiconductor devices.
第１図ａ ％ ｄは従来の素子間分離領域の製造工程図
、第２図ａ −ｈは本発明の一実施例にかかる素子間分
離領域の製造工程図、第３図ｈ −ｆは本発明の他の実
施例にかかる素子間分離領域の製造工程図、第４図は本
発明における他の製造途中における工程図である。
１０ 、２０ 、３０ 、４（）−’−，・Ｓｉ基板、
１２゜２２．４２・・・・・・Ｓｉ３Ｎ４膜、１３，２
３．４３・・・・・・ＰＳＧ膜、１８．３１・・・・・
・Ｐｏ１ｙＳｉ膜、１１，１７゜２１．２９，３０．４
１・・・・・・ＳｉＯ２膜、１５ 、２６ 。
２６．４５・・・・・・溝、１６，２７．２８・・・・
・・不純物層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
（３’／
第２図Figure 1 a% d is a manufacturing process diagram of a conventional element isolation region, Figures 2 a - h are manufacturing process diagrams of an element isolation region according to an embodiment of the present invention, and Figures 3 h - f are the actual manufacturing process diagrams of an element isolation region according to an embodiment of the present invention. FIG. 4 is a process diagram for manufacturing an inter-element isolation region according to another embodiment of the present invention. 10, 20, 30, 4()-'-, Si substrate,
12゜22.42...Si3N4 film, 13,2
3.43...PSG film, 18.31...
・PolySi film, 11,17°21.29,30.4
1...SiO2 film, 15, 26. 26.45...groove, 16,27.28...
...Impurity layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure (3'/ Figure 2
Claims (1)
程と、前記拡散防止膜上に不純物を含む堆積被膜を形成
する工程と、所定の領域の前記堆積被膜及び前記拡散防
止膜をエツチングし、さらに前記半導体基板を所望の深
さまでエツチングし凹部を形成する工程と、前記半導体
基板上に半導体膜を形成する工程と、熱処理を施して前
記半導体膜に前記堆積被膜から不純物を拡散し、拡散領
域を形成する工程と、前記拡散領域の半導体膜を選択的
にエツチングし、前記凹部内に半導体膜を残存させる工
程とを有することを特徴とする半導体装置の製造方法。 （２）ホトレジストパターンをマスクとして凹部を形成
した後、前記凹部底面に半導体基板の導電形と同導電形
を有するイオン注入領域を形成する工程を備えているこ
とを特徴とする特許請求の範囲第１項に記載の半導体装
置の製造方法。 （３）堆積被膜にＰＳＧ膜を用いていることを特徴とす
る特許請求の範囲第１項に記載の半導体装置の製造方法
。 （４）半導体膜に多結晶シリコン膜を用いていることを
特徴とする特許請求の範囲第１項に記載の半導体装置の
製造方法。 （６）拡散領域の半導体膜の選択エツチング液として、
弗化水素酸と硝酸と酢酸の混合液を用いていることを特
徴とする特許請求の範囲第１項に記載の半導体装置の製
造方法。 （６）拡散防止膜にシリコン窒化膜を用いていることを
特徴とする特許請求の範囲第１項に記載の半導体装置の
製造方法。Scope of Claims (11) A step of forming a diffusion prevention film on one principal surface of a semiconductor substrate, a step of forming a deposited film containing impurities on the diffusion prevention film, and a step of forming a deposited film containing an impurity on a predetermined region. A step of etching the diffusion prevention film, further etching the semiconductor substrate to a desired depth to form a recess, a step of forming a semiconductor film on the semiconductor substrate, and a heat treatment to form the deposited film on the semiconductor film. A method for manufacturing a semiconductor device comprising the steps of: diffusing impurities to form a diffusion region; and selectively etching a semiconductor film in the diffusion region to leave the semiconductor film in the recess. (2) A method comprising the step of forming a recess using a photoresist pattern as a mask, and then forming an ion implantation region having the same conductivity type as that of the semiconductor substrate on the bottom surface of the recess. A method for manufacturing a semiconductor device according to claim 1. (3) A method for manufacturing a semiconductor device according to claim 1, characterized in that a PSG film is used as the deposited film. (4) Semiconductor film A method for manufacturing a semiconductor device according to claim 1, characterized in that a polycrystalline silicon film is used in the semiconductor device. (6) As a selective etching solution for the semiconductor film in the diffusion region,
2. The method of manufacturing a semiconductor device according to claim 1, wherein a mixed solution of hydrofluoric acid, nitric acid, and acetic acid is used. (6) The method for manufacturing a semiconductor device according to claim 1, wherein a silicon nitride film is used as the diffusion prevention film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9640182A JPS58213444A (en) | 1982-06-04 | 1982-06-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9640182A JPS58213444A (en) | 1982-06-04 | 1982-06-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58213444A true JPS58213444A (en) | 1983-12-12 |
Family
ID=14163935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9640182A Pending JPS58213444A (en) | 1982-06-04 | 1982-06-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58213444A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63299361A (en) * | 1987-05-29 | 1988-12-06 | Sony Corp | Manufacture of semiconductor device |
| JPH01276641A (en) * | 1988-03-24 | 1989-11-07 | Motorola Inc | Manufacture of semiconductor device |
| CN105514020A (en) * | 2014-10-14 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of groove isolation structure and semiconductor device |
-
1982
- 1982-06-04 JP JP9640182A patent/JPS58213444A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63299361A (en) * | 1987-05-29 | 1988-12-06 | Sony Corp | Manufacture of semiconductor device |
| JPH01276641A (en) * | 1988-03-24 | 1989-11-07 | Motorola Inc | Manufacture of semiconductor device |
| CN105514020A (en) * | 2014-10-14 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of groove isolation structure and semiconductor device |
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