JPH05283404A - Manufacture of element isolation region of semiconductor - Google Patents

Abstract

PURPOSE:To prevent a channel stopper layer under an element isolation film of a semiconductor device from diffusing into an element forming region, and form a mask for ion implantation to form the channel stopper layer in a self alignment manner. CONSTITUTION:When the element isolation region of a semiconductor device is formed, a low stress silicon nitride film 4 is thickly deposited by a plasma CVD method, on a silicon nitride film 3 deposited by an LPCVD method, and an element isolation film 5 is formed by patterning and thermally oxidizing the silicon nitride film. Then channel stopper ions are implanted through the element isolation film 5 by using the thick silicon nitride film as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an element isolation region in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art A conventional element isolation region manufacturing method is shown in FIG.
Will be explained.

FIG. 3 shows a method of manufacturing an element isolation film by the LOCOS method which is usually used. Description will be given below with reference to the drawings. The thermal oxide film 2 is formed on the P-type silicon substrate 21.
2 is formed on the order of 300Å and further LPCVD (Low Pr
essure Chemical Vapor Dep
of the silicon nitride film 23 to 200
About 0Å is deposited. Thermal oxide film 22 and silicon nitride film 33
After patterning, boron (B ⁺ ) was used as a channel stop ion implantation on the entire surface, for example, 30 KeV2 ×
The implantation is performed under the condition of 10 ¹³ / cm ² . (The above is FIG. 3a) Next, the silicon substrate is heated at 1000 ° C. for 12 hours in an oxidizing atmosphere.
A high temperature heat treatment for about 0 minutes is performed to form an element isolation film (so-called field oxide film) 24 of about 5000 Å. (Fig. 3
b)) Next, the silicon nitride film 23 is removed in hot phosphoric acid, and the thermal oxide film 12 is removed with a hydrofluoric acid-based chemical solution. Then, devices such as transistors and PN junction diodes are formed on the exposed silicon surface. (FIG. 3 c)) An N ⁺ P junction is shown as an example. This also corresponds to the source / drain regions of the transistor. As a method, arsenic (As ⁺ ) or phosphorus (P ⁺ ) is ion-implanted on the entire surface of the silicon substrate 21 to obtain 4 × 10 ¹⁵ ions / c.
m ² at 30 KeV, and then 900 ° C.
N ⁺ by heat treatment for about 20 minutes in a nitrogen atmosphere
A P-type junction is formed.

However, in the method described above, the N ⁺ region and the high-concentration P-type region 26 formed by the channel stop ion implantation are formed at the end portion (A portion of FIG. 3D) of the element isolation film 24. However, there is a problem that the contact capacitance increases and the junction capacitance increases. This is because a high temperature heat treatment is introduced after the channel stop ion implantation, so that the high concentration P-type region 26 which is the channel stop layer is inevitably formed in the element isolation film 2.
This is because it diffuses into the outside of 4, that is, into the silicon substrate for device formation.

Therefore, recently, in 1990 IEDM
P. 647-P. As shown by 650, a method has been proposed in which channel stop ion implantation is performed after the element isolation film is formed. This will be described below with reference to FIG. First, a thermal oxide film 12 is formed on the P-type silicon substrate 11 to a thickness of about 300 Å, and a silicon nitride film 13 is further formed by LPCVD.
Accumulate about 000Å. After patterning the thermal oxide film 12 and the silicon nitride film 13, the silicon substrate is subjected to a high temperature heat treatment at 1000 ° C. for about 120 minutes in an oxidizing atmosphere without performing channel stop ion implantation.
The element isolation film 14 of about 000Å is formed. (Fig. 2
a)) Next, the silicon nitride film 13 is removed in hot phosphoric acid, and the thermal oxide film 12 is removed with a hydrofluoric acid-based chemical solution. After that, a resist is applied on the entire surface and exposed and developed to obtain a resist pattern 15. At this time, the end of the resist pattern 15 is formed apart from the end of the element isolation film by a predetermined distance L. Next, using the resist pattern 15 as a mask, boron (B ⁺ ) is used as channel stop ion implantation for accelerating energy of 220 KeV and dose of 2 × 10 ¹³ ions.
Ion implantation is performed under the condition of / cm ² . Then, the implanted ions pass through the element isolation film 14 and are implanted under the element isolation film. (FIG. 2B) Next, the resist pattern 15 is removed. For example N ⁺ P
Arsenic (As ⁺ ) or phosphorus (P ⁺ ) is ion-implanted to form a junction at 4 × 10 ¹⁵ ions / cm 2.
^2. Implanted under the conditions of 30 KeV and then heat treated at 900 ° C. in a nitrogen atmosphere for about 40 minutes to obtain N ⁺ P
As the junction is formed, the channel stop ions are also activated and become the channel stop P-type layer 16.
As is clear from FIG. 2c), the channel stop ion implantation is performed after the high temperature heat treatment for forming the element isolation film 14, and the resist serving as the mask for the channel stop ion implantation. Since the end of the pattern 15 is separated from the end of the element isolation film 14 by the distance L, the N ⁺ region 17 and the P-type layer 16 do not come into contact with each other,
The junction capacitance can also be kept low.

[0006]

However, the above-mentioned method has a problem that misalignment or the like is likely to occur because the place where the channel stop ion implantation is performed is limited by using the photolithography method. If the misalignment is more than the distance L, the N ⁺ region 17 and the P-type layer 16 come into contact with each other and the junction capacitance increases.

Further, the number of steps is increased by 5 steps of resist coating photomask alignment exposure development resist removal, so that there are problems such as an increase in cost and a decrease in yield, so that a technically satisfactory one cannot be obtained.

[0008]

According to the present invention, in forming an element isolation region of a semiconductor device, a low stress silicon nitride film is thickly deposited by a plasma CVD method on a silicon nitride film deposited by an LPCVD method, and then a silicon nitride film is formed. The film is patterned and subjected to high temperature heat treatment in an oxidizing atmosphere to selectively form an element isolation film, and then channel stop ions are implanted through the element isolation film using a thick silicon nitride film as a mask. is there.

[0009]

According to the present invention, after the high temperature heat treatment is performed, the channel stop ion implantation is performed using the thick silicon nitride film as a mask, so that the channel stop diffusion layer can be formed in a self-aligned manner. it can. Therefore, it is possible to solve the problems such as misalignment due to the photolithography method and the cost increase and the yield decrease due to the increase of the steps.

[0010]

FIG. 1 is a process sectional view of a manufacturing method showing an embodiment of the present invention. First, the P-type silicon substrate 1 is heat-treated in an oxidizing atmosphere to form an oxide film 2 of about 300Å. After that, the silicon nitride film 3 is deposited to 1500 Å by the LPCVD method.
Deposit to a degree. Subsequently, a low stress silicon nitride film 4 is deposited to about 8000 Å by the plasma CVD method. The low stress silicon nitride film has a flow rate ratio of silane, ammonia and nitrogen of 140/60/1500 SCC, respectively.
M, the pressure was raised to 6.5 Torr, and the RF power was 2.
If the film is deposited under the condition of 5 W / cm ² and the lowering temperature of about 400 ° C., a silicon-rich silicon nitride film with a stress of about 5 × 10 ⁸ dyne / cm ² can be obtained. In the present invention, since the low stress silicon nitride film is deposited as described above, cracks and defects due to film stress can be prevented even if the film thickness is increased to 8000Å. After that, the oxide film 2 and the silicon nitride films 3 and 4 are left only on the element formation region by the usual photolithography method and etching method. (FIG. 1a) Next, when the silicon substrate is oxidized by heat treatment at 1000 ° C. for about 90 minutes in a wet oxidizing atmosphere, the element isolation film 5 of about 5000 Å is selectively formed on the element isolation region.

[0011] Next, boron serving as a channel stop ions (B ^+), acceleration energy 220 keV, at a dose of ^{2 × 10 13 ions / cm 2} , low stress
Ions are implanted over the entire surface using the silicon nitride film 4 as a mask. At this time, the range of boron (B ⁺ ) is about 5000 Å, and boron (B ⁺ ) is selectively injected only under the element isolation film. In a region where the thick silicon nitride film is present, boron (B ⁺ ) is stopped in the silicon nitride film, so that it is not implanted into the silicon substrate. Further, since the end portion of the element isolation film 5 is partly formed under the silicon nitride film 3 (so-called bird's beak), boron (B ⁺ ) is closer to the element isolation region than the end portion of the element isolation film 5. Are injected at a predetermined distance.
(FIG. 1b) Next, the thick silicon nitride film 4 and the underlying silicon nitride film 3 are removed by hot phosphoric acid, and the oxide film 2 of about 300 Å is removed by a hydrofluoric acid-based solution. After that, a PN junction of a transistor or the like is formed on the exposed silicon substrate. The figure shows a case where N-type impurities are ion-implanted by a normal method to form an N ⁺ P junction. (FIG. 1c) Although the silicon substrate is P type and the channel stop ions are P type in the above description, it goes without saying that the conductivity type thereof may be N type.

[0012]

As described above in detail, according to the manufacturing method of the present invention, the thick silicon nitride film overlaps with the end portion of the element isolation film, and the thick silicon nitride film is used as a mask for self-alignment. Since channel stop ion implantation is performed on the substrate, there is no increase in junction capacitance due to misalignment of photolithography, and no increase in cost or reduction in yield due to an increase in the number of processes.

Furthermore, since the channel stop layer can be formed in a self-aligning manner, it can be used for high integration of semiconductor devices.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a manufacturing method of the present invention.

FIG. 2 is a process sectional view showing a conventional manufacturing method (1)

FIG. 3 is a process cross-sectional view showing a conventional manufacturing method (2)

[Explanation of symbols]

1,11,21 P-type silicon substrate 2,12,22 Oxide film 3,13,23 Silicon nitride film 4 Plasma CVD silicon nitride film 5,14,24 Element isolation oxide film 6,16,26 Dense P-type layer 7, 17,25 N ⁺ area 15 Resist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/76 S 9169-4M

Claims (1)

[Claims] 1. A step of forming a relatively thin oxide film in an element formation region on one main surface of a silicon substrate, and a low pressure chemical vapor deposition (LPC) method on the relatively thin oxide film.
VD) forming a relatively thin silicon nitride film, and forming a low stress thick silicon nitride film on the relatively thin silicon nitride film by plasma enhanced chemical vapor deposition. The step of forming a thick element isolation film by thermally oxidizing the silicon substrate using the silicon nitride film and the low stress thick silicon nitride film as an oxidation-resistant mask, the relatively thin nitride film, and the low stress thick silicon nitride film A method of forming an element isolation region of a semiconductor device, which comprises sequentially performing a step of forming a channel stop region by ion-implanting an impurity of the same conductivity type as that of the silicon substrate through the thick element isolation film as a mask.