JPH07312391A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To simplify a process for forming a twin well on a semiconductor substrate. CONSTITUTION:After p-type impurity ions are implanted into the entire surface of a semiconductor substrate 1, photoresist 4 covering a region for forming p-type well is masked and n-type implurity ions are implanted selectively into the semiconductor substrate 1 of the n-type well formation region and the semiconductor substrate is heat-treated to extend and diffuse the n-type impurity and p-type impurity. After that, with the photo,resist 4 as a mask, the surface of the semiconductor substrate 1 is partially etched to form an alignment mark 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a twin well (Twi
n Well) related technology that is effective when applied to the process of forming.

[0002]

2. Description of the Related Art FIGS. 6 to 10 show an example of a process for forming a twin well composed of an n-type well and a p-type well on a semiconductor substrate.

First, as shown in FIG. 6, a semiconductor substrate 11
Is heat-treated to form a silicon oxide film 12 on its surface, and then a silicon nitride film 13 serving as a mask for forming a well is deposited on the silicon oxide film 12 by a CVD method. In addition,
In the figure, a region indicated by n indicates an n-type well forming region, and a region indicated by p indicates a p-type well forming region. Further, the area indicated by a indicates the area where the alignment mark used for alignment of the photomask is formed.

Next, as shown in FIG. 7, the photoresist 14 is used as a mask to remove the silicon nitride film 13 in the n-type well formation region by etching, and then the n-type well is formed in the semiconductor substrate 11 in the n-type well formation region. Impurities (phosphorus or arsenic)
Is ion-implanted.

After removing the photoresist 14 by etching, the semiconductor substrate 11 is heat treated to form a thick silicon oxide film 15 on the surface of the n-type well forming region, as shown in FIG. By forming the silicon oxide film 15, the n-type well forming region on the surface of the semiconductor substrate 11 and the p-type well forming region are formed.
A step is formed between the well and the mold well formation region. Further, the alignment mark 16 is formed by utilizing this step.

Then, after the silicon nitride film 13 is removed by etching, as shown in FIG. 9, the thick silicon oxide film 15 is used as a mask to p-type impurities (boron) on the semiconductor substrate 11 in the p-type well formation region. Is ion-implanted.

Next, as shown in FIG. 10, the semiconductor substrate 1
The n-type well 17 and the p-type well 18 are formed by heat-treating 1 and extending and diffusing the n-type impurity and the p-type impurity, respectively.

Next, although not shown, the n-type well 17
Element isolation regions are formed in predetermined regions of the p-type well 18 and the p-type well 18 by a selective oxidation method (LOCOS method) or the like. The alignment mark 16 is used for aligning the photomask when forming the element isolation region.

Then, a semiconductor element is formed in the active region surrounded by the element isolation region by a conventional method.

[0010]

According to the study by the present inventor, the twin well forming process has a problem that the number of steps is large.

It is an object of the present invention to provide a technique capable of simplifying the twin well formation process.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

The typical ones of the inventions disclosed in the present application will be outlined below.

The method of forming a twin well according to the present invention is as follows.
First, a semiconductor substrate is heat-treated to form a silicon oxide film on its surface, and then p-type impurities are ion-implanted into the entire surface of the semiconductor substrate through the silicon oxide film, and then a photoresist covering the p-type well formation region is formed. An n-type impurity is selectively ion-implanted into the semiconductor substrate in the n-type well formation region using the mask as a mask, the photoresist is removed, and then the semiconductor substrate is heat-treated to remove the n-type impurity and the p-type impurity. An n-type well and a p-type well are formed by extending and diffusing each.

After selectively implanting n-type impurities into the semiconductor substrate in the n-type well formation region by ion implantation, a part of the surface of the semiconductor substrate is etched by using the photoresist used as a mask for this ion implantation as a mask. Then, the alignment mark is formed by forming a step.

[0016]

According to the above means, the number of steps for forming the twin well can be reduced as compared with the method in which the silicon nitride film is used as the mask for forming the well.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First, as shown in FIG. 1, the semiconductor substrate 1 is heat treated to form a silicon oxide film 2 on its surface,
As shown in FIG. 2, p-type impurities (boron) are ion-implanted into the entire surface of the semiconductor substrate 1 through the silicon oxide film 2. The region indicated by n in FIG. 1 indicates an n-type well forming region, and the region indicated by p indicates a p-type well forming region. Further, the area indicated by a indicates the area where the alignment mark used for alignment of the photomask is formed.

Next, as shown in FIG. 3, the p-type well forming region is covered with a photoresist 4 and the photoresist 4 is removed.
Is used as a mask to selectively ion-implant an n-type impurity (phosphorus or arsenic) into the semiconductor substrate 1 in the n-type well formation region. This n-type impurity is introduced at a position deeper than the p-type impurity.

Next, as shown in FIG. 4, a part of the surface of the semiconductor substrate 1 is etched by using the photoresist 4 as a mask to form a step between the n-type well forming region and the p-type well forming region. Form. The alignment mark 5 is formed by forming the step.

Next, after the photoresist 4 is removed, as shown in FIG. 5, the semiconductor substrate 1 is heat-treated to extend and diffuse each of the n-type impurity and the p-type impurity, thereby n A type well 7 and a p-type well 8 are formed.

Next, although not shown, an element isolation region (field insulating film) is formed in a predetermined region of each of the n-type well 7 and the p-type well 8 by a selective oxidation method (LOCOS method). The alignment mark 6 is
It is used for aligning the photomask when forming this element isolation region.

Thereafter, a semiconductor element is formed in the active region surrounded by the element isolation region by a conventional method.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0025]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the number of steps for forming a twin well can be reduced as compared with the method of using a silicon nitride film as a mask for forming a well.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of forming a twin well according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of forming a twin well according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for forming a twin well according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of forming a twin well according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of forming a twin well according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor substrate showing a conventional method of forming a twin well.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a conventional method of forming a twin well.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a conventional method of forming a twin well.

FIG. 9 is a sectional view of an essential part of a semiconductor substrate, showing a conventional method for forming a twin well.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a conventional method of forming a twin well.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor substrate 2 silicon oxide film 4 photoresist 5 alignment mark 7 n-type well 8 p-type well 11 semiconductor substrate 12 silicon oxide film 13 silicon nitride film 14 photoresist 15 silicon oxide film 16 alignment mark 17 n-type well 18 p-type well

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/027 21/316 M 21/318 M 21/761 H01L 21/30 502 M 21/76 J 27/08 321 N (71) Applicant 000233240 Hitachi Measurement Engineering Co., Ltd. 312 832 Nagakubo, Horiguchi, Hitachinaka City, Ibaraki Prefecture (72) Inventor Yang Reiji 5-20-1, Kamisuimotocho, Kodaira-shi, Tokyo Ultra LSI Engineering Co., Ltd. (72) Inventor Mitsuhiko Yoshida, Nakajima 145, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi Hokkai Semiconductor Co., Ltd. No. 1 Incorporated company Hitachi Ltd. Semiconductor Division (72) Inventor Yasuhide Fujioka 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Hitachi Umi Semiconductor Co., Ltd. (72) Inventor Yoshiyuki Kaneko, 882 Ige, Katsuta, Ibaraki Hitachi Measurement Engineering Co., Ltd. (72) Inventor, Hiroki Soeda, 882 Moe, Katsuta, Ibaraki Hitachi Measurement Engineering Co., Ltd. (72) Inventor Atsushi Ogishima 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device, which comprises the following steps (a) to (c) when forming an n-type well and a p-type well on a main surface of a semiconductor substrate. (a) A step of heat-treating the semiconductor substrate to form a silicon oxide film on the surface thereof, and then ion-implanting p-type impurities into the entire surface of the semiconductor substrate through the silicon oxide film. (b) A step of selectively ion-implanting n-type impurities into the semiconductor substrate in the n-type well forming region using a photoresist as a mask covering the p-type well forming region. (c) A step of forming an n-type well and a p-type well by removing the photoresist and then heat-treating the semiconductor substrate to extend and diffuse each of the n-type impurity and the p-type impurity. 2. After the step (b), an alignment mark is formed by etching a part of the surface of the semiconductor substrate by using the photoresist as a mask to form a step, and the step (c). 2. The semiconductor integrated circuit device according to claim 1, wherein after that, the alignment mark is used for alignment of a photomask to form an element isolation region on each main surface of the n-type well and the p-type well. Manufacturing method.