JPH0358471A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0358471A
JPH0358471A JP1193450A JP19345089A JPH0358471A JP H0358471 A JPH0358471 A JP H0358471A JP 1193450 A JP1193450 A JP 1193450A JP 19345089 A JP19345089 A JP 19345089A JP H0358471 A JPH0358471 A JP H0358471A
Authority
JP
Japan
Prior art keywords
photoresist
region
well
conductivity type
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1193450A
Other languages
Japanese (ja)
Other versions
JP3057692B2 (en
Inventor
Hiroshi Yoshida
宏 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1193450A priority Critical patent/JP3057692B2/en
Publication of JPH0358471A publication Critical patent/JPH0358471A/en
Application granted granted Critical
Publication of JP3057692B2 publication Critical patent/JP3057692B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent impurity from being injected into a well forming region and to improve an element formed in a well in characteristics by a method wherein an active region is covered with a multilayered film which includes an acid-resistant oxide film and a photoresist when a reverse conductivity type channel stopper region is formed. CONSTITUTION:An oxide film 2 is formed on the whole face of a silicon substrate 1, and a P-well 4 is formed using a photoresist 3 as a mask. Then, a nitride film 5 is formed on the whole face, which is etched using a photoresist 6 as a mask to selectively leave the nitride film 5 unremoved as prescribed, and the unremoved nitride film 5 and the photoresist 6 are used as a mask to form an N-type channel stopper region 7 on a field region. Furthermore, a P-type channel stopper 9 is formed in the field region on the P-type well 4 side using a photoresist 8 as a mask. Then, the photoresists 6 and 8 are removed, a field oxide film 10 is formed using the nitride film 5 as a mask, the nitride film 5 is removed, and an N-well 12 is formed using a photoresist 11 as a mask. By this setup, impurity is prevented from being injected into a well forming region and an element formed in a well can be improved in characteristics.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMOS}ランジスタを用いた半導体装置の製造
に好適な製造方法に関する. 〔従来の技術] 従来、MOS}ランジスタを備える半導体装置では、隣
接する素子を互いに電気的に分離するために、厚い酸化
膜で形威されたフィールド領域で活性領域を囲む構造が
用いられている.この構造はフィールド領域の酸化膜の
膜厚を厚くするだけで簡単に素子分離できるため、この
種の半導体装置の高集積化が容易になる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a manufacturing method suitable for manufacturing a semiconductor device using a MOS transistor. [Prior Art] Conventionally, in a semiconductor device including a MOS transistor, a structure is used in which an active region is surrounded by a field region formed by a thick oxide film in order to electrically isolate adjacent elements from each other. .. In this structure, elements can be easily isolated by simply increasing the thickness of the oxide film in the field region, making it easy to achieve high integration of this type of semiconductor device.

第3図(a)乃至(d)は従来のこの種のフィールド領
域の製造方法を工程順に示す図である。
FIGS. 3(a) to 3(d) are diagrams illustrating a conventional manufacturing method of this type of field region in the order of steps.

先ず、第3図(a)のように、半導体基板lに酸化膜2
を形威し、その後フォトレジスト3をマスク材としてボ
ロンをイオン注入し、拡散してPウェル4を形成する. 次いで、第3図(b)のように、フォトレジスト3を除
去した後、全面に窒化膜5を戒長し、別のフォトレジス
ト6を利用した選択エッチングにより、後にトランジス
タを形成する部分に窒化膜5を残す。更に、別のフォト
レジスト8を選択形威し、これをマスクにして素子分離
領域のPウェル4側にボロンをイオン注入し、P型チャ
ネルストッパ領域9を形成する。
First, as shown in FIG. 3(a), an oxide film 2 is formed on a semiconductor substrate l.
Then, using the photoresist 3 as a mask material, boron ions are implanted and diffused to form a P-well 4. Next, as shown in FIG. 3(b), after removing the photoresist 3, a nitride film 5 is formed on the entire surface, and selective etching is performed using another photoresist 6 to form a nitride film on the part where a transistor will be formed later. Membrane 5 is left. Further, another photoresist 8 is selectively applied, and using this as a mask, boron ions are implanted into the P-well 4 side of the element isolation region to form a P-type channel stopper region 9.

次いで、第3図(C)のように、フォトレジスト6,8
を除去した後、フォトレジスト14をマスクにして素子
分離領域内のPウェル4以外の部分にリンをイオン注入
し、N型チャネルストツパ領域7を形成する。
Next, as shown in FIG. 3(C), photoresists 6 and 8 are applied.
After removing phosphorus, phosphorus ions are implanted into a portion of the element isolation region other than the P well 4 using the photoresist 14 as a mask to form an N-type channel stopper region 7.

その後、第3図(d)のように、フォトレジスト14を
除去し、窒化膜5をマスクとして熱酸化を行い、厚さ6
000人程度のフイールF酸化膜10を形成する。その
上で、フォトレジスト11をマスクとしてリンをイオン
注入し、Nウェルl2を形成する。
Thereafter, as shown in FIG. 3(d), the photoresist 14 is removed, thermal oxidation is performed using the nitride film 5 as a mask, and a thickness of 6
000 film F oxide film 10 is formed. Thereafter, phosphorus ions are implanted using the photoresist 11 as a mask to form an N well 12.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の製造方法では、第3図(C)の工程にお
いてN型チャネルストツパ領域7にリンをイオン注入す
る際には、Nウェル12の形成領域上のマスクは窒化膜
5のみとなる。この窒化膜5の膜厚はフィールド酸化膜
形成時のバーズビークでの応力を抑えて拡散層でのリー
クを抑える必要があり、あまり厚くできない。このため
、N型チャネルストツパ領域7へのリンのイオン注入の
際に、活性領域としてのNウェル形成領域にリンが注入
され、後にNウェル12に形成されるMOSトランジス
タ等の素子のサブスレッショルド電圧の制御性を低下さ
せたり、ドレイン耐圧の低下をまねくという問題がある
In the conventional manufacturing method described above, when ion-implanting phosphorus into the N-type channel stopper region 7 in the step shown in FIG. . The thickness of the nitride film 5 cannot be too thick because it is necessary to suppress stress at the bird's beak during formation of the field oxide film and to suppress leakage in the diffusion layer. Therefore, when ion-implanting phosphorus into the N-type channel stopper region 7, phosphorus is implanted into the N-well formation region as an active region, and the subthreshold of elements such as MOS transistors to be formed later in the N-well 12 is reduced. There are problems in that voltage controllability is deteriorated and drain breakdown voltage is reduced.

本発明はウェル形威領域への不純物の注入を防止し、該
ウェルに形威される素子の特性を改善することを可能に
した半導体装置の製造方法を提供することを目的とする
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents impurity injection into a well-forming region and improves the characteristics of an element formed in the well.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の製造方法は、半導体基板に一導電型のウェルを
形成する工程と、少なくとも耐酸化膜とフォトレジスト
とを含む多層膜で前記半導体基板の活性領域を覆う工程
と、前記活性領域の境界部に逆導電型の不純物を注入し
て逆導電型のチャネルストフパ領域を形威する工程と、
この逆導電型のチャネルストツパ領域をフォトレジスト
等の膜で覆った後、前記一導電型のウェルの境界部に一
導電型の不純物を注入して一導電型のチャネルストツバ
領域を形成する工程と、前記耐酸化膜をマスクにして選
択酸化法によりフィールド酸化膜を形成する工程と、前
記逆導電型のチャネルスト・ンパ領域を境界とする領域
に逆導電型の不純物を注入して逆導電型のウェルを形成
する工程とを含んでいる。
The manufacturing method of the present invention includes a step of forming a well of one conductivity type in a semiconductor substrate, a step of covering an active region of the semiconductor substrate with a multilayer film including at least an oxidation-resistant film and a photoresist, and a boundary of the active region. forming a channel stopper region of opposite conductivity type by implanting impurities of opposite conductivity type into the region;
After covering this opposite conductivity type channel stopper region with a film such as a photoresist, impurities of one conductivity type are implanted into the boundary of the one conductivity type well to form a one conductivity type channel stopper region. a step of forming a field oxide film by a selective oxidation method using the oxidation-resistant film as a mask; and a step of implanting an impurity of the opposite conductivity type into a region bounded by the channel striker region of the opposite conductivity type. and forming a conductive type well.

[作用] この製造方法は、活性領域の境界部に逆導電型の不純物
を注入して逆導電型のチャネルストンノ《領域を形成す
るに際し、少なくとも耐酸化膜とフォトレジストとを含
む多層膜で該活性領域を覆うため、該逆導電型の不純物
が活性領域に注入されることが防止され、該活性領域に
形威されるウェルの不純物濃度を好適に制御することが
可能となる. 〔実施例〕 次に、本発明を図面を参照して説明する。
[Function] This manufacturing method uses a multilayer film containing at least an oxidation-resistant film and a photoresist when forming a channel region of the opposite conductivity type by implanting impurities of the opposite conductivity type into the boundary of the active region. Since the active region is covered, the impurity of the opposite conductivity type is prevented from being implanted into the active region, and it becomes possible to suitably control the impurity concentration of the well formed in the active region. [Example] Next, the present invention will be described with reference to the drawings.

第1図(a)乃至(d)は本発明の第1実施例を工程順
に示す断面図である. 先ず、第1図(a)のように、シリコン基板1の全面に
酸化膜2を形威し、かつフォトレジスト3をマスクにし
てボロン等をイオン注入し、Pウェル4を形成する. 次に、第1図(b)のように、全面に窒化膜5を形威し
、かつこれをフォトレジスト6を利用してエッチングし
、後にトランジスタを形成する領域に窒化膜5を残す.
そして、窒化膜5及びフォトレジスト6をマスクにして
フィールド領域全体にリンをイオン注入し、N型チャネ
ルストツパ領域7を形成する。
FIGS. 1(a) to 1(d) are cross-sectional views showing the first embodiment of the present invention in the order of steps. First, as shown in FIG. 1(a), an oxide film 2 is formed on the entire surface of a silicon substrate 1, and boron or the like is ion-implanted using a photoresist 3 as a mask to form a P-well 4. Next, as shown in FIG. 1(b), a nitride film 5 is formed over the entire surface and etched using a photoresist 6, leaving the nitride film 5 in the area where a transistor will be formed later.
Then, using the nitride film 5 and the photoresist 6 as a mask, phosphorus ions are implanted into the entire field region to form an N-type channel stopper region 7.

更に、第1図(C)のように、フォトレジスト8をマス
クとしてフィールド領域のPウェル4側にボロンをイオ
ン注入し、P型チャネルストツパ9を形成する。
Furthermore, as shown in FIG. 1C, boron ions are implanted into the P well 4 side of the field region using the photoresist 8 as a mask to form a P type channel stopper 9.

その後、第1図(d)のように、フォトレジスト6.8
を除去した後、窒化膜5をマスクとして熱酸化をjテい
、6000λ程度の厚さのフィールド酸化膜10を形成
する。そして、窒化膜5を除去し、フォトレジスト11
をマスクとしてリンをイオン注入し、Nウェル12を形
成ずる。
After that, as shown in FIG. 1(d), photoresist 6.8
After removing the nitride film 5, thermal oxidation is performed using the nitride film 5 as a mask to form a field oxide film 10 having a thickness of about 6000λ. Then, the nitride film 5 is removed and the photoresist 11
Using this as a mask, phosphorus ions are implanted to form an N well 12.

この製造方法によれば、N型チャネルストッパ7を形成
する際のリンのイオン注入時には、Nウェル12の形r
Ii.’pM域には窒化膜5とフォトレジスト6の二層
構造膜がマスクとされるため、このNウェル12の形成
領域へのリンの注入が防止でき、後にNウェル12内に
形成されるMOS}ランジスタ等の素子のサブスレッシ
ョルド電圧の制御性を改善する。
According to this manufacturing method, when ion-implanting phosphorus when forming the N-type channel stopper 7, the shape of the N-well 12 is
Ii. Since the two-layer structure film of the nitride film 5 and the photoresist 6 is used as a mask in the 'pM region, it is possible to prevent phosphorus from being implanted into the formation region of the N-well 12. }Improves controllability of subthreshold voltage of elements such as transistors.

第2図(a)及び(b)は本発明の第2実施例の工程一
部を示す断面図である。
FIGS. 2(a) and 2(b) are sectional views showing a part of the process of a second embodiment of the present invention.

先ず、第1実施例と同様の工程によりPウェル4を形成
する。その後、第2図(a)のように、全面に窒化流5
及び酸化膜13を形威し、これらをフォトエッチングし
て、後にトランジスタを形成する部分に窒化膜5及び酸
化膜l3を残す。その上で、フィールド領域全体にリン
をイオン注入してN型チャネルス1・ツバ領域7を形成
ずる。
First, the P well 4 is formed by the same process as in the first embodiment. Then, as shown in Fig. 2(a), nitriding flow 5 is applied to the entire surface.
and the oxide film 13 are shaped and photo-etched to leave the nitride film 5 and the oxide film 13 in the area where a transistor will be formed later. Thereafter, phosphorus ions are implanted into the entire field region to form N-type channels 1 and brim region 7.

次に、第2図(b)のように、、フォトレジスト6を除
去し、新たにフォトレジスト8をマスクとしてフィール
ド領域のPウェル4側にボロンをイオン注入してP型チ
ャネルストッパ9を形成する。
Next, as shown in FIG. 2(b), the photoresist 6 is removed, and using the photoresist 8 as a mask, boron ions are implanted into the P-well 4 side of the field region to form a P-type channel stopper 9. do.

その後、フォトレジスト8及び酸化膜13を除去した後
、第l実施例と同様にフィールド酸化膜形成以降の工程
を行う。
Thereafter, after removing the photoresist 8 and the oxide film 13, the steps after forming the field oxide film are performed in the same manner as in the first embodiment.

この製造方法においても、N型チャネルストッパ7の形
成時には、Nウェルl2の形成領域を窒化膜5,酸化膜
13及びフォトレジスト8で覆っているため、リンが注
入されることはない。
Also in this manufacturing method, when forming the N-type channel stopper 7, the formation region of the N-well 12 is covered with the nitride film 5, the oxide film 13, and the photoresist 8, so that phosphorus is not implanted.

なお、本発明は前記各実施例と不純物の導電型が逆の場
合にも同様に適用できる。
Note that the present invention can be similarly applied to cases where the conductivity type of the impurity is opposite to that of each of the above embodiments.

〔発明の効果] 以上説明したように本発明は、逆導電型のチャネルスト
ッパ領域を形成する際に、耐酸化膜とフォトレジストと
を含む多層膜で該活性領域を覆うので、該逆導電型の不
純物が活性領域に注入されることが防止でき、該活性領
域に形威されるウ工ルの不純物濃度を好適に制御し、こ
の活性領域に形威されるMOSトランジスタ等の素子の
ドレイン耐圧の低下を防止し、かつスレッショルド電圧
の制御性を改善した半導体装置を製造することができる
効果がある.
[Effects of the Invention] As explained above, the present invention covers the active region with a multilayer film including an oxidation-resistant film and a photoresist when forming a channel stopper region of the opposite conductivity type. It is possible to prevent impurities from being implanted into the active region, to appropriately control the impurity concentration of the oxide formed in the active region, and to improve the drain breakdown voltage of elements such as MOS transistors formed in the active region. This has the effect of making it possible to manufacture a semiconductor device that prevents a decrease in voltage and improves the controllability of the threshold voltage.

【図面の簡単な説明】[Brief explanation of drawings]

第l図(a)乃至(d)は本発明の第1実施例を製造工
程順に示す断面図、第2図(a)及び(b)は本発明の
第2実施例の工程一部を示す断面図、第3図(a)乃至
(d)は従来の製造方法を工程順に示す断面図である。 1・・・半導体基板、2・・・酸化膜、3・・・フォト
レジスト、4・・・Pウェル、5・・・窒化膜、6・・
・フォトレジスト、7・・・N型チャネルストッパ領域
、8・・・フォトレジスト、9・・・P型チャネルスト
ンバ領域、10・・・フィールド酸化膜、11・・・フ
ォトレジスト、l2・・・Nウェル、13・・・酸化膜
、14・・・フォトレジスト. 第 1 図
Figures 1 (a) to (d) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and Figures 2 (a) and (b) show a part of the process of the second embodiment of the present invention. 3(a) to 3(d) are cross-sectional views showing a conventional manufacturing method in the order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, 3... Photoresist, 4... P well, 5... Nitride film, 6...
- Photoresist, 7... N-type channel stopper region, 8... Photoresist, 9... P-type channel stopper region, 10... Field oxide film, 11... Photoresist, l2...・N well, 13... Oxide film, 14... Photoresist. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板に一導電型のウェルを形成する工程と、
少なくとも耐酸化膜とフォトレジストとを含む多層膜で
前記半導体基板の活性領域を覆う工程と、前記活性領域
の境界部に逆導電型の不純物を注入して逆導電型のチャ
ネルストッパ領域を形成する工程と、この逆導電型のチ
ャネルストッパ領域をフォトレジスト等の膜で覆った後
、前記一導電型のウェルの境界部に一導電型の不純物を
注入して一導電型のチャネルストッパ領域を形成する工
程と、前記耐酸化膜をマスクにして選択酸化法によりフ
ィールド酸化膜を形成する工程と、前記逆導電型のチャ
ネルストッパ領域を境界とする領域に逆導電型の不純物
を注入して逆導電型のウェルを形成する工程とを含むこ
とを特徴とする半導体装置の製造方法。
1. Forming a well of one conductivity type in a semiconductor substrate;
covering the active region of the semiconductor substrate with a multilayer film including at least an oxidation-resistant film and a photoresist; and forming a channel stopper region of the opposite conductivity type by implanting impurities of the opposite conductivity type into the boundary of the active region. After covering this opposite conductivity type channel stopper region with a film such as photoresist, impurities of one conductivity type are implanted into the boundary of the one conductivity type well to form a one conductivity type channel stopper region. forming a field oxide film by selective oxidation using the oxidation-resistant film as a mask; and implanting impurities of opposite conductivity type into a region bounded by the channel stopper region of reverse conductivity type to form a field oxide film of opposite conductivity type. 1. A method of manufacturing a semiconductor device, comprising the step of forming a mold well.
JP1193450A 1989-07-26 1989-07-26 Method for manufacturing semiconductor device Expired - Lifetime JP3057692B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1193450A JP3057692B2 (en) 1989-07-26 1989-07-26 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1193450A JP3057692B2 (en) 1989-07-26 1989-07-26 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0358471A true JPH0358471A (en) 1991-03-13
JP3057692B2 JP3057692B2 (en) 2000-07-04

Family

ID=16308199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1193450A Expired - Lifetime JP3057692B2 (en) 1989-07-26 1989-07-26 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3057692B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05110006A (en) * 1991-10-18 1993-04-30 Sanyo Electric Co Ltd Manufacture of semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05110006A (en) * 1991-10-18 1993-04-30 Sanyo Electric Co Ltd Manufacture of semiconductor integrated circuit

Also Published As

Publication number Publication date
JP3057692B2 (en) 2000-07-04

Similar Documents

Publication Publication Date Title
US4488348A (en) Method for making a self-aligned vertically stacked gate MOS device
JPH08274268A (en) Manufacture of cmos semiconductor device
US5994190A (en) Semiconductor device with impurity layer as channel stopper immediately under silicon oxide film
JPH02264464A (en) Manufacture of semiconductor device
JPH1065019A (en) Manufacturing method of cmos device
JP2775765B2 (en) Semiconductor device manufacturing method
JPH0358471A (en) Manufacture of semiconductor device
JPH07321212A (en) Forming method for channel stop diffusion layer
JP2658027B2 (en) Method for manufacturing semiconductor device
KR100379534B1 (en) Method for Fabrication Semiconductor Device
JP3188132B2 (en) Method for manufacturing semiconductor device
JPH0479336A (en) Production of semiconductor device
JPH0349236A (en) Manufacture of mos transistor
JPH01223741A (en) Semiconductor device and manufacture thereof
KR100198673B1 (en) Semiconductor integrated circuit device
JPH0214788B2 (en)
JPH0766400A (en) Semiconductor and its manufacture
JPH09167832A (en) Manufacture of semiconductor device
JPS63144543A (en) Formation of semiconductor interelement isolation region
JPH036844A (en) Manufacture of semiconductor integrated circuit
JPH04242934A (en) Manufacture of semiconductor device
KR19990086918A (en) Manufacturing method of semiconductor device
JPH06349942A (en) Manufacture of semiconductor device
JPS60142557A (en) Manufacture of semiconductor device with high withstand voltage
JPH02260452A (en) Semiconductor device