JPH02260452A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a leakage current from flowing to a gray zone under a gate electrode without expanding a formation region of a transistor element by a method wherein a conductor layer is formed between an isolation insulating film and the gate electrode. CONSTITUTION:An isolation insulating film 10a is formed on a boundary between an n-channel formation region 1 and a p-channel formation region 2 which are situated on the main surface of a semiconductor substrate 8. A gate electrode 5 of a transistor is formed on the isolation insulating film 10a. A conductor layer 6 which restrains an inversion layer from being formed at a boundary part 9 between the n-channel transistor formation region 1 and the p-channel transistor formation region 2 is formed between the gate electrode 5 and the isolation insulating film 10a. Since a voltage not exceeding a threshold voltage in the gray zone 9 is applied to the conductor layer 16, the inversion layer is not formed in the gray zone under the gate electrode 5 even when any voltage is applied to the gate electrode 5. Thereby, a leakage current cannot flow in the semiconductor substrate 8 under the gate electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device including both an n-channel transistor and a p-channel transistor.

[Prior art] Figure 7 shows a twin-tab type CMOS l-transistor n.
FIG. 3 is a plan view of the vicinity of a well. As shown in FIG. 7, a p-well 2 a s 2 b s2c is formed around the n-well 1. A source region 3 and a drain region 4 are formed on the n-well 1. A gate electrode 5 is formed between the source region 3 and the drain region 4. An aluminum wiring layer 6C is electrically connected to the source region 3. An aluminum wiring layer 6 is provided in the drain region 4.
b is electrically connected. An aluminum wiring layer 6a is electrically connected to the gate electrode 5. An n-type diffusion layer 7 is formed on the n-well 1 so as to surround the source region 3 and drain region 4 . The role of the diffusion layer 7 will be explained later. An aluminum wiring layer 6d is electrically connected to the diffusion layer 7.

By applying a voltage to the aluminum wiring layer 6d,
The n-well 1 is set at a predetermined voltage.

FIG. 8 is a cross-sectional view of the n-well 1 shown in FIG. 7 taken along the line indicated by the arrow ■. As shown in FIG. 8, an n-well 1 and an n-well 2a are formed in a p-type silicon substrate 8.

At the boundary between the n-well 1 and the n-well 2a, there is a region 9 (hereinafter referred to as a gray zone) with a low impurity concentration. This is n
Part of the n-type impurity diffused into the silicon substrate 8 to form the well 1 invades the n-well 2a, and part of the p-type impurity diffused into the silicon substrate 8 to form the n-well 2a. This is because the n-type impurity and the p-type impurity intersect at the boundary between the n-well 1 and the n-well 2, and as a result, the impurity concentration becomes low. Although not shown in Figure 8, n-well 1 and n-well
Boundary of well 26 and n well 1 and p'7 x le 2
There is also a gray zone at the boundary of c.

A diffusion layer 7 is formed in the n-well 1 . 0 well 1
A field oxide film 10a is formed on the boundary between the n-well 2a and the n-well 2a.
is formed. Field oxide films 10b and 10c are formed on n-well 1 so as to sandwich diffusion layer 7 therebetween. Field oxide @ 10 A gate oxide film 11 is formed between a and 10b, and a field oxide film 10
Silicon oxide fi12 is formed between b and 10c.

A gate electrode 5 is formed from above gate oxide film 11 to above field oxide film 10a.

A PSGM 13 is formed on the gate electrode 5, on the field oxide film 10a, on the field oxide film 10b, on the field oxide film 10c, and on the silicon oxide film 12. On the PSG film 13, aluminum wiring layers 6a s 6 d are formed. The aluminum wiring layer 6a and the gate electrode 5 are electrically connected by aluminum filled in a contact hole provided in the PSG film 13. The aluminum wiring layer 6d and the diffusion layer 7 are electrically connected by aluminum filled in a contact hole provided in the PSG film 13. In addition, in FIG. 8, 0MO5 is applied along the gate electrode 5)
Since this is a cross-sectional view of the transistor cut away, the source region 3 and drain region 4 do not appear in FIG.

Here, the role of the diffusion layer 7 will be explained. As explained earlier, there is a gray zone 9 where the impurity concentration is low at the boundary between the n-well 1 and the n-well 2as 2bs 2C. In gray zone 9, the impurity concentration is low, so the threshold voltage is lowered. Therefore, when voltage is applied to the gate electrode 5 and the aluminum wiring layers 6c and 6b, the gray zone 9
There is a risk that an inversion layer may be formed. This causes a leakage current, resulting in an unfavorable state in terms of the characteristics of the CMOS transistor.

Therefore, to prevent this, as shown in Figure 7, the n-well r
on top of the n, surrounding the source region 3 and drain region 4.
A mold diffusion layer 7 is formed. As a result, the impurity concentration in the portions of the n-well 1 near the p-wells 2 a and 2 bs 2 C is increased, and a leakage current is generated to be LL%.

[affil to be solved by the invention However, since the diffusion layer 7 is formed by implanting ions into the silicon substrate 8 using the gate electrode 5 as a mask and diffusing them, the diffusion layer 7 is formed by implanting ions into the silicon substrate 8 using the gate electrode 5 as a mask and diffusing them. No diffusion layer 7 is formed underneath. Therefore, as shown in FIG. 8, when an inversion layer is formed in the gray zone 9 under the gate electrode 5 due to the voltage applied to the gate electrode 5, a current flows through the channel formed under the gate oxide l1ill. flows through this inversion layer, and as a result, this current flows into the n-well 2a.

In order to prevent this, it is conceivable to form the diffusion layer 7 so as to also surround the gate electrode 5, but since only one transistor element is formed inside the diffusion layer 7, according to this method, one transistor element is formed inside the diffusion layer 7. This increases the area in which transistor elements are formed, which goes against the demand for miniaturization of CMOS transistors.

Therefore, the present invention has been made to solve such conventional problems, and its purpose is to prevent leakage current from flowing into the gray zone under the gate electrode without enlarging the formation area of the transistor element. The purpose is to provide equipment.

[Means for Solving the Problems] The present invention provides an isolation insulating film that insulates and isolates inner regions on the boundary between an n-channel forming region and a p-channel forming region on the main surface of a semiconductor substrate, and The present invention relates to a semiconductor device in which a gate electrode of a transistor is formed on an insulating film.

In such a semiconductor device, the present invention provides a conductor layer between the gate electrode and the isolation insulating film to prevent the formation of an inversion layer at the boundary between the n-channel transistor formation regions. It is characterized by

[Function] By providing a conductor layer between the isolation insulating film and the gate electrode, the present invention replaces the gate electrode with the conductor layer as the electrode that affects the formation of an inversion layer in the gray zone below the gate electrode. Since a voltage that does not exceed the threshold voltage of the gray zone is applied to this conductor layer, no inversion layer is formed in the gray zone below the gate electrode no matter what voltage is applied to the gate electrode.

[Embodiment] FIG. 1 is a plan view showing an embodiment of the present invention. The difference from the conventional example shown in FIG. 7 is that a first polycrystalline silicon film 16 is formed under the gate electrode 5, and the first polycrystalline silicon film 16 and the diffusion layer 7 are connected to aluminum wiring layers 6e, 6f. The electrical connection was made using

FIG. 2 is a cross-sectional view of the n-well 1 shown in FIG. 1 taken along the line indicated by the arrow . As shown in FIG. 2, the first polycrystalline silicon film 16 is formed between the field oxide film 10a and the gate electrode 5. As shown in FIG.

The manufacturing process of one embodiment of this invention will be described below from Figure 3A to Figure 3.
This will be explained in order using three figures.

First, as shown in FIG. 3A, a silicon oxide film 17, a silicon nitride film 18, and a resist 19 are sequentially laminated on the main surface of a p-type silicon substrate 8. A predetermined patterning process is applied to the resist 19, and the silicon nitride film 18 is etched using the resist 19 as a mask. Furthermore, using the resist 19 as a mask, p-type impurities are added into the silicon substrate 8.
For example, boron ions are implanted.

Next, as shown in FIG. 3B, the resist 19 is removed and the LO
A field oxide film 20 is formed on the silicon substrate 8 using the CO3 method. After removing the silicon nitride film 18, an n-type impurity such as phosphorus is ion-implanted into the silicon substrate 8 using the field oxide film 20 as a mask.

Next, as shown in FIG. 3C, by thermally diffusing the boron and phosphorus implanted into the silicon substrate 8, the n-well 1
A p-well 2a is formed. At this time, a gray zone 9 is also formed.

Next, as shown in FIG. 3D, silicon oxide film 17 and field oxide film 20 are removed from silicon substrate 8 to expose the main surface of silicon substrate 8. A silicon oxide film 21 is then formed on the main surface of silicon substrate 8 by subjecting silicon substrate 8 to heat treatment. Furthermore, silicon oxide film 2
1, a silicon nitride film 22 and a resist are laminated thereon. This resist is subjected to predetermined patterning, and the silicon nitride 22 is removed using this resist as a mask.

This resist is then removed.

Next, as shown in FIG. 3E, a field oxide film 1° as 10b is formed on the silicon substrate 8 using the Locos method.
Form 10c. Then, silicon nitride film 22 and silicon oxide film 21 are removed from the main surface of silicon substrate 8.

Next, as shown in FIG. 3F, the field oxide film 10a,
A first polycrystalline silicon film 16 is formed on the surface of 10bs 10c and the exposed main surface of silicon substrate 8 using the CVD method. Next, the first polycrystalline silicon film 16
A resist is applied on top of the resist, and a predetermined patterning process is applied to this resist.

Then, using this resist as a mask, the first polycrystalline silicon film 16 is etched, leaving only the first polycrystalline silicon film 16 on the field oxide film 10a on the n-well 1. Next, thermal oxidation is performed to form silicon oxide films 11, 12, and 17 on the surface of first polycrystalline silicon film 16 and the exposed main surface of silicon substrate 8.

Silicon oxide film 11 becomes a gate oxide film.

Next, as shown in FIG. 3G, a field oxide film 10 a is formed.
s 10 b s t Q c, silicon oxide film 1
7. A second polycrystalline silicon fi5 is formed on 12 and on the gate oxide film 11 using the CVD method, and is patterned in a predetermined manner to form a gate electrode.

Next, as shown in FIG. 3H, using the resist formed on the gate electrode 5 and the silicon oxide film 12 as a mask, a p-type impurity such as boron, which is used to form the source region 3 and the drain region 4, is applied to the silicon substrate 8. Ions are implanted into the main surface.

Next, as shown in FIG. 3I, the resist 14 formed on the silicon oxide film 12 is removed, and a resist is then formed on the source region 3 and drain region 4. Note that since the source region 3 and the drain region 4 do not appear in FIG. 3I, the state in which the resist is applied on the source region 3 and the drain region 4-1 also does not appear. Then, using the resist formed on the source region 3 and drain region 4 and the gate electrode 5 as masks, n-type impurities such as arsenic used for forming the C1 diffusion layer 7 are ion-implanted into the silicon substrate 8.

Next, as shown in FIG. 3J, the silicon substrate 8 is subjected to heat treatment to diffuse the ions implanted into the silicon substrate 8 to form the source region 3, drain region 4, and diffusion layer 7. Note that the source region 3 and drain region 4 do not appear in FIG. 31. Next, PSGfi 13 is deposited over the entire main surface of silicon substrate 8 using the CVD method. Then, contact holes are formed on the source region 3, the drain region 4, the gate electrode 5, the diffusion layer 7, and the first polycrystalline silicon film 16, and the aluminum wiring I3 is formed on the contact holes.
I layers 6a, 6b, 6c, 6d, 6e, and 6f are formed.

In addition, in FIG. 3J, aluminum wiring layers 6b, 6c, 6
e and 6f do not appear.

The above steps complete the manufacturing process of one embodiment of the present invention. Note that the cross section shown in FIG. 3J does not show that the diffusion layer 7 and the first polycrystalline silicon film 16 are electrically connected by the aluminum wiring layers 6e and 6f. Therefore, this state is shown in FIG. FIG. 4 is a cross-sectional view of the n-well 1 shown in FIG. 1 taken along the line indicated by the arrow ■.

As shown in FIGS. 1 and 2, according to this embodiment, by providing the first polycrystalline silicon film 16 between the field oxide film 10a and the gate electrode 5, The gate electrode 5, which affects the formation of the inversion layer in the gray zone 9, was replaced with the first polycrystalline silicon film 16.

First polycrystalline silicon H! 16 is electrically connected to the diffusion layer 7, the n-well 1 and the first polycrystalline silicon film 16 are at the same potential. Therefore, no inversion layer is formed in the gray zone 9 below the gate electrode 5.

In this embodiment, the first polycrystalline silicon film 16 is formed on the field oxide film 10a on the n-well 1, but the invention is not limited to this, and as shown in FIG. Lowell 1 and Lowell 2 as shown
The first polycrystalline silicon film 16 may be formed on the field oxide film 10a so as to straddle the boundary of the field oxide film 10a.

In this example, a CM with n wells and n rows is used.
O5) Although the transistor has been described, the present invention is not limited thereto, and may be a CMOS transistor having only either an n-well or a row well.

Further, in this embodiment, an MO3m field effect transistor has been described, but the present invention is not limited to this, and other field effect transistors may be used.

Other embodiments of the invention will be described below.

FIG. 6 is a plan view of the vicinity of the n-well 1 of a CMOS transistor according to another embodiment of the present invention.

In this embodiment, first polycrystalline silicon film 16 and diffusion layer 7 are not electrically connected. Instead, by applying a voltage to the aluminum wiring layer 6g electrically connected to the first polycrystalline silicon film 16 such that an inversion layer is not formed in the gray zone under the gate electrode 5, the present invention We are trying to achieve this effect.

[Effect] According to the present invention, by providing a conductor layer between the isolation insulating film and the gate electrode, the electrode that affects the formation of an inversion layer in the gray zone under the gate electrode can be transferred from the gate electrode to the conductor layer. I changed it.

Since a voltage that does not exceed the threshold voltage of the gray zone is applied to this conductor layer, no inversion layer is formed in the gray zone below the gate electrode no matter what voltage is applied to the gate electrode. Therefore, even if a diffusion layer serving as a channel stopper is not formed under the gate electrode, leakage current will not flow into the semiconductor substrate under the gate electrode.

Furthermore, this eliminates the need to form a diffusion layer serving as a channel stopper so as to also surround the gate electrode, thereby eliminating the need to enlarge the transistor formation region. Therefore, according to the present invention, the demand for miniaturization of CMOS transistors can also be satisfied.

The present invention is particularly effective in semiconductor devices used at high voltages of 10 volts or more, such as nonvolatile memory devices having floating gates.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the vicinity of an n-well in an embodiment of the present invention. FIG. 2 is a cross-sectional view of the n-well shown in FIG. 1 taken along the line indicated by the arrow ■. Third
Figures 8 to 3J are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. FIG. 4 is a cross-sectional view of the n-well shown in FIG. 1 taken along the line indicated by the arrow ■. FIG. 5 is a sectional view showing a modification of one embodiment of the present invention. FIG. 6 is a plan view showing the vicinity of the n-well of another embodiment of the present invention. FIG. 7 is a plan view of the vicinity of the n-well of a conventional twin-tab type CMO3) transistor. FIG. 8 is a cross-sectional view of the n-well shown in FIG. 7 taken along the line indicated by the arrow ■. As shown in the figure, 1 is an n-well, 2a, 2b, and 2C are n-wells, 5 is a gate electrode, 8 is a silicon substrate, 10a is a field oxide film, and 16 is a first polycrystalline silicon film.

Claims (1)

[Claims] An isolation insulating film is formed on the main surface of the semiconductor substrate on the boundary between the n-channel transistor formation region and the p-channel transistor formation region to insulate and isolate both regions, and a gate electrode of the transistor is formed on the isolation insulating film. In the semiconductor device, a conductor layer is provided between the gate electrode and the isolation insulating film to prevent formation of an inversion layer at a boundary between the n-channel transistor formation region and the p-channel transistor formation region. A semiconductor device characterized by: