JPS63144543A - Formation of semiconductor interelement isolation region - Google Patents

Abstract

PURPOSE:To prevent an impurity from intruding into an element region due to lateral diffusion, to shorten a channel width and to contrive an increase in density by a method wherein impurity introduced regions of the same conductivity type as that of an Si substrate are previously ready-separated by a constant distance from the ends of a mask. CONSTITUTION:A three-layer film consisting of an SiO2 film 2, an Si3N4 film 3 and an SiO2 film 4 is formed on a P-type Si substrate 1. The three-layer film is selectively etched after a photo resist film 5 is formed and part of the three-layer film is left on a region, where the formation of an element is expected, of the Si substrate 1. Then, an Si oxide film 6 is adhered on the whole surface. Then, the whole surface is etched back to form a spacer 7 on the sidewall of a mask and moreover, B (boron ions) 8 is ion-implanted to form P-type impurity implanted regions 9 on both sides of the spacer 7. The Si oxide film 4 on the mask and the oxide film of the spacer 7 are etched away, a selectively oxidation is performed using the Si nitride film 3 as a mask and a thick field oxide film 10 is formed on a region not being coated with the mask. Moreover, a P-type impurity diffused region 11 is formed right under the oxide film 10. After that, the Si nitride film 3 and the oxide film 2 are removed and when a normal production process is executed, a desired N-channel MOS transistor can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming insulating isolation regions between elements formed on a semiconductor substrate, and particularly relates to a method for forming insulating isolation regions between elements formed on a semiconductor substrate. The present invention relates to a method for forming a separation region.

[Conventional technology]

Today's semiconductor devices are often manufactured with a LOCO8 structure, in which semiconductor elements are provided within island-like regions surrounded by thick field oxide films that are selectively patterned on a silicon substrate. Each semiconductor element is insulated and isolated by this thick oxide film. At this time, the thick field oxide film is formed so as to be partially buried inside the silicon substrate, so there is parasitic MO8 directly under it.
) transistors are easily formed.

Therefore, in order to prevent league current between elements caused by the four parasitic MO8) transistors, an impurity region of the same conductivity type as the substrate is usually formed immediately below and adjacent to this thick feed oxide film. Ru. For example, today,
In an integrated circuit device having an N-channel type MO8) transistor as a component, which is the most widely used transistor, boron (B) is usually introduced into the p-type substrate directly under the field oxide film. Further, as is already known, this thick field oxide film is formed by covering the element formation region with an oxidation-resistant film (for example, a silicon nitride film) and selectively oxidizing only the insulating region.

[Problem that the invention seeks to solve]

Typically, boron (B) is introduced into the substrate by ion implantation prior to the formation of a field oxide film. Field oxide films are generally formed by a thermal oxidation method at about 1000°C, but at this time, the introduced boron (B) diffuses into the substrate and at the same time spreads over the silicon nitride film of the mask used in the oxidation process. It also spreads laterally to the bottom.

In recent years, integrated circuits have become increasingly dense, and element miniaturization technology has been highly praised, and has become an essential condition, but especially when the element to be formed is a transistor (MOS), it is necessary to shorten the channel length. At the same time, there is a need to narrow the channel width. However, using conventional techniques, for example, the channel width of an N-channel MOS transistor element can be narrowed! ! - If you try to increase the channel width, as mentioned above, lateral diffusion of boron will occur, making it extremely difficult to narrow the channel width. That is,
If a fine narrow channel transistor with a channel width of about 2 μm or less is made using conventional technology, the threshold voltage of the MOS transistor element will increase significantly. transistor?
It is extremely difficult to imitate.

In view of the above circumstances, an object of the present invention is to provide a method for forming a semiconductor element isolation region that can effectively suppress the lateral diffusion effect of an impurity region formed directly under a thick field oxide film to the lower part of a thermal oxidation mask. It is to be.

[Failure to solve the problem]

According to the present invention, the method for forming the ¥-hypomorphic separation region is as follows:
a step of forming an oxidation-resistant mask on a semiconductor substrate; a step of incorrectly forming a mask for implanted ions, forming a material film on the top and side surfaces of the oxidation-resistant mask to block transmission of implanted ions; and a mask for the implanted ions. The method includes a step of removing the semiconductor group from above the film, and a thermal oxidation step of performing selective oxidation (using the oxidation-resistant mask).

That is, according to the present invention, the implantation is performed at a distance from the region where the oxidation-resistant mask is to be formed. Therefore, even when a thermal oxidation process is performed, the oxide is not laterally diffused to the bottom of the mask, and the channel width can be reduced.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

Figures 1 (a) to (f) show a working example of the present invention 8J.
@This is the introduction. This example is an N-channel type M with a Locos structure.
Although the case where the present invention is applied to the manufacture of an OS transistor is shown, the case where it is applied to a P-channel type MOS transistor can be explained in exactly the same manner. That is, according to this embodiment, a P-type silicon substrate l is first prepared as shown in FIG.
2. A three-layer film consisting of a silicon nitride film (SisN4) 32 and a silicon oxide film (SiOz) 4 is formed. Here, the lower silicon oxide film 2 is formed to a thickness of 200 to 500 AO to relieve stress during selective oxidation.
The intermediate silicon nitride film 3 serves as a mask in the selective oxidation step and is formed to have a thickness of about 100.0 to 2000×. Furthermore, the upper layer of silicon oxide @4 is a base material for forming spacers on the side walls of the mask, and has a thickness of 30
It is formed to have a film thickness of about 00 to 5oooX. The above three-layer film is a normal photo ring 2 using a photoresist film 5.
A part of the selective etching is shown in Figure 1 (
As shown in the figure, a mask is left on the silicon substrate where the ICI element is to be formed as a mask for selective oxidation. Then, as shown in FIG. 1(C), a silicon oxide film 6 is deposited on the entire surface.

The appropriate thickness of this oxide film 6 is approximately 3,000 to 50,000 mm. Next, the entire surface is etched back with gold to form spacers 7t on the side walls of the mask, and further boron (B) 8 is formed on both sides of the spacers 7. If the oxide group of the silicon oxide film 4 and spacer 7 on the mask is etched away and selective oxidation is performed using the silicon nitride film 3 as a mask, a thick field oxide film lO is formed in the area not covered by the mask. A P-type impurity diffusion region 11 is formed directly below. According to this embodiment, boron ions 8 are implanted onto the silicon substrate 1 away from the silicon nitride film 3 due to the presence of the spacer 7, so even if lateral diffusion is performed by the selective oxidation process, the silicon nitride mask 3 The P-type impurity diffusion region 11 is not formed to extend below. In this embodiment, the ion implantation was performed after the spacer 7 was formed, but the ion implantation may be performed immediately after the silicon oxide film 6t- is formed as shown in FIG. 1 (0).

This can be easily carried out by appropriately selecting the implantation energy and the film thickness of the group 6 oxide. Thereafter, the silicon nitride film 3 and the oxidation film 3 are removed and a normal manufacturing process is carried out to obtain a desired N-channel MO resistor.

It is also possible to form a bipolar transistor in this region where the element is to be formed. Further, in some cases, an ordinary photoresist may be used in place of the silicon oxide IA6; that is, any semiconductor material can be used as long as it has an over-blocking ability against implanted ions.

〔Effect of the invention〕

As explained in detail above, according to the present invention, in forming an inter-element insulating region by selective oxidation, the region into which the 11L type impurity is introduced is separated from the silicon substrate by a certain distance from the edge of the mask in advance. As a result, it is possible to prevent impurities from entering the device region due to lateral diffusion of impurities, making it possible to reduce the channel width of MOS transistor elements and greatly contributing to the increase in density of semiconductor integrated circuit devices. I can do that.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(f) are process flow diagrams showing one embodiment of the present invention. 1... P-type silicon substrate, 2... silicon oxide film, 3... silicon nitride film, 4...
... silicon oxide film, 5 ... photoresist film, 6 ... silicon oxide film, 7 ... spacer, 8 ... boron ion, 9.・・・・・・
P-type impurity implantation region, 10°°°°°° thick field oxide film, 11...P-type impurity diffusion region. Agent: Susumu Uchihara, -l-, (
(b) 6-thorn bamboo 1 diagram

Claims (1)

[Claims] a step of forming an oxidation-resistant mask on a semiconductor substrate; a step of forming a mask film for implanted ions, forming a material film on the top and side surfaces of the oxidation-resistant mask to block transmission of implanted ions; and a mask for the implanted ions. A step of ion-implanting impurities of the same conductivity type as the substrate into the semiconductor substrate surface from above a film, a step of removing a mask film for the implanted ions, and a thermal oxidation step of performing selective oxidation using the oxidation-resistant mask. A method for forming an isolation region between semiconductor elements, the method comprising: