JPH05175441A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate the step differences on the surfaces formed on respective wells by omitting the formation of the thick oxide films in the forming step of the first and second wells. CONSTITUTION:Boron ions 22 are implanted into a well forming region on the main surface of a semiconductor substrate 21, and a P-type impurity layer 23 is formed. A part corresponding to a region, which is to become a P-type well, on the layer 23 is covered with a first resist pattern 24. At the same time, a second resist pattern 25 is formed. With the patterns 24 and 25 as masks, phosphorus ions 26 are implanted, and an N-type impurity layer 27 is formed. The region other than the second resist pattern 25 is covered with a third resist pattern 28. Then, the resist patterns 24, 25 and 28, especially the resist Pattern 25, are used as the masks, and the surface of the substrate 2 is etched. Thus, an alignment pattern 29 is made to remain. The resist patterns 24, 25 and 28 are removed. Then, heat treatment is performed, and boron and phosphorus are diffused. Thus, P- and N-type wells 30 and 31 without the step differences on the respective surfaces are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to at least two or more first mutually different first well formation regions set on a main surface of a semiconductor substrate. , A semiconductor device having wells of the second conductivity type adjacent to each other, and an improved manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices, speedup,
A semiconductor device called a so-called CMOS (complementary MOS) is often used to reduce power consumption.
In the case of this type of CMOS, it is necessary to form two wells which are impurity diffusion layers of two different conductivity types.

Next, two adjacent two in the conventional CMOS.
A method for forming two wells of different conductivity types will be described in detail with reference to FIG.

2 (a) to 2 (e) are cross-sectional views each schematically showing the main steps of a conventional method of forming two wells of different conductivity types.

That is, a conventional C having two wells
In the MOS, first, on the semiconductor substrate 1, an oxide film 2 having a thickness of about 200 Å and a nitride film 3 having a thickness of about 1000 Å formed by LPCVD are sequentially formed on the semiconductor substrate 1. After that, a portion corresponding to a region to be an N-type well after that is covered with a resist pattern 4 by using a photolithography method, and the nitride film 3 in a region portion not covered with the resist pattern 4 is selectively formed. It is removed (FIG. 2 (a)).

Then, by using the resist pattern 4 as a mask, boron 5 of about 1 × 10 ¹³ cm ^-2 is selectively ion-implanted into the main surface of the semiconductor substrate 1 to form a P-type impurity layer. 6 is formed (FIG. 2 (b)).

After removing the resist pattern 4,
A thick oxide film 7 having a thickness of about 5000 angstroms is selectively formed in the region where the nitride film 3 is removed by the thermal oxidation method (FIG. 2 (c)).

Next, after removing the remaining nitride film 3, 5 × 10 ¹² cm is added to the region where the nitride film 3 is removed.
The phosphorus 8 of about ^-2 is selectively ion-implanted to form the N-type impurity layer 9. At this time, the P-type impurity layer 6 previously formed is formed.
Since the thick oxide film 7 is present in the region (3), phosphorus 8 is not implanted (FIG. 2 (d)).

Thereafter, a heat treatment is performed in a nitrogen atmosphere at a temperature of about 1100 ° C. to remove the impurities contained in the P-type impurity layer 6 and the N-type impurity layer 9 onto the corresponding main surface of the substrate. The diffusion is performed to a depth of about 3 μm, and thereby the P-type well 10 and the N-type well 11 are formed on the semiconductor substrate 1 as expected (FIG. 2 (e)).

[0010]

However, two wells sequentially formed in the conventional manufacturing method described above, that is, the P-type well 10 and the N-type well 11 are sequentially formed on the main surface of the semiconductor substrate 1. In the process of forming the respective wells, there is a step between the surfaces of the P-type and N-type wells 10 and 11 inevitably resulting in a step. During the formation process of the resist, in particular, at the time of forming a gate using the photolithography method, a resist formed over the respective wells 10 and 11 due to a surface step difference between the wells 10 and 11 is formed. Will have different film thicknesses.

As shown in FIG. 3, when the resist film thicknesses are different from each other, the amount of light absorbed in the resist is also different, so that each well 1 has the same exposure time.
Even if a resist pattern is formed on the layers 0 and 11, there is a problem in that the pattern widths are different from each other, which adversely affects subsequent gate formation.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to form two or more wells of different conductivity types on the main surface of a semiconductor substrate. In this case, there is provided a semiconductor device of this kind and a method for manufacturing the same, in which the surface step between the wells is eliminated so that the resist pattern width in the subsequent process can be formed with good uniformity. That is.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention and a method for manufacturing the same are provided with a thick oxide film formed in the process of forming a first well and a second well. By adopting an eliminable means, the surface step generated between these wells is eliminated.

That is, the present invention is a semiconductor device having at least two wells of different first and second conductivity types adjacent to each other in a well forming region set on the main surface of a semiconductor substrate. 2. In the semiconductor device according to the first aspect, each of the individual wells is formed on a flat surface having no surface step.

Further, according to the present invention, a semiconductor device having at least two wells of different first and second conductivity types adjacent to each other in a well forming region set on the main surface of a semiconductor substrate. And a first step of implanting a first conductivity type impurity into the entire surface of the set well formation region, and a predetermined first conductivity type impurity implantation region of the impurity implantation region. With a first resist pattern, and a second step of covering a reference area for mask alignment with a second resist pattern, and using at least the first resist pattern as a mask. A third step of implanting an impurity of the second conductivity type into a region not covered by the first resist pattern; and a region covered by the first resist pattern. And a fourth step of covering the entire surface of the well forming region excluding the covered area by the second resist pattern by the third resist pattern, the second
By etching using the resist pattern of
A fifth step of forming a reference pattern in the reference area,
After removing the resist patterns, the first and second resist patterns are removed.
A sixth step of diffusing the respective impurities injected into the conductivity type impurity implantation regions into the respective regions to form the first and second conductivity type wells, respectively. A method for manufacturing a semiconductor device is characterized in that the two conductivity type wells are formed on a flat surface having no surface step.

[0016]

Therefore, in the present invention, since the surface step between the wells of the first and second conductivity types formed adjacent to each other is eliminated, the film thickness of the resist pattern formed in the subsequent step is reduced. Therefore, the resist pattern can be made uniform and the width of the resist pattern can be set as a predetermined value.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to FIG.

1 (a) to 1 (e) show a semiconductor device to which an embodiment of the present invention is applied and a method of manufacturing the same, in which two adjacent impurity diffusion layers of different conductivity types in a CMOS are shown. FIG. 3 is a cross-sectional view schematically showing main steps of a method for forming a certain well in order.

That is, in the CMOS having two mutually different wells according to the method of this embodiment, first, 1 × 10 ¹³ cm is added to the well forming region set on the main surface of the semiconductor substrate 21. ^-2 boron (in this case,
A P-type impurity layer 23 is formed by ion-implanting 22 of the first conductivity type impurities (FIG. 1A).

Further, a portion corresponding to a region which will be a P-type well on the P-type impurity layer 23 is covered with a first resist pattern 24 by using a photolithography method.
At the same time, after forming a second resist pattern 25 for obtaining an alignment pattern serving as a reference for mask alignment in the subsequent steps and the like, these patterns 24, 25 are formed.
With a mask of about 1 × 10 ¹³ cm ^-2 phosphorus (in this case,
Ion implantation of 26 corresponding to the second conductivity type impurity is performed to form an N-type impurity layer 27 (FIG. 1B).

Then, the first resist pattern 24 is formed.
And a region other than the second resist pattern 25 is covered with the third resist pattern 28 (FIG. 1 (c)). In this state, each of the resist patterns 24, 25 and 28, especially the second resist pattern The substrate surface is etched using the resist pattern 25 as a mask to leave the alignment pattern 29 in the corresponding region (FIG. 1 (d)).

Then, the resist patterns 24 and 2 are formed.
After removing all 5,28, in a nitrogen atmosphere, 110
By performing the heat treatment at a temperature of about 0 ° C., the boron implanted in the P-type impurity layer 23 and the phosphorus implanted in the N-type impurity layer 27 are diffused, and the desired well formation region is not formed. A P-type well 30 and an N-type well 31 having no steps are formed on the surfaces of the two adjacent streets (FIG. 1 (e)).

Therefore, in the method of the above embodiment, the P-type impurity layer 23 is formed, and then the portion of the P-type impurity layer 23 corresponding to the P-type well is covered with the first resist pattern 24. Since the N-type impurity layer 27 is formed by using the mask of the first resist pattern 24, as a result, the P-type well 30 and the N-type well 31 are formed.
There is no possibility of causing a surface step between them, and the second resist pattern 25 is formed in conformity with the first resist pattern 24, and the N-type impurity layer 27 is covered with the third resist pattern 28. The alignment pattern 29 can be easily formed by etching using the second resist pattern 25 as a mask.

In the method of the above embodiment, the N-type impurity layer 27 is formed after the P-type impurity layer 23 is formed. However, the order of formation is not necessarily limited, and the N-type impurity layer is not limited thereto. Needless to say, the P-type impurity layer may be formed after the formation of.

[0025]

As described above in detail with reference to the embodiments,
According to the present invention, in a semiconductor device having at least two wells of different first and second conductivity types adjacent to each other in a well formation region set on a main surface of a semiconductor substrate, After forming the impurity layer of the first conductivity type in the well formation region set on the main surface of the substrate, the first conductivity type impurity layer is formed.
A portion of the conductivity type impurity layer corresponding to the second conductivity type well is covered with the first resist pattern, and the second conductivity type impurity layer is formed by the mask of the first resist pattern. Therefore, there is no possibility that a surface step will be formed between the wells of the first and second conductivity types that are finally formed adjacent to each other, and thus the film thickness of the resist pattern formed in the subsequent process can be improved. It can be made uniform and the pattern width can be set accurately.
A second resist pattern is formed together with the first resist pattern so as to obtain a reference alignment pattern for mask alignment in the subsequent steps, and the third resist pattern is formed on the second conductivity type impurity layer. The desired alignment pattern can be easily obtained by performing the etching with the second resist pattern as a mask.

[Brief description of drawings]

FIG. 1 is a cross-sectional view that sequentially schematically shows main steps of a method of forming wells that are two adjacent impurity diffusion layers of different conductivity types in a CMOS to which an embodiment of the present invention is applied. is there.

FIGS. 2A to 2C are cross-sectional views each schematically showing main steps of a method of forming two wells of adjacent conductivity types different from each other in a conventional CMOS.

FIG. 3 is a graph showing the relationship between resist film thickness and resist pattern width.

[Explanation of symbols]

 21 semiconductor substrate 22 boron (P-type impurity) 23 P-type impurity layer 24 first resist pattern 25 second resist pattern 26 phosphorus (N-type impurity) 27 N-type impurity layer 28 third resist pattern 29 alignment pattern 30 P Type well 31 N type well

Claims (2)

[Claims] 1. A semiconductor device having at least two wells of different first and second conductivity types adjacent to each other in a well formation region set on a main surface of a semiconductor substrate, wherein A semiconductor device, characterized in that the respective wells are formed on a flat surface having no surface step. 2. A method of manufacturing a semiconductor device having at least two wells of different first and second conductivity types adjacent to each other in a well formation region set on a main surface of a semiconductor substrate. A first step of implanting a first conductivity type impurity into the entire surface of the set well formation region, and a predetermined first conductivity type impurity implantation region of the impurity implantation region A second step of covering a reference region for resist alignment and a reference area for mask alignment with a second resist pattern, and the first resist pattern using at least the first resist pattern as a mask A third step of implanting an impurity of the second conductivity type into a region not covered by the second region; and a region covered by the first resist pattern, A fourth step of covering the entire surface of the well forming region except the region covered with the resist pattern with the third resist pattern, and a step of forming a reference pattern in the reference region by etching using the second resist pattern as a mask. 5 step, and after removing the resist pattern, the first, second
At least a sixth step of diffusing the impurities injected into the conductivity type impurity implantation regions into the regions to form wells of the first and second conductivity types, respectively. A method for manufacturing a semiconductor device, characterized in that a space between two wells of two conductivity type is formed on a flat surface having no surface step.