JP2658983B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a method for forming impurity diffusion layers of different conductivity types on the same semiconductor substrate.

[0002]

2. Description of the Related Art Generally, an N-type semiconductor substrate is provided on one conductivity type semiconductor substrate.
When an element having a P-type impurity diffusion layer is manufactured, for example, in order to form an NPN-type bipolar transistor, an N-type buried diffusion layer having a high impurity concentration mainly used as a collector or emitter extraction region; After forming a P-type buried diffusion layer used for isolation between elements, it is necessary to grow an N-type epitaxial layer. Conventionally, such two types of N-type and P-type buried diffusion layers are formed by repeating a cycle of forming a mask by a photolithography process, introducing impurities using the mask, and thermally diffusing the introduced impurities twice. Is formed by selectively diffusing impurities. For this reason, there is a problem that the number of steps is increased, and there is also a problem that since there are two photolithography steps, a margin for alignment must be taken into account, and the element size increases.

As a method for improving this, a method of forming two types of buried diffusion layers in a single photolithography process in a self-aligned manner has been proposed in Japanese Patent Laid-Open No. 2-284458. This will be described with reference to FIG. First, FIG.
As shown in FIG. 1A, a silicon nitride film (Si ₃ N ₄ ) is formed on a P-type semiconductor
0nm is formed with a thickness, Si ₃ N ₄ by patterning the the Si ₃ N ₄ film by a known photo-etching technique
A film pattern 12 is formed.

[0004] Next, as shown in FIG. 2 (b), Si ₃ N
_The substrate 11 is subjected to a thermal oxidation treatment using the _four- film pattern 12 as a mask, so that 50 to 100 parts of the surface of the semiconductor substrate 11 where the Si ₃ N ₄ film pattern 12 is removed are formed.
A thin oxide film 13 having a thickness of 10 nm is formed, and using the Si ₃ N ₄ film pattern 12 as a mask, 10 ¹² to 10 ¹³ / cm 2 of P-type impurity boron are applied at 100 keV through the thin oxide film 13.
^Implant about ² ions.

[0005] Next, as shown in FIG. 2 (c), Si ₃ N
_{4 The} film pattern 12 is removed by etching with hot phosphoric acid or the like, and the N-type impurity antimony is
About 10 ¹³ to 10 ¹⁴ ions / cm ² are implanted at 0 keV. Next, as shown in FIG. 2D, after the thin oxide film 13 is removed by etching, the thin oxide film 13 is set to 1150 to 1250 in an atmosphere of an inert gas such as nitrogen or argon mixed with a small amount of oxygen.
A heat treatment is performed at a temperature of about 100 ° C. to activate the ion-implanted impurities, and the P-type buried diffusion layer 14 and the N-type buried diffusion layer
Is formed.

[0006]

The problem to be solved by the present invention is disclosed in Japanese Patent Application Laid-Open No. 2-284.
According to Japanese Patent No. 458, the photolithography process is performed only once, and the number of processes is reduced. Therefore, when P-type and N-type buried diffusion layers having a high impurity concentration are adjacent to each other, a PN junction occurs at the adjacent boundary, and the reverse breakdown voltage of the buried diffusion layer may be reduced. In addition, there is a problem that the junction capacitance between the substrate and the N-type buried diffusion layer is increased, and the operation speed of the formed transistor is reduced.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a manufacturing method capable of forming a P-type diffusion layer and an N-type diffusion layer at arbitrary intervals by a single photolithography step without making contact with the N-type diffusion layer. It is in.

[0008]

According to a manufacturing method of the present invention, a first film containing an impurity of one conductivity type is formed on one main surface of a semiconductor substrate, and a second film is formed on the entire surface thereof. Removing a part of the second film by photolithography to form an opening, and then removing the part of the first film by isotropic etching using the second film as a mask; The surface of the semiconductor substrate larger than the area of the semiconductor substrate is exposed. Next, an impurity of the opposite conductivity type is ion-implanted into the semiconductor substrate using the second film as a mask, and the one conductivity type impurity in the first film is diffused into the semiconductor substrate by heat treatment. Diffusing impurities of the opposite conductivity type inside,
The step of forming each diffusion layer is included.

Here, before the step of ion-implanting impurities of the opposite conductivity type, it is preferable to include a step of forming an oxide film by oxidizing the surface of the semiconductor substrate exposed by heat treatment in an oxidizing atmosphere.

When the one conductivity type impurity is an impurity having a low diffusion constant, the one conductivity type impurity is removed from the first film by heat treatment before the step of ion-implanting the opposite conductivity type impurity. To form a diffusion layer of one conductivity type.

[0011]

The first film is isotropically etched by using the opening provided in the second film, so that the first film can be formed in a shape in which the end is recessed from the opening. The impurity of the opposite conductivity type is ion-implanted through the opening of the first film and the impurity of the one conductivity type is diffused from the first film. It is possible to form the diffusion layer and the diffusion layer of the impurity of the opposite conductivity type separately.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a manufacturing method according to an embodiment of the present invention in the order of steps. Here, an N-type buried diffusion layer of an NPN-type bipolar transistor and element isolation formed between a plurality of N-type buried diffusion layers are shown. Of forming an embedded P-type buried diffusion layer. First, as shown in FIG. 1A, a thickness of 0.1 to 1.0 μm, preferably 0.2 to 1.0 μm is formed on a P-type semiconductor substrate 1.
A glass coating film 2 containing 0.5 μm N-type impurity As, P or Sb is formed,
A partial heat treatment is performed to harden the glass coating film 2. Next, a thickness of 0.2 to 0.6 μm, preferably 0.4 to 0.5 μm
The silicon nitride film 3 is formed on the glass coating film 2. Since the silicon nitride film 3 serves as a mask at the time of boron ion implantation to be described later, it is necessary to select the film thickness so as to be at least the projection range of boron ion implantation.

Next, as shown in FIG. 1B, by photolithography and anisotropic etching using a photoresist (not shown), a silicon nitride film on a P-type semiconductor substrate which will become a P-type buried diffusion layer in the future. 3 is removed to form an opening 3a. Then, after removing the resist, the glass coating film 2 is formed using the silicon nitride film 3 in which the opening 3a is formed as a mask.
Is removed by isotropic etching to expose a part of the P-type semiconductor substrate 1. At this time, the etching amount of the glass coating film 2 is 2 to 2 in the dimension B of the exposed P-type semiconductor substrate 1 than in the dimension A of the opening 3a of the silicon nitride film 3.
It should be 10 μm wide, preferably 5-8 μm wide. As the etching amount of the glass coating film 2 increases, the reverse breakdown voltage between the buried diffusion layers increases, and the diffusion capacity decreases. Regarding the selection of the etching amount, when the transistor operates,
The distance may be set so that a depletion layer generated between the N-type buried diffusion layer and the P-type semiconductor substrate does not reach the P-type buried diffusion layer. When the density is 1 × 10 ^15, the width B is 8 μm more than the interval A.
m is enough.

Next, as shown in FIG.
A heat treatment is performed in an oxidizing atmosphere at 00 ° C., and a thickness of 10 to 80 nm, preferably 2 nm is formed on the exposed surface of the P-type semiconductor substrate 1.
A silicon oxide film 4 having a thickness of 0 to 60 nm is formed. This silicon oxide film 4 may not be formed, but it has the effect of preventing the N-type impurity from diffusing from the gas phase into the portion to be the P-type buried diffusion layer during the heat treatment for the N-type impurity diffusion. Has the effect of reducing the occurrence of defects occurring in the semiconductor substrate at the time of ion implantation. Next, heat treatment is performed in an inert atmosphere at 1100 to 1200 ° C. to diffuse N-type impurities from the glass coating film 2, and N-type buried diffusion having a sheet resistance of 10 to 200 Ω / □, preferably 20 to 40 Ω / □. The layer 5 is formed. The heat treatment step may be omitted, but if the P-type impurity and the N-type impurity are simultaneously diffused in a later step, As
In order to sufficiently diffuse Sb and Sb, a long-time heat treatment must be performed at a high temperature, and a boron diffusion layer having a high diffusion constant, which is mainly used as a P-type impurity, is excessively widened. It is better to diffuse the impurities first.

Next, as shown in FIG. 1 (d), a P-type impurity boron is applied at 60 to 120 keV, preferably 80 to 10 keV through the silicon oxide film 4 using the silicon nitride film 3 as a mask.
At 0 keV, 10 ¹³ to 10 ¹⁵ particles / cm ² , preferably 3
× 10 ^{13 to} 2 × 10 ¹⁴ particles / cm ^{2 are} implanted. According to LSS theory, the projected range of boron is 0.23 at 60 keV.
Since it is 0.45 μm at μm and 120 keV, it is possible to implant ions into the semiconductor substrate through the silicon oxide film 4. Since the thickness of the silicon nitride film 3 is equal to or greater than the projection range of boron, boron is hardly implanted into the semiconductor substrate 1 under the silicon nitride film 3. next,
A heat treatment is performed in an inert atmosphere at 900 to 1100 ° C. for 20 to 30 minutes to activate the P-type impurities and form the P-type buried diffusion layer 6.

Thereafter, as shown in FIG. 1E, the silicon nitride film 3 is entirely removed, the glass coating film 2 and the silicon oxide film 4 are removed, and then an N-type epitaxial layer 7 is formed. Thereafter, although not shown, a P-type base and an N-type emitter of an NPN bipolar transistor are formed on the N-type buried diffusion layer 5 of the N-type epitaxial layer 7, and a P-type base is formed on the P-type buried diffusion layer 6. By forming an element isolation layer, N
It becomes possible to form an array of PN bipolar transistors.

Therefore, in this manufacturing method, the N-type buried diffusion layer 5 and the P-type buried diffusion layer 6 can be formed by one photolithography. In addition, the glass coating film 2
By etching isotropically, the end can be set at a position recessed from the end of the silicon nitride film 3, so that the P-type buried diffusion layer 6 formed using the silicon nitride film 3 as a mask can be formed. The end and the end of the N-type buried diffusion layer 5 formed by diffusion from the glass coating film 2 can be separated.
Thereby, the end portions of the P-type buried diffusion layer 6 and the N-type buried diffusion layer 5 do not come into contact with each other to form a junction, the reverse breakdown voltage between the buried diffusion layers does not decrease, and the junction does not occur. The capacity does not increase and the operation speed of the transistor does not decrease.

In this case, the N-type buried diffusion layer 5 and the P-type buried diffusion layer 5 are formed by appropriately setting the etching amount of the glass coating film, that is, the retreat amount of the glass coating film 2 with respect to the end of the silicon nitride film. The distance from the diffusion layer 6 can be set arbitrarily. Furthermore, in this case, it is needless to say that the dimensions of the selected pattern of the silicon nitride film 3 are appropriately set, so that the planar dimensions of the N-type buried diffusion layer 5 and the P-type buried diffusion layer 6 can be set arbitrarily. No.

Although the above embodiment shows an example in which an N-type buried diffusion layer and a P-type buried diffusion layer of an NPN bipolar transistor are formed, the N-type diffusion layer required for manufacturing a MOS transistor is formed. It is also possible to form a P-type diffusion layer at the same time. Further, even if the N-type in the above embodiment is changed to the P-type and the P-type is changed to the N-type, the N-type buried diffusion layer and the P-type buried diffusion layer can be similarly formed by one photolithography.

[0020]

As described above, according to the present invention, the first film is isotropically etched using the opening provided in the second film so that the end of the first film is formed. The second conductive film can be formed in a shape recessed from the opening, ion-implanted with an impurity of the opposite conductivity type through the opening of the second film, and diffused with one impurity of the conductivity type from the first film to form each impurity layer. It becomes possible to form the diffusion layer of the one conductivity type impurity and the diffusion layer of the opposite conductivity type impurities at the end of the one film apart from each other by the recessed amount. Accordingly, diffusion layers of different conductivity types can be formed in a self-aligned manner by one photolithography, so that the number of steps can be reduced, and the interval between diffusion layers of different conductivity types can be arbitrarily set. In addition, the reverse breakdown voltage of the diffusion layer can be increased, and the diffusion capacitance of both diffusion layers can be reduced.

Further, by oxidizing the surface of the semiconductor substrate exposed before the ion implantation of the impurity of the opposite conductivity type to form an oxide film, the impurity of one conductivity type is diffused into the diffusion region of the opposite conductivity type by vapor phase diffusion. Spreading can be prevented.

Further, when the one conductivity type impurity is an impurity having a low diffusion constant, the one conductivity type impurity is diffused from the first film into the semiconductor substrate before the opposite conductivity type impurity is ion-implanted. In addition, it is possible to prevent the impurity of the opposite conductivity type having a high diffusion constant from being excessively diffused.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a manufacturing method of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view showing an example of a conventional manufacturing method in the order of manufacturing steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 Glass coating film 3 Silicon nitride film 4 Silicon oxide film 5 N-type buried diffusion layer 6 P-type buried diffusion layer 7 N-type epitaxial layer

Claims (4)

(57) [Claims] A step of forming a first film containing an impurity of one conductivity type on one main surface of a semiconductor substrate; a step of forming a second film over the entire surface of the first film; Removing a part of the second film to form an opening, and removing the part of the first film by isotropic etching using the second film as a mask to reduce the area of the opening. Exposing the surface of the semiconductor substrate,
Ion-implanting an impurity of the opposite conductivity type into the semiconductor substrate using the film as a mask; and diffusing the impurity of the one conductivity type in the first film into the semiconductor substrate by heat treatment, and simultaneously A method for manufacturing a semiconductor device, comprising a step of diffusing a conductive impurity to form respective diffusion layers. 2. The semiconductor device according to claim 1, further comprising a step of oxidizing a surface of the semiconductor substrate exposed by a heat treatment in an oxidizing atmosphere to form an oxide film before the step of ion-implanting the impurity of the opposite conductivity type. Manufacturing method. 3. The one-conductivity-type impurity is an impurity having a low diffusion constant. Before the step of ion-implanting the opposite-conductivity-type impurity, the one-conductivity-type impurity is transferred from the first film to the semiconductor substrate by heat treatment. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a diffusion layer of one conductivity type by diffusing. 4. The method according to claim 1, wherein the first film is a glass coating film containing one conductivity type impurity, and the second film is a silicon nitride film.