JP2003077935A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a size of a gate electrode layer in processing and to control a regions of impurity diffusion layers (= a source region, a drain region) in a heat treatment step in particular when having a LDD structure as a gate length shortens with a MOS transistor made fine. SOLUTION: The impurities 110 are introduced into a silicon substrate 101 using a silicon nitride film pattern 107 and a polycrystal silicon film pattern 108 as a mask, a high concentration impurity diffusion layers of an N type (N<+> type diffusion layers 111, 112) are formed at positions of a source region and a drain region of the MOS transistor. Next, by using chemical dry etching (CDE) method or the like, the polycrystal silicon film pattern 108 is isotropic etched from both sides direction and thus the gate electrode layer 115 is formed. Next, by using the gate electrode layer 115 as a mask, the impurity is introduced and thus a low concentration impurity diffusion layer of an N type is formed.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention is particularly applicable to LDD (Li
The present invention relates to a method for manufacturing a semiconductor device having a MOS transistor having a ghtly Doped Drain structure.

[0002]

2. Description of the Related Art At present, the miniaturization of MOS transistors has progressed further, and the width of the gate electrode layer (= gate length) is 1 μm.
It has been narrowed down to m or less. In this way, as miniaturization progresses, in order to suppress fluctuations in threshold voltage and the like, impurity diffusion regions having a lower concentration than these are formed in the vicinity of the source region and the drain region, and Make the impurity concentration distribution gentle (= LDD (Lightly
Doped drain structure), and it is necessary to increase the withstand voltage of MOS transistors.

A conventional method of manufacturing a semiconductor device will be described below with reference to FIGS. Here, as an example, a method of manufacturing a CMOS transistor having an LDD structure will be described.

First, a silicon oxide film 302 having a film thickness of about 2.5 nm is formed on the entire surface of a silicon substrate 301. The silicon oxide film 302 is used as a gate insulating film forming a MOS transistor. After that, a polycrystalline silicon film 303 is formed as a conductive film on the silicon oxide film 302 (= gate oxide film) with a film thickness of about 200 nm. This conductive film is used as a material for the gate electrode layer of the MOS transistor.

Next, a photosensitive photoresist film is formed by coating on the polycrystalline silicon film 303. After that, an exposure step and a development step are performed by using a lithography technique, and as shown in FIG. 8A, on the polycrystalline silicon film 303,
A resist pattern 304 is formed.

Next, as shown in FIG. 8B, a gate electrode layer 305 of the MOS transistor is formed in each region on the silicon substrate 301. Here, an anisotropic etching technique such as RIE is used to selectively etch the polycrystalline silicon film 303 using the resist pattern 304 as a mask to form a pattern. Hereinafter, this pattern is used as the gate electrode layer 305.

Next, a low-concentration impurity diffusion layer is formed in each of the N-type and P-type MOS transistor regions by using the lithography technique and the ion implantation method.

Here, first, as shown in FIG. 8C, N-type low-concentration impurity diffusion layers, that is, N ^-- type diffusion layers 308 and 309 are formed, and thereafter, P-type MOS transistor regions are formed. Similarly, a low-concentration impurity diffusion layer is formed.

In this case, first, a photoresist film 306 is deposited so as to cover the P type transistor region.
After that, in this state, the impurity 307 is introduced into each position corresponding to the source region and the drain region of the N-type MOS transistor region by using the gate electrode layer 305 as a mask in the ion implantation method. Here, the impurities include
Arsenic (As) or the like is used.

Next, as shown in FIG. 9A, a P-type M
P-type low-concentration impurity diffusion layers, that is, P ⁻ -type diffusion layers 310 and 311 are also formed at positions corresponding to the source region and the drain region of the OS transistor region. In this case, in order to form a P type low concentration impurity diffusion layer, an N type M
The OS transistor region is covered with a photoresist film, and in the same manner, ion implantation is used to introduce impurities into the drain region and the source region of the P-type MOS transistor region. Here, BF ₂ or the like is used as the impurity.

Next, low-concentration impurity diffusion layers, N ^-- type diffusion layers 308 and 309, and P ^-- type diffusion layers 310 and 311.
Then, a so-called annealing process is performed. Here, the silicon substrate 301 is subjected to heat treatment at about 850 ° C. to activate the impurities in the N ⁻ type diffusion layers 308 and 309 and the P ⁻ type diffusion layers 310 and 311.

Next, a silicon oxide film 312 having a thickness of about 20 nm is formed on the entire surface of the silicon substrate 301 so as to cover the silicon oxide film 302 and the gate electrode layer 305 (= polycrystalline silicon film pattern). To do. afterwards,
As shown in FIG. 9A, a silicon nitride film 313 (= side wall) having a film thickness of about 70 nm is formed on the silicon oxide film 312 along the side wall of the gate electrode layer 305 (= polycrystalline silicon film pattern). To form.

Here, first, the chemical vapor deposition method (= C
VD method) or the like to form a silicon oxide film 312 with a thickness of about 20 nm,
A silicon nitride film 313 having a film thickness of about 70 nm is sequentially formed.
It is formed in a laminated shape. After that, an anisotropic etching technique such as RIE is used to leave the silicon nitride film 31 along the side wall of the gate electrode layer 305 (= polycrystalline silicon film).
Process 3 (= sidewall).

Next, as shown in FIG. 9B, an N-type high-concentration impurity diffusion layer is formed by a lithography technique and an ion implantation method using the silicon nitride film 313 (= side wall) as a mask. And a P-type impurity diffusion layer are formed.

Here, first, a photoresist film 314 is deposited so as to cover the P-type MOS transistor region. Then, in this state, the impurity 315 is introduced into each position corresponding to the source region and the drain region of the N-type MOS transistor region by using the silicon nitride film 313 (= sidewall) as a mask, and the N ⁺ -type diffusion is performed. Layer 31
6, 317 are formed. Here, the impurities 315 include
Arsenic (As) or the like is used.

Next, as shown in FIG. 9C, a P-type M
High-concentration impurity diffusion layers, that is, P ⁺ type diffusion layers 318 and 319 are also formed in the OS transistor region. Here, P ⁺ type diffusion layers 318 and 319 are formed by using boron (B) or the like as an impurity in the same manner as the case of forming the N ⁺ type diffusion layers 316 and 317.

After that, a high concentration impurity diffusion layer (= N⁺Type
Diffusion layer, and P⁺Annealing treatment is applied to the mold diffusion layer). This
Here, the silicon substrate 301 is heat-treated at 1035 ° C.
Then N ⁺Type diffusion layers 316, 317, and P⁺Type diffusion layer 31
Activate the impurities of 8,319.

The N ⁺ type diffusion layers 316, 317 and P ⁺
The type diffusion layers 318 and 319 are N-type and P-type M, respectively.
The OS transistor functions as a source region and a drain region.

[0019]

When such a method is used, a high concentration impurity diffusion layer (= N ⁺ type diffusion layer 31
6, 317, P ⁺ -type diffusion layers 318, 319) in the process of activating impurities, the impurity concentration of the impurity diffusion layer (= N ⁻ -type diffusion layer 3) is low in proportion to the impurity concentration and the volume of the diffusion layer.
08, 309, P ⁻ -type diffusion layers 318, 319), it is necessary to perform annealing treatment at a higher temperature.
In this case, if heat treatment is performed in the process of activating the impurities in the high-concentration impurity diffusion layer, the heat treatment also acts on the low-concentration impurity diffusion layer, and the impurities diffuse to the periphery to expand the region.

As a result, when the gate length is shortened to 1 μm or less (eg, 0.15 μm) with the miniaturization of the semiconductor device, a short channel effect easily occurs, which causes a remarkable deterioration in the characteristics of the MOS transistor. Become.

Further, as described above, in the conventional technique, RIE is used.
A pattern is formed on the polycrystalline silicon film 303 by using an anisotropic dry etching technique such as a method using the resist pattern as a mask. This pattern is used as a mask in forming a low-concentration impurity diffusion layer,
A MOS transistor is formed as the gate electrode layer 305.

Here, first, a resist pattern 304 (= mask pattern) is formed on the polycrystalline silicon film 303 (= processed film) by using a lithography technique, and the size and shape of the resist pattern 304 are changed. A pattern is formed by transfer to the polycrystalline silicon film 303 by means of isotropic dry etching.

In this case, as miniaturization progresses, dimensional errors and the like are likely to occur in the exposure process, the development process, and the dry etching process, and the degree of influence is great in improving the performance and reliability of the semiconductor device. Become. In particular, as the gate length of the MOS transistor becomes shorter, the misalignment of the mask position occurs when introducing impurities, and it is impossible to accurately form each low-concentration impurity diffusion layer at a predetermined position. Becomes

Further, if the pattern formed on the polycrystalline silicon film 303 is used for the gate electrode layer, misalignment of the position of the gate electrode layer, processing size error, etc. will occur, and the operation of the MOS type transistor will occur. Etc. have a very large adverse effect.

In view of the above problems, it is an object of the present invention to provide a method of manufacturing a semiconductor device having high performance and high reliability, which corresponds to miniaturization.

[0026]

The present invention provides a method of manufacturing a semiconductor device having high performance and high reliability in response to miniaturization.

According to the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a conductive film on the insulating film, a step of forming a mask pattern on the conductive film, and using this mask pattern Etching to form a pattern on the conductive film, and using the pattern formed on the conductive film as a mask, introducing impurities into the semiconductor substrate,
Forming a first impurity diffusion layer on the semiconductor substrate; heat treating the first impurity diffusion layer; isotropically etching both side surfaces of the conductive film pattern; Using the etched pattern as a mask, introducing an impurity of the same conductivity type as the impurity to form a second impurity diffusion layer having a lower impurity concentration than the first impurity diffusion layer on the semiconductor substrate. And a step of heat-treating the second impurity diffusion layer at a temperature lower than a temperature of heat-treating the first impurity diffusion layer.

The present invention also includes the steps of forming a gate insulating film on a semiconductor substrate, forming a conductive film on the gate insulating film, and forming a mask pattern on the conductive film. Etching using a mask pattern to form a pattern on the conductive film; a step of introducing impurities by using the conductive film pattern as a mask to form a first impurity diffusion layer; A step of heat-treating the diffusion layer to form a source region and a drain region on the semiconductor substrate; and using the mask pattern to perform isotropic etching on both side surfaces of the conductive film pattern to form a gate insulating film on the gate insulating film. A step of forming a gate electrode layer on the semiconductor substrate, and using the gate electrode layer as a mask, introducing an impurity of the same conductivity type as that of the impurity into the source region and the drain region of the semiconductor substrate. A second impurity diffusion layer having a lower impurity concentration than that of the first impurity diffusion layer, and a temperature for heat-treating the second impurity diffusion layer and the first impurity diffusion layer. And a step of performing a heat treatment at a lower temperature than the above.

As described above, according to the present invention, a semiconductor device having high performance and high reliability can be manufactured by suppressing the short channel effect and responding to miniaturization.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
A description will be given with reference to the drawings. (First Embodiment) In the present embodiment, a CMOS transistor having an LDD structure will be described as an example with reference to FIGS.

First, a silicon oxide film 102 having a film thickness of about 2.5 nm is formed on the entire surface of the silicon substrate 101. A part of the silicon oxide film 102 constitutes the gate oxide film of the MOS transistor. After that, a conductive film is formed over the silicon oxide film 102. This conductive film is N
Type and P type MOS transistors, it is used as a material for forming a gate electrode layer. Here, as the conductive film, a chemical vapor deposition method (hereinafter referred to as a CVD method) is used.
Etc., the polycrystalline silicon film 103 is formed to a film thickness of about 200 nm. After that, as shown in FIG. 1A, a silicon nitride film 104 is formed on the polycrystalline silicon film 103.
About 0 nm, and then a photosensitive photoresist film 105
Are sequentially formed with a film thickness of about 400 nm.

Next, an exposure step and a development step are performed by using a lithographic technique, and as shown in FIG. 1B, a resist pattern 1 having a predetermined dimension width (eg, 0.33 μm).
06 is formed.

Next, using the resist pattern 105 as a mask, an anisotropic dry etching technique is applied, and FIG.
As shown in (c), a pattern (= silicon nitride film pattern 107 / polycrystalline silicon film pattern 108) having a predetermined size and shape is formed on each of the silicon nitride film 104 and the polycrystalline silicon film 103. Here, patterns having dimensions and shapes according to the resist pattern 105 are sequentially formed on the silicon nitride film 104 and the polycrystalline silicon film 103 by etching.

Here, for the anisotropic dry etching technique, a reactive ion etching method (hereinafter referred to as RIE method) suitable for fine processing may be used.

After that, N which constitutes the CMOS transistor
Type and P type MOS transistors are formed in predetermined regions on the silicon substrate 101, respectively. These, N
Type and P type MOS transistors are so-called LOC.
It is assumed that they are isolated from each other by an element isolation region (hereinafter, not particularly shown) such as OS or STI (Shallow Trench Isolation).

Next, as shown in FIG.
Nitride film pattern 107 and polycrystalline silicon film pattern
108 is used as a mask and a predetermined amount is formed by an ion implantation method.
Impurity 110 is introduced to each polycrystalline silicon film pattern 1
08 on both sides, that is, the source region and the drain region
A high-concentration impurity diffusion layer (= N ⁺
The mold diffusion layers 111, 112) are formed.

Here, first, a photoresist film 109 is deposited by using a lithography technique so as to cover a region for (forming) a P-type MOS transistor. After that, in this state, as shown in FIG.
As described above, the impurity 110 is introduced into each of the positions corresponding to the source region and the drain region of the S-transistor region, and the high-concentration N-type impurity diffusion layer (hereinafter referred to as N ⁺ -type diffusion layer
11 and 112) are formed. N ⁺ type diffusion layer 11
Each of 1 and 112 constitutes a source region and a drain region in the N-type MOS transistor.

In the present embodiment, as an example, N ⁺
The type diffusion layers 111 and 112 use arsenic (As) or the like as an impurity and have an energy (= accelerating voltage) of 50 ke.
v, the dose amount is 5e15 (= 5.0 × 10 ¹⁵ ) (ato
Under the condition of about ms / cm ² ), they are formed by introducing into the positions corresponding to the source region and the drain region.

Next, as shown in FIG. 2B, a P-type M
Also in the OS transistor, a high-concentration impurity diffusion layer, that is,
P ⁺ type diffusion layers 113 and 114 are formed.

Here, first, the photoresist film 109 is removed from the region where the P-type MOS transistor is to be formed. Then, using a lithography technique, a photoresist is deposited so as to cover the N-type MOS transistor region, and in this state, it corresponds to the source region and the drain region of the P-type MOS transistor (forming) region. Impurities are introduced into each position (above, not particularly shown). After that, from above the N-type MOS transistor region,
The photoresist film is removed. P ⁺ type diffusion layers 113, 1
Each of 14 forms a source region and a drain region in a P-type MOS transistor.

In this embodiment, as an example, P ⁺
Boron (B) is used as an impurity in the type diffusion layers 113 and 114, and this is used with an energy (= accelerating voltage) of 5 kev and a dose of 4e15 (= 4.0 × 10 ¹⁵ ) (atoms /
It is formed by introducing into the positions of the source region and the drain region under the condition of about cm ² ).

As described above, the high-concentration impurity diffusion layers, the N ⁺ -type diffusion layers 111 and 112, and the P ⁺ -type diffusion layers 113 and 114 are formed in the N-type and P-type MOS transistor regions.

In the case of this embodiment, the N ⁺ type diffusion layers 111 and 112 and the P ⁺ type diffusion layer 11 are provided in each transistor region.
The order of forming 3, 114 is not particularly limited. Therefore, contrary to the above case, the high-concentration impurity diffusion layers may be formed in the order of the P ⁺ type diffusion layers 113 and 114, and then the N ⁺ type diffusion layers 111 and 112.

Next, the high-concentration impurity diffusion layer (= N ⁺ type diffusion layer and P ⁺ type diffusion layer) is subjected to so-called annealing treatment. Here, the silicon substrate 101 is subjected to a heat treatment at about 1035 ° C. to activate the impurities in the N ⁺ type diffusion layers 111 and 112 and the P ⁺ type diffusion layers 113 and 114, and the N type and P type MOS transistor regions. Then, a source region and a drain region are formed.

In the heat treatment, for example, RTA (Rapid
It is effective to use the Thermal Anneal method.

As described above, in the N-type and P-type MOS transistor regions, high-concentration impurity diffusion layers, that is, N ⁺ -type diffusion layers 111 and 112, and P ⁺ -type diffusion layers 113 and 11, respectively.
4 is formed.

Next, as shown in FIG. 2C, CDE
By a isotropic etching such as (Chemical-Dry-Etching) method, the polycrystalline silicon film pattern 108 is selectively etched by an equal amount from both side surfaces to form a gate electrode layer having a predetermined gate length. 115 is formed. Specifically, as an example, the polycrystalline silicon film pattern 108
Is about 90 nm from both sides, for a total of 180 n
The gate electrode layer 115 is formed by etching to a width of about 0.15 μm.

In this case, in the CDE method, for example, CF ₄ / O ₂ / Cl ₂ is used as the etching gas, and the component ratio of these gases is 7: 3: 1. The etching processing time is about 10 seconds.

In this case, in the CDE method, the selection ratio (= etching rate ratio) of polycrystalline silicon / silicon nitride is about 30, and the polycrystalline silicon film pattern 10 is used.
The conditions are set so that the etching rate of No. 8 is about 300 nm / min. Further, at this time, the selection ratio with the silicon oxide film 102 (= gate oxide film) (=
The etching rate ratio) can be about 50.

Here, the upper surface of the gate electrode layer 115 is
Covered by the silicon nitride film pattern 107,
The etching acts evenly from both sides. Therefore, in the process of etching by the CDE method, the gate electrode layer 115 is formed by precisely processing only the pattern width and the dimension corresponding to the gate length without changing the film thickness of the polycrystalline silicon film pattern 108. You can Further, at this time, unlike anisotropic dry etching such as the RIE method, the silicon oxide film 102 (= gate oxide film) can be prevented from being adversely affected by physical composition destruction or the like. Does not lower the

Next, as shown in FIG. 3A, the silicon nitride film pattern 107 is selectively removed from the gate electrode layer 115 by using isotropic etching such as wet etching. In this case, the wet etching method uses a solution of H ₃ PO ₄ and the processing time is about 100 seconds.

As described above, in the process of etching the polycrystalline silicon film pattern 108 using isotropic etching such as the CDE method, a part of the silicon nitride film pattern 107 is also etched at the same time. 115
There is no particular problem in the dimensional accuracy of.

Next, the N type low concentration impurity diffusion layer and the P type low concentration impurity diffusion layer are formed using the gate electrode layer 115 as a mask by using the lithography technique and the ion implantation method.

Here, first, the photoresist film 116 is covered so as to cover a region for forming a P-type MOS transistor.
Deposit. Then, in this state, as shown in FIG. 3B, the gate electrode layer 115 is used as a mask at each position corresponding to the source region and the drain region of the N-type MOS transistor region by using the ion implantation method. Impurity 1
Introduce 17. Here, the N ⁻ type diffusion layers 118 and 119
Along the gate electrode layer 115, the N ⁺ type diffusion layer 111,
It can be expanded from 112 and formed at a position in the vicinity thereof.

The N ⁻ type diffusion layers 118 and 119 are, for example, arsenic (As) is used as the impurity 117, the energy (= accelerating voltage) is 3 kev, and the dose amount is 1.0 e.
It is formed in a predetermined region of the silicon substrate 101 under the condition of about 15 (= 1.0 × 10 ¹⁵ ) (atoms / cm ² ).

Next, as shown in FIG. 3C, a P-type M
Also in the OS transistor region, low-concentration impurity diffusion layers, that is, P ⁻ type diffusion layers 120 and 121 are formed.

Here, first, the photoresist film 116 is removed from above the P-type MOS transistor region. After that, a photoresist film is deposited by lithography so as to cover the N-type MOS transistor region, and in this state, a P-type MOS transistor region is also formed.
An impurity is introduced into each position corresponding to the source region and the drain region by using an ion implantation method. Here, with the gate electrode layer 115 as a mask, impurities are introduced into the positions of the source region and the drain region along both sides thereof.
After that, the photoresist film is removed from the N-type MOS transistor region (above, not particularly shown).

The P ^-- type diffusion layers 120 and 121 use, for example, BF ₂ as an impurity, energy (= accelerating voltage) of 2.5 kev, and dose of 1.0e15 (=).
It is formed in a predetermined region of the silicon substrate 101 under the condition of about 1.0 × 10 ¹⁵ ) (atoms / cm ² ).

As described above, the gate electrode layer 115 is selectively and uniformly etched in the direction of both side surfaces, and the N-type and P-type M-layers are formed without causing positional deviation.
It is formed at a predetermined position in the OS transistor region. Therefore, using the ion implantation method, the gate electrode layer 1
If impurities are introduced using 15 as a mask, a low concentration impurity diffusion layer, that is, N ⁻ type diffusion layers 118, 119 and P ^−.
The mold diffusion layers 120 and 121 can be accurately formed at predetermined positions.

In the case of the present embodiment, the N ⁻ type diffusion layers 118 and 119 and the P ⁻ type diffusion layer 12 are provided in each transistor region.
The order of forming 0 and 121 is not particularly limited. Therefore, contrary to the above case, the low-concentration impurity diffusion layers may be formed in the order of the P ⁻ type diffusion layers 120 and 121, and then the N ⁻ type diffusion layers 118 and 119.

[0061] Next, a low concentration impurity diffusion layer, P^-Type diffusion
Layers 120, 121, and N^-Type diffusion layers 118 and 119
Then, a so-called annealing process is performed. Here, silicon-based
The plate 101 is subjected to heat treatment at about 850 ° C., and N^-Type diffusion layer
118, 119, and P^-Of the mold diffusion layers 120 and 121
Activate pure things.

As described above, the silicon substrate 101
In addition, so-called LDD structure N-type and P-type MOS
Form a transistor. Corresponding to the progress of miniaturization, C
A MOS transistor can be formed.

In this embodiment, the method of forming the low-concentration impurity diffusion layer can be changed as follows.

For example, in the case of the present embodiment, the gate electrode layer 115 is not removed without removing the silicon nitride film pattern 107.
It is also possible to form the N ⁻ -type diffusion layer and the P ⁻ -type diffusion layer by using the ion implantation method while leaving them above.
In this case, as shown in FIG. 4, the P-type MOS transistor region is covered with a photoresist film 116 so as to pass through the silicon nitride film pattern 107, and an impurity 117 is introduced into the silicon substrate 101 from substantially vertically above. ,
The N ⁻ type diffusion layer 11 is formed in the N type MOS transistor region.
8 and 119 are formed. After that, in the same way, N type M
The OS transistor region is covered with a photoresist film, impurities are introduced into the silicon substrate 101, and a P ⁻ type diffusion layer is also formed in the P type MOS transistor region (not particularly shown).

In the case of this modification, the silicon nitride film pattern 107 acts as a buffer material that attenuates the energy of the impurity 117 and the dose amount. Therefore, the impurities 117
In addition to the effects described above, the impurity diffusion layer can be accurately formed at a shallower position with a lower concentration when it is introduced into the silicon substrate 101.

In this modification, the N ^-- type diffusion layer 11 is used.
The 8, 119 and P ⁻ type diffusion layers can be formed under the same conditions as those described above in the present embodiment.

Further, in the case of the present embodiment, the silicon nitride film pattern 107 is left on the gate electrode layer 115 without being removed, and in this state, the surface (= main surface) of the silicon substrate 101 is ion-implanted. It is also possible to add a step of introducing impurities from the oblique direction.

In this case, first, the P-type MOS transistor region is covered with the photoresist film 116, and the N-type MOS transistor is formed.
The high-concentration impurity diffusion layers (= N ⁺ -type diffusion layers 111 and 112) and the low-concentration impurity diffusion layers (= N ⁻ -type diffusion layers 118 and 119) are sequentially formed in the transistor region by the procedure described above. Then, as shown in FIG.
01 with respect to the direction perpendicular to the surface (= main surface) of the impurity 122 from a diagonal direction having a predetermined inclination angle (eg, 25 degrees).
Is introduced into the low concentration impurity diffusion layer (= N ⁻ type diffusion layer 1
18, 119) with the opposite conductivity type, and
High concentration P ⁺ type diffusion layers 123 and 124 are formed.

In the P ⁺ type diffusion layers 123 and 124, for example, BF ₂ or the like is used as the impurity 122, and the energy (= accelerating voltage) is 50 kev and the dose amount is 3.0.
e13 (= 3.0 × 10 ¹⁵ ) (atoms / cm 2) or so under the high concentration P ⁺ type diffusion layers 123 and 124.
Introduced around and formed.

Next, similarly, the N-type MOS transistor region is covered with a photoresist film, and the silicon substrate 10 is formed.
Into the P-type MOS transistor region, the high-concentration impurity diffusion layer (= P ⁺ -type diffusion layer) and the low-concentration impurity diffusion layer (= P ⁻ -type diffusion layer) )
To form. After that, impurities are introduced from an oblique direction having a predetermined inclination angle with respect to the direction perpendicular to the surface (= main surface) of the silicon substrate 101, and the N ⁺ type diffusion layer is also provided around each P ⁻ type diffusion layer. Are formed (not particularly shown).

In this N ⁺ type diffusion layer, for example, arsenic (As) or the like is used as an impurity, and the energy (=
Acceleration voltage) 70 kev, dose amount 3.0e13 (=
Under the condition of about 3.0 × 10 ¹³ ) (atoms / cm ² ), they are formed by being introduced around each P ⁻ type diffusion layer.

In the case of this modification, an impurity diffusion layer of opposite conductivity type and high concentration is formed around the N-type and P-type low-concentration impurity diffusion layers, and the N-type and P-type low concentration impurity diffusion layers are formed. The spread of the impurity diffusion layer can be surely suppressed. Therefore,
By forming a low-concentration impurity diffusion layer locally at a shallow position, it is possible to prevent a short channel effect and the like, and it is possible to accurately cope with miniaturization.

In the case of this modification, the N ^-- type diffusion layer 11 is used.
8, 119 and P ⁻ -type diffusion layers 120 and 121 can be formed under the same conditions as those described in the present embodiment. (Second Embodiment) The present embodiment will be described below with reference to FIGS. In this embodiment, as an example, a method for manufacturing an N-type MOS transistor having an LDD structure will be described.

First, a silicon oxide film 202 is formed on the entire surface of the silicon substrate 201 to have a film thickness of about 2.5 nm. A part of the silicon oxide film 202 constitutes the gate oxide film of the MOS transistor. After that, a conductive film is formed over the silicon oxide film 202. This conductive film is, for example, in an N-type MOS transistor,
It is used as a material for forming the gate electrode layer. Here, a polycrystalline silicon film 203 is formed with a film thickness of about 200 nm as a conductive film by using a CVD method (= chemical vapor deposition method) or the like. Then, as shown in FIG. 6A, a photosensitive photoresist film 204 is applied and formed on the polycrystalline silicon film 203 to a film thickness of about 400 nm.

Next, the photoresist film 204 is subjected to an exposure process and a development process by using a lithography technique.
As shown in FIG. 6 (b), a predetermined dimension width (example: 0.33
A resist pattern 205 having a thickness of μm) is formed. afterwards,
Anisotropic dry etching is performed using the resist pattern 205 as a mask, and as shown in FIG. 6B, a pattern (= polycrystalline silicon film pattern 206 of a predetermined size and shape) is formed on the polycrystalline silicon film 203. ) Is formed.
Here, a pattern having a size and shape according to the resist pattern 205 is processed and formed on the polycrystalline silicon film 203 by etching.

After that, as an example, N-type MOS transistors are formed in predetermined regions on the silicon substrate 201. These N-type MOS transistors are so-called LOCOS or STI (Shallow Trench Isolator).
element isolation region (hereinafter, not particularly shown), etc.

Here, for the anisotropic dry etching technique, the RIE method or the like suitable for fine processing may be used.

Next, using the resist pattern 205 and the polycrystalline silicon film 206 as a mask, as shown in FIG. 6C, a predetermined impurity 207 is introduced by an ion implantation method to form each polycrystalline silicon film pattern. A high-concentration impurity diffusion layer, that is, the N ⁺ -type diffusion layer 20
8 and 209 are formed. Each of the N ⁺ type diffusion layers 208 and 209 constitutes a source region and a drain region in the N type MOS transistor.

In the present embodiment, as an example, N ⁺
For the type diffusion layers 208 and 209, arsenic (As) or the like is used as an impurity, and the energy (= accelerating voltage) is set to 50 ke.
v, the dose amount is 5.0e15 (= 5.0 × 10 ¹⁵ ) (a
Under the condition of about toms / cm ² ), it is formed by introducing into the positions corresponding to the source region and the drain region.

Next, the high-concentration impurity diffusion layers and the N ⁺ type diffusion layers 208 and 209 are subjected to so-called annealing treatment. Here, the silicon substrate 201 is subjected to heat treatment at about 1035 ° C. to activate the impurities in the N ⁺ type diffusion layers 208 and 209, and a source region and a drain region are formed in the N type MOS transistor region.

Next, as shown in FIG. 7A, the polycrystal silicon film pattern 206 is selectively and uniformly etched from both side surfaces by isotropic etching such as CDE. , A gate electrode layer 2 having a predetermined gate length
Form 10. Specifically, as an example, the polycrystalline silicon film pattern 206 is formed to have a thickness of about 90 nm from both side surfaces.
Etching about 180 nm each, 0.15μ
The gate electrode layer 210 is processed to have a width of about m.
To form.

In this case, in the CDE method, for example, CF ₄ / O ₂ / Cl ₂ is used as an etching gas, and the composition ratio of these gases is 7: 3: 1. The etching processing time is about 10 seconds.

In this case, the CDE method has a polycrystal silicon film / photoresist selection ratio (= etching rate ratio) of about 100 and the polycrystal silicon film 20.
Each etching condition is set so that the etching rate of No. 6 is about 540 nm / min. Also, at this time,
The selection ratio (= etching rate ratio) to the silicon oxide film 202 (= gate oxide film) can be about 50.

Here, the upper surface of the gate electrode layer 210 is
Since it is covered with the resist pattern 205, the etching acts in a uniform amount only from the direction of both side surfaces. Therefore, in the process of etching by the CDE method, the gate electrode layer 210 is formed by accurately processing only the pattern width and the dimension corresponding to the gate length without changing the film thickness of the polycrystalline silicon film pattern 206. You can Further, at this time, unlike anisotropic dry etching such as the RIE method, the silicon oxide film 202 (= gate oxide film) can be prevented from being adversely affected by physical composition destruction or the like. Does not lower the

In this embodiment, the polycrystalline silicon film 20 is used.
The resist pattern 205 is used as a mask material in the process of isotropic etching of 3. In this case, in the first embodiment, the silicon nitride film pattern 1 is used as the mask material.
The same effect as that when 07 is used can be obtained.

As described above, in the process of etching the polycrystalline silicon film pattern 206 using isotropic etching such as the CDE method, part of the resist pattern 205 is also etched at the same time, but the gate electrode layer 210 is not etched. There is no particular problem in dimensional accuracy.

Next, as shown in FIG. 7B, the resist pattern 205 is selectively removed. Here, a known ashing technique is used to selectively remove oxygen radicals (O ^* ) or the like by supplying them to the resist pattern 205.

Next, as shown in FIG. 7C, using the gate electrode layer 210 as a mask, an ion implantation method is used to remove the source region and the drain region at the positions on both sides of the gate electrode layer 210. Impurities 211 are introduced into the respective positions to form a low concentration N-type impurity diffusion layer, that is, an N ⁻ -type diffusion layer 212,
213 is formed. Here, the N ⁻ type diffusion layers 212 and 21
3 is an N ⁺ type diffusion layer 20 along the gate electrode layer 210.
8 and 209, it can be formed at a position near them.

Here, the N ⁻ type diffusion layers 212, 212 are used.
Is, for example, arsenic (As) is used as the impurity 211, the energy (= accelerating voltage) is 3 kev, and the dose is 1.0e15 (= 1.0 × 10 ¹⁵ ) (atoms / cm ² ).
It is formed in a predetermined region of the silicon substrate 201 under conditions of moderate degree.

As described above, the gate electrode layer 210 is selectively and uniformly etched from both side surfaces, and is formed at a predetermined position in the N-type MOS transistor region without causing a positional shift or the like. Has been done. Therefore, if impurities are introduced using the ion implantation method with the gate electrode layer 210 as a mask, a low concentration impurity diffusion layer,
That is, the N ⁻ type diffusion layers 212 and 213 can be accurately formed at predetermined positions.

Next, the low-concentration impurity diffusion layers and the N ^-- type diffusion layers 212 and 213 are subjected to so-called annealing treatment. Here, the silicon substrate 201 is heat-treated at about 850 ° C. to activate the impurities in the N ⁻ type diffusion layers 212 and 213, and an N type MOS transistor having a so-called LDD structure is formed on the silicon substrate 201. .

In this embodiment, similarly to (Embodiment 1), in the method of forming a low-concentration impurity diffusion layer,
It is also possible to change.

In the case of the present embodiment, the resist pattern 2
05 is not removed but left on the gate electrode layer 210,
In this state, the silicon substrate 20 is formed by the ion implantation method.
It is also possible to add a step of introducing impurities into the surface of 1 from an oblique direction.

In this case, first, in the N-type MOS transistor region, the high-concentration impurity diffusion layer (= N
^{The +} type diffusion layers 208 and 209) and the low-concentration impurity diffusion layers (= N ⁻ type diffusion layers 212 and 213) are sequentially formed. After that, the impurities 211 are introduced from an oblique direction having a predetermined inclination angle (eg, 25 degrees) with respect to the direction perpendicular to the surface (= main surface) of the silicon substrate 201, and the low-concentration impurity diffusion layer (= N ^- around type diffusion layer 212, 213),
A P ⁺ type diffusion layer of opposite conductivity type and high concentration is formed.

In this P ⁺ type diffusion layer, for example, BF ₂ or the like is used as the impurity 211, and this is used as energy (=
The acceleration voltage is 50 kev and the dose is 3e13 (= 3.
Under the condition of about 0 × 10 ¹³ ) (atoms / cm 2), they are formed by being introduced into positions corresponding to the source region and the drain region.

In the case of this modification, as described in (Embodiment 1), a low-concentration impurity diffusion layer can be locally formed. Therefore, in addition to the above-described effects, it is possible to further suppress the spread of the impurity diffusion layer, prevent the short channel effect, and the like, and accurately cope with miniaturization.

In this modification, the N ^-- type diffusion layer 21 is used.
2, 213 can be formed under the same conditions as those described in the present embodiment.

As described above, in the case of the present embodiment, it is possible to prevent the short channel effect and the like and to cope with the miniaturization with high accuracy in simplifying the process and manufacturing each MOS transistor. .

[0099]

According to the present invention, in the process of forming a semiconductor device, the impurity diffusion layer is formed into a high concentration impurity diffusion layer,
The low-concentration impurity diffusion layers are formed in this order. Therefore, it is possible to suppress the spread of the low-concentration impurity diffusion layer due to the high-temperature heat treatment, and manufacture the semiconductor device in response to miniaturization such as the short channel effect.

Further, in the process of forming the impurity diffusion layer in the order of high concentration and then low concentration, the pattern of the conductive film used as the mask material for introducing impurities by isotropic etching such as CDE method is set to a predetermined value. Is processed and formed with high dimensional accuracy. Therefore, by using this pattern as a mask, it is possible to accurately form a high-concentration, then low-concentration impurity diffusion layer at a predetermined position on the semiconductor substrate.

Further, at this time, if polycrystalline silicon or the like is used as the material of the conductive film, the pattern of the conductive film formed by isotropic etching such as the CDE method after the impurity diffusion layer is formed is misaligned. , And a gate electrode layer in which dimensional error and the like are suppressed. Therefore, the high-concentration and low-concentration impurity diffusion layers, and further the gate electrode layer can be accurately formed at predetermined positions.

According to the present invention, in particular, an MO of LDD structure
These effects can be obtained in manufacturing the S-type transistor.

As described above, according to the present invention, it is possible to manufacture a semiconductor device having high performance and high reliability in response to miniaturization.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 6 is a cross-sectional view of the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view of the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a cross-sectional view of a conventional semiconductor device manufacturing process.

FIG. 9 is a cross-sectional view of a conventional semiconductor device manufacturing process.

[Explanation of symbols]

101, 201, 301 ... Silicon substrates 102, 202, 302 ... Silicon oxide film (= gate oxide film) 103, 203, 303 ... Polycrystalline silicon film 104 ... Silicon nitride films 105, 109, 116, 204, 306, 314 ...
Photoresist film 106, 205, 304 ... Resist pattern 107 ... Silicon nitride film pattern 108, 206 ... Polycrystalline silicon film pattern 110, 117, 122, 207, 211, 307, 3
15 ... Impurities 111, 112, 208, 209, 316, 317 ...
N ⁺ type diffusion layers 113, 114, 123, 124, 318, 319 ...
P ⁺ type diffusion layers 115, 210, 305 ... Gate electrode layers 118, 119, 212, 213, 308, 309 ...
N ^- type diffusion layers 120, 121, 310, 311 ... P ^- type diffusion layer 312 ... Silicon oxide film 313 ... Silicon nitride film (= sidewall)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/43 29/78 F term (reference) 4M104 AA01 BB01 CC05 DD02 DD43 DD56 DD65 DD66 DD78 DD80 GG09 GG10 GG14 HH14 5F004 AA06 BA19 DA01 DA04 DA26 DB02 EB02 FA02 FA03 5F048 AA00 AA01 AA07 AC03 BA01 BB06 BB07 BC05 BC06 BD04 BG12 BG14 5F140 AA21 AA39 AB03 BA01 BF01 BF04 BG22 BG28 BG38 BG39 BG45 BG58 BH15 BH35 BK03 BK06 BK13 BK14 BK21 BK22 CB01 CB04 CB08

Claims (7)

[Claims] 1. A process of forming an insulating film on a semiconductor substrate, a process of forming a conductive film on the insulating film, a process of forming a mask pattern on the conductive film, and an etching process using the mask pattern. And forming a pattern on the conductive film, and using the pattern formed on the conductive film as a mask to introduce impurities into the semiconductor substrate to form a first impurity diffusion layer on the semiconductor substrate. A step of heat-treating the first impurity diffusion layer, a step of isotropically etching both side surfaces of the conductive film pattern, and a mask using the isotropically etched pattern,
Introducing an impurity of the same conductivity type as the impurity to form a second impurity diffusion layer having an impurity concentration lower than that of the first impurity diffusion layer on the semiconductor substrate; and the second impurity diffusion layer And a heat treatment step at a temperature lower than the heat treatment temperature of the first impurity diffusion layer. 2. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a conductive film on the gate insulating film, a step of forming a mask pattern on the conductive film, and using the mask pattern. Etching to form a pattern on the conductive film, and using the pattern of the conductive film as a mask to introduce impurities,
Forming a first impurity diffusion layer, heat treating the first impurity diffusion layer to form a source region and a drain region in the semiconductor substrate, and using the mask pattern, the conductive film Isotropically etching both side surfaces of the pattern to form a gate electrode layer on the gate insulating film, and using the gate electrode layer as a mask, impurities having the same conductivity type as the impurities are introduced, and the semiconductor A step of forming a second impurity diffusion layer having a lower impurity concentration than the first impurity diffusion layer on the substrate; and a temperature of heat treating the second impurity diffusion layer to the second impurity diffusion layer. And a step of performing a heat treatment at a low temperature. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film is a polycrystalline silicon film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the mask pattern formed on the conductive film is made of an insulating material. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the isotropic etching is performed by using a chemical dry etching method. 6. The first and second impurity diffusion layers are formed by using an ion implantation method.
Alternatively, the method of manufacturing the semiconductor device according to the item 2. 7. An impurity is introduced obliquely to the main surface of the semiconductor substrate, and a third conductivity type opposite to that of the second impurity diffusion layer is introduced around the second impurity diffusion layer. The impurity diffusion layer is formed, and the impurity diffusion layer is formed.
A method of manufacturing a semiconductor device according to item 1.