KR100268932B1 - Method for forming well of semiconductor device - Google Patents

Method for forming well of semiconductor device Download PDF

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KR100268932B1
KR100268932B1 KR1019970067042A KR19970067042A KR100268932B1 KR 100268932 B1 KR100268932 B1 KR 100268932B1 KR 1019970067042 A KR1019970067042 A KR 1019970067042A KR 19970067042 A KR19970067042 A KR 19970067042A KR 100268932 B1 KR100268932 B1 KR 100268932B1
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well
mask
layer
oxide film
substrate
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KR1019970067042A
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Korean (ko)
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KR19990048377A (en
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서정민
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for forming a well of a semiconductor device is provided to remove the setp height of n- and p-type wells in order to remove unbalance during process such as defocusing. CONSTITUTION: The method for forming the well of the semiconductor device includes following steps. At the first step, the first oxide layer is formed on a substrate(21) and the first mask layer is formed on a predetermined region of the first oxide layer. At the second step, the first heat oxidation layer is formed on the surface of the substrate on which the well of the first conductive type is formed by using the first mask layer as a mask. At the third step, an impurity ion of the first conductive type is injected on the front surface of the substrate by using the first mask layer as a mask to form a well of the first conductive type. At the forth step, the first mask is removed and an impurity ion of the second conductive type is injected on the front surface of the substrate by using the first heat oxidation layer as a mask to form a well of the second conductive type. The first heat oxidation layer and the first oxidation layer are removed to form the second oxidation layer on the front surface of the substrate. Then, the second mask layer is formed on the second oxidation layer of the first conductive type well. The second heat oxidation layer is formed on the surface of the substrate on which the well of the second conductive type is formed by using the second mask layer as a mask. At the last step, the second heat oxidation layer and the second mask layer are removed to form a device isolation layer(32) between the well of the first and second conductive types.

Description

반도체 소자의 웰 형성방법Well Forming Method of Semiconductor Device

본 발명은 반도체 소자의 제조 공정에 관한 것으로, 특히 N-웰(N-Well) 및 P-웰(P-Well)형성시 N-웰과 P-웰의 단차를 제거하는데 적당한 반도체 소자의 웰 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device. In particular, well formation of a semiconductor device suitable for removing a step difference between an N-well and a P-well during formation of an N-well and a P-well It is about a method.

일반적으로 반도체 소자의 특성을 향상시키기 위해 반도체 기판에 소자를 직접형성하지 않고, 기판내에 기판과 반대 도전형의 불순물을 이온 주입하여 웰을 형성한 후 소자를 형성한다.Generally, in order to improve characteristics of a semiconductor device, a device is formed after ion formation of a well by implanting impurities of opposite conductivity type to the substrate without directly forming the device on the semiconductor substrate.

이와 같은 반도체 소자의 n-웰과 p-웰을 형성하기 위해 두 번의 포토리소그래피(Photolithography) 공정을 실시한다.Two photolithography processes are performed to form the n-well and p-well of the semiconductor device.

이때 포토 공정이 두 번 진행되면서 미스얼라인(Misalign)이 발생하는 문제점을 가지고 있어 한 번의 포토리스그래피공정으로 n-웰과 p-웰을 형성하는 기술이 개발되었다.At this time, there is a problem in that misalignment occurs as the photo process is performed twice, and a technology of forming n-well and p-well in one photolithography process has been developed.

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 웰 형성방법을 설명하면 다음과 같다.Hereinafter, a well forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1f는 종래의 반도체 소자의 웰 형성방법을 나타낸 공정단면도이다.1A to 1F are process cross-sectional views showing a well forming method of a conventional semiconductor device.

도 1a에 도시한 바와같이 반도체 기판(11)표면에 제 1 산화막(12) 및 제 1 질화막을 차례로 형성하고, 포토리소그래피공정으로 상기 제 1 산화막(12)의 표면이 일부분 노출되도록 제 1 질화막을 선택적으로 제거하여 제 1 질화막 패턴(13)을 형성한다.As shown in FIG. 1A, the first oxide film 12 and the first nitride film are sequentially formed on the surface of the semiconductor substrate 11, and the first nitride film is partially exposed so as to partially expose the surface of the first oxide film 12 by a photolithography process. It is selectively removed to form the first nitride film pattern 13.

여기서 상기 반도체 기판(11)표면에 제 1 산화막(12)을 형성하는 이유는 제 1 질화막형성시에 제 1 질화막에 의한 반도체 기판(11) 표면의 결점결함이 유발되는 현상을 방지하기 위한 것으로, 상기 제 1 산화막(12)을 반도체 기판(11)과 제 1 질화막 사이에서 완충역할을 하는 스트레스 릴리프 옥사이드(Stress Relief Oxide)층이다.The reason for forming the first oxide film 12 on the surface of the semiconductor substrate 11 is to prevent a phenomenon in which defects on the surface of the semiconductor substrate 11 are caused by the first nitride film when the first nitride film is formed. The first oxide film 12 is a stress relief oxide layer that buffers the semiconductor substrate 11 and the first nitride film.

이어, 상기 패터닝된 제 1 질화막 패턴(13)을 마스크로 이용하여 반도체 기판(11)의 전면에 n형 불순물을 이온 주입하여 상기 반도체 기판(11)의 표면내에 n-웰(14)을 형성한다.Subsequently, n-type impurities are ion-implanted on the entire surface of the semiconductor substrate 11 using the patterned first nitride layer pattern 13 as a mask to form n-wells 14 in the surface of the semiconductor substrate 11. .

도 1b에 도시한 바와같이 상기 패터닝된 제 1 질화막 패턴(13)을 마스크로 이용한 열처리공정을 실시하여 상기 n-웰(14)이 형성된 반도체 기판(11)의 표면에 열산화막(12a)을 형성한다.As shown in FIG. 1B, a thermal oxide film 12a is formed on the surface of the semiconductor substrate 11 on which the n-well 14 is formed by performing a heat treatment process using the patterned first nitride film pattern 13 as a mask. do.

여기서 상기 열처리 공정대신에 LOCOS 공정을 실시할 수도 있다.Here, the LOCOS process may be performed instead of the heat treatment process.

도 1c에 도시한 바와같이 상기 제 1 질화막 패턴(13)을 제거하고, 상기 열산화막(12a)을 마스크로 이용하여 상기 반도체 기판(11)의 전면에 p형 불순물 이온 주입하여 반도체 기판(11)의 표면내에 p-웰(15)을 형성한다.As illustrated in FIG. 1C, the first nitride film pattern 13 is removed, and the p-type impurity ions are implanted into the entire surface of the semiconductor substrate 11 by using the thermal oxide film 12a as a mask. The p-well 15 is formed in the surface of the.

도 1d에 도시한 바와같이 상기 열산화막(12a) 및 제 1 산화막(12)을 제거하고, 상기 반도체 기판(11)의 전면에 제 2 산화막(16) 및 제 2 질화막을 차례로 형성한다.As shown in FIG. 1D, the thermal oxide film 12a and the first oxide film 12 are removed, and the second oxide film 16 and the second nitride film are sequentially formed on the entire surface of the semiconductor substrate 11.

이어, 포토리소그래피공정으로 상기 n-웰(14)과 p-웰(15)이 겹치는 부분이 오픈(Open)되도록 상기 제 2 질화막을 선택적으로 제거하여 제 2 질화막 패턴(17)을 형성한다.Subsequently, the second nitride layer is selectively removed to form a second nitride layer pattern 17 so that the portion where the n-well 14 and the p-well 15 overlap with each other is opened by a photolithography process.

도 1e에 도시한 바와같이 상기 제 2 질화막 패턴(17)을 마스크로 이용한 LOCOS(local oxidation of silicon) 공정을 실시하여 n-웰(14)과 p-웰(15)을 격리하는 소자 격리막(18)을 형성한다.As shown in FIG. 1E, a device isolation layer 18 isolating the n-well 14 and the p-well 15 by performing a local oxidation of silicon (LOCOS) process using the second nitride layer pattern 17 as a mask. ).

도 1f에 도시한 바와같이 상기 제 2 질화막 패턴(17) 및 제 2 산화막(16)을 제거함으로써 웰 형성공정으로 완료한다.As shown in Fig. 1F, the second nitride film pattern 17 and the second oxide film 16 are removed to complete the well forming process.

그러나 상기와 같은 종래의 반도체 소자의 웰 형성방법에 있어서 소자 격리막으로 격리된 n-웰과 p-웰의 단차에 의하여 커패시터 형성 뒤 n-웰 및 p-웰에 각종 콘택홀 형성시 디포커스등 포토노광상의 문제점이 있었다.However, in the conventional method of forming a well of a semiconductor device as described above, defocus and the like are formed when various contact holes are formed in n-well and p-well after capacitor formation by a step difference between n-well and p-well separated by device isolation layers. There was a problem with exposure.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 n-웰과 p-웰의 단차를 제거하여 이후공정의 진행을 원할하게 하도록한 반도체 소자의 웰 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a well of a semiconductor device in which a step between n-well and p-well is removed to facilitate the progress of a subsequent process.

도 1a 내지 도 1f는 종래의 반도체 소자의 웰 형성방법을 나타낸 공정단면도1A to 1F are process cross-sectional views showing a well forming method of a conventional semiconductor device

도 2a 내지 도 2h는 본 발명에 의한 반도체 소자의 웰 형성방법을 나타낸 공정단면도2A through 2H are cross-sectional views illustrating a method of forming a well of a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 제 1 산화막21 semiconductor substrate 22 first oxide film

23 : 제 1 질화막 패턴 24 : n-웰23: first nitride film pattern 24: n-well

25 : p-웰 26 : 제 2 산화막25: p-well 26: second oxide film

27 : 제 2 질화막 패턴 28 : 제 1 포토레지스트27: second nitride film pattern 28: first photoresist

29 : 제 2 산화막 30 : 제 3 질화막 패턴29: second oxide film 30: third nitride film pattern

31 : 제 2 포토레지스트 32 : 소자 격리막31 second photoresist 32 element isolation film

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 웰 형성방법은 기판상에 제 1 산화막을 형성하는 단계와, 상기 제 1 산화막상의 일정영역에 제 1 마스크층을 형성하는 단계와, 상기 제 1 마스크층을 마스크로 이용하여 기판의 전면에 제 1 도전형 불순물 이온을 주입하여 기판 표면내에 제 1 도전형 웰을 형성하는 단계와, 상기 제 1 마스크층을 마스크로 이용하여 제 1 도전형 웰이 형성된 기판의 표면에 제 1 열산화막을 형성하는 단계와, 상기 제 1 마스크층을 제거하고 상기 제 1 열산화막을 마스크로 이용하여 기판의 전면에 제 2 도전형 불순물 이온을 주입하여 기판의 표면내에 제 2 도전형 웰을 형성하는 단계와, 상기 제 1 열산화막 및 제 1 산화막을 제거하고 상기 기판의 전면에 제 2 산화막을 형성하는 단계와, 상기 제 1 도전형 웰의 제 2 산화막상에 제 2 마스크층을 형성하는 단계와, 상기 제 2 마스크층을 마스크로 이용하여 상기 제 2 도전형 웰의 기판 표면에 제 2 열산화막을 형성하는 단계와, 그리고 상기 제 2 열산화막 및 제 2 마스크층을 제거하고 상기 제 1 도전형 웰과 제 2 도전형 웰 사이에 소자 격리막을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The well forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a first oxide film on a substrate, forming a first mask layer in a predetermined region on the first oxide film, Implanting a first conductivity type impurity ion into the entire surface of the substrate using the first mask layer as a mask to form a first conductivity type well in the substrate surface, and using the first mask layer as a mask a first conductivity type Forming a first thermal oxide film on the surface of the substrate on which the well is formed, and removing the first mask layer and implanting second conductivity type impurity ions into the entire surface of the substrate using the first thermal oxide film as a mask. Forming a second conductivity type well in the surface, removing the first thermal oxide film and the first oxide film, and forming a second oxide film on the entire surface of the substrate; Forming a second mask layer on the second oxide film, forming a second thermal oxide film on the substrate surface of the second conductivity type well using the second mask layer as a mask, and the second thermal oxide film And removing the second mask layer and forming an isolation layer between the first conductivity type well and the second conductivity type well.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 웰 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a well forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2h는 본 발명에 의한 반도체 소자의 웰 형성방법을 나타낸 공정단면도이다.2A to 2H are cross-sectional views showing a well forming method of a semiconductor device according to the present invention.

도 2a에 도시한 바와같이 반도체 기판(21)상에 제 1 산화막(22)을 형성하고, 상기 제 1 산화막(22)상에 LPCVD법으로 제 1 질화막을 형성한 후 포토리소그래피공정으로 상기 제 1 산화막(22)의 표면이 일부분 노출되도록 제 1 질화막을 선택적으로 제거하여 제 1 질화막 패턴(23)을 형성한다.As shown in FIG. 2A, a first oxide film 22 is formed on the semiconductor substrate 21, and a first nitride film is formed on the first oxide film 22 by LPCVD. The first nitride film is selectively removed to partially expose the surface of the oxide film 22 to form the first nitride film pattern 23.

여기서 상기 제 1 산화막(22)은 산화막 생성로(Oxidation Furnace)내에 반도체 기판(21)을 넣고, 산소(O) 가스를 주입하면 반도체 기판(21)의 실리콘(Si)과 O2가 결합하여 실리콘 산화막인 SiO2층이 형성된다.Here, the first oxide film 22 is a semiconductor substrate 21 is placed in an oxide furnace, and when oxygen (O) gas is injected, silicon (Si) and O 2 of the semiconductor substrate 21 are bonded to silicon. An SiO 2 layer, which is an oxide film, is formed.

이어, 상기 제 1 질화막 패턴(23)을 마스크로 이용하여 반도체 기판(21)의 전면에 n형 불순물을 이온 주입하여 상기 반도체 기판(21)의 표면내에 n-웰(24)을 형성한다.Next, n-type impurities are ion-implanted on the entire surface of the semiconductor substrate 21 using the first nitride film pattern 23 as a mask to form n-wells 24 in the surface of the semiconductor substrate 21.

도 2b에 도시한 바와같이 상기 제 1 질화막 패턴(23)을 마스크로 이용한 열처리공정을 실시하여 상기 n-웰(24)이 형성된 반도체 기판(21)의 표면에 제 1 열산화막(22a)을 형성한다.As shown in FIG. 2B, the first thermal oxide film 22a is formed on the surface of the semiconductor substrate 21 on which the n-well 24 is formed by performing a heat treatment process using the first nitride film pattern 23 as a mask. do.

여기서 상기 열처리 공정대신에 선택적 산화공정(예를 들면 LOCOS 공정등)의 여러 공정을 사용할 수도 있다.Instead of the heat treatment process, various processes of a selective oxidation process (eg, LOCOS process, etc.) may be used.

도 2c에 도시한 바와같이 상기 제 1 질화막 패턴(23)을 제거하고, 상기 제 1 열산화막(22a)을 마스크로 이용하여 상기 반도체 기판(21)의 전면에 p형 불순물 이온 주입하여 반도체 기판(21)의 표면내에 p-웰(25)을 형성한다.As shown in FIG. 2C, the first nitride film pattern 23 is removed, and p-type impurity ions are implanted into the entire surface of the semiconductor substrate 21 by using the first thermal oxide film 22a as a mask. A p-well 25 is formed in the surface of 21).

도 2d에 도시한 바와같이 제 1 산화막(22) 및 제 1 열산화막(22a)을 제거하고, 상기 반도체 기판(21)의 전면에 제 2 산화막(26)을 형성하고, 상기 제 2 산화막(26)상에 제 2 질화막을 형성하고, 상기 제 2 질화막상에 제 1 포토레지스트(28)를 도포한 후, 노광 및 현상공정으로 상기 n-웰(24)의 반도체 기판(21)상에만 남도록 패터닝한다.As shown in FIG. 2D, the first oxide film 22 and the first thermal oxide film 22a are removed, a second oxide film 26 is formed on the entire surface of the semiconductor substrate 21, and the second oxide film 26 is formed. A second nitride film is formed on the second nitride film, and the first photoresist 28 is coated on the second nitride film, and then patterned to remain only on the semiconductor substrate 21 of the n-well 24 by an exposure and development process. do.

그리고 상기 패터닝된 제 1 포토레지스트(28)를 마스크로 이용하여 상기 제 2 질화막을 선택적으로 제거하여 제 2 질화막 패턴(27)을 형성한다.The second nitride layer is selectively removed by using the patterned first photoresist 28 as a mask to form a second nitride layer pattern 27.

도 2e에 도시한 바와같이 상기 제 1 포토레지스트(28)를 제거하고, 상기 제 2 질화막 패턴(27)을 마스크로 이용한 열처리 공정을 실시하여 상기 p-웰(25)의 반도체 기판(21) 표면에 제 2 열산화막(26a)을 형성한다.As shown in FIG. 2E, the first photoresist 28 is removed, and a heat treatment process using the second nitride film pattern 27 as a mask is performed to surface the semiconductor substrate 21 of the p-well 25. The second thermal oxide film 26a is formed in the film.

여기서 상기 열처리 공정대신에 선택적 산화공정(예를 들면 LOCOS 공정등)의 여러 공정을 사용할 수도 있다.Instead of the heat treatment process, various processes of a selective oxidation process (eg, LOCOS process, etc.) may be used.

도 2f에 도시한 바와같이 상기 제 2 산화막(26)과 제 2 질화막 패턴(27) 및 제 2 열산화막(26a)을 제거하고, 상기 반도체 기판(21)의 전면에 제 3 산화막(29) 및 제 3 질화막을 차례로 형성한다.As shown in FIG. 2F, the second oxide film 26, the second nitride film pattern 27, and the second thermal oxide film 26a are removed, and the third oxide film 29 and the front surface of the semiconductor substrate 21 are removed. The third nitride film is formed in sequence.

이어, 상기 제 3 질화막상에 제 2 포토레지스트(31)를 도포한 후, 노광 및 현상공정으로 격리영역이 형성될 영역을 정의한다.Subsequently, after the second photoresist 31 is coated on the third nitride film, a region where an isolation region is to be formed is defined by an exposure and development process.

그리고 상기 패터닝된 제 2 포토레지스트(31)를 마스크로 이용하여 상기 격리영역이 형성될 제 3 질화막을 선택적으로 제거하여 제 3 질화막 패턴(30)을 형성한다.The third nitride layer pattern 30 may be formed by selectively removing the third nitride layer in which the isolation region is to be formed using the patterned second photoresist 31 as a mask.

도 2g에 도시한 바와같이 상기 제 2 포토레지스트(31)를 제거하고, 상기 제 3 질화막 패턴(30)을 마스크로 이용하여 LOCOS공정을 실시하여 n-웰(24)과 p-웰(25)을 격리하는 소자 격리막(32)을 형성한다.As shown in FIG. 2G, the second photoresist 31 is removed, and a LOCOS process is performed using the third nitride film pattern 30 as a mask to perform n-well 24 and p-well 25. An isolation film 32 is formed to isolate the device.

도 2h에 도시한 바와같이 상기 제 3 질화막 패턴(30) 및 제 3 산화막(29)을 제거함으로써 웰 형성공정을 완료한다.As shown in FIG. 2H, the well forming process is completed by removing the third nitride film pattern 30 and the third oxide film 29.

이상에서 설명한 바와같이 본 발명에 의한 반도체 소자의 웰 형성방법에 있어서 n-웰과 p-웰의 단차를 제거함으로써 평탄화를 이룰 수 있기 때문에 이후 공정에서 각종 공정진행시 언발란스를 제거하여 디포커스등 포토공정상의 문제점들을 해결할 수 있는 효과가 있다.As described above, in the method for forming a well of a semiconductor device according to the present invention, the planarization can be achieved by removing the step difference between the n-well and the p-well. It is effective in solving process problems.

Claims (2)

기판상에 제 1 산화막을 형성하는 단계;Forming a first oxide film on the substrate; 상기 제 1 산화막상의 일정영역에 제 1 마스크층을 형성하는 단계;Forming a first mask layer in a predetermined region on the first oxide film; 상기 제 1 마스크층을 마스크로 이용하여 기판의 전면에 제 1 도전형 불순물 이온을 주입하여 기판 표면내에 제 1 도전형 웰을 형성하는 단계;Implanting first conductivity type impurity ions into the entire surface of the substrate using the first mask layer as a mask to form a first conductivity type well in the substrate surface; 상기 제 1 마스크층을 마스크로 이용하여 제 1 도전형 웰이 형성된 기판의 표면에 제 1 열산화막을 형성하는 단계;Forming a first thermal oxide film on a surface of a substrate on which a first conductivity type well is formed using the first mask layer as a mask; 상기 제 1 마스크층을 제거하고 상기 제 1 열산화막을 마스크로 이용하여 기판의 전면에 제 2 도전형 불순물 이온을 주입하여 기판의 표면내에 제 2 도전형 웰을 형성하는 단계;Removing the first mask layer and implanting second conductivity type impurity ions into the entire surface of the substrate using the first thermal oxide film as a mask to form a second conductivity type well in the surface of the substrate; 상기 제 1 열산화막 및 제 1 산화막을 제거하고 상기 기판의 전면에 제 2 산화막을 형성하는 단계;Removing the first thermal oxide film and the first oxide film and forming a second oxide film on the entire surface of the substrate; 상기 제 1 도전형 웰의 제 2 산화막상에 제 2 마스크층을 형성하는 단계;Forming a second mask layer on a second oxide film of the first conductivity type well; 상기 제 2 마스크층을 마스크로 이용하여 상기 제 2 도전형 웰의 기판 표면에 제 2 열산화막을 형성하는 단계;Forming a second thermal oxide film on a substrate surface of the second conductivity type well using the second mask layer as a mask; 상기 제 2 열산화막 및 제 2 마스크층을 제거하고 상기 제 1 도전형 웰과 제 2 도전형 웰 사이에 소자 격리막을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 웰 형성방법.And removing the second thermal oxide film and the second mask layer, and forming a device isolation layer between the first conductive well and the second conductive well. 제 1 항에 있어서,The method of claim 1, 상기 제 1, 제 2 마스크층은 질화막으로 형성함을 특징으로 하는 반도체 소자의 웰 형성방법.And the first and second mask layers are formed of a nitride film.
KR1019970067042A 1997-12-09 1997-12-09 Method for forming well of semiconductor device KR100268932B1 (en)

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