KR20010019155A - Method of forming wells in semiconductor device - Google Patents
Method of forming wells in semiconductor device Download PDFInfo
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- KR20010019155A KR20010019155A KR1019990035435A KR19990035435A KR20010019155A KR 20010019155 A KR20010019155 A KR 20010019155A KR 1019990035435 A KR1019990035435 A KR 1019990035435A KR 19990035435 A KR19990035435 A KR 19990035435A KR 20010019155 A KR20010019155 A KR 20010019155A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
Description
본 발명은 반도체장치의 웰 형성방법에 관한 것으로서, 특히, 각각 다른 도전형의 소자를 제조하기 위한 웰 형성공정 진행시 한 번의 포토마스크공정으로 각기 다른 도전형의 웰을 이온주입으로 형성하므로서 공정단순화 및 공정시간을 단축하도록 한 반도체장치의 자기정렬된 웰 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a well of a semiconductor device. In particular, the process simplifies the formation of wells of different conductivity types by ion implantation in a single photomask process during the well formation process for manufacturing devices of different conductivity types. And a method for forming a self-aligned well of a semiconductor device to shorten a process time.
일반적으로 CMOS 소자등의 반도체장치를 형성하기 위하여 각각 다른 도전형의 웰을 형성하여 소자를 제조하게 된다. 그러나, 이러한 웰들을 형성하기 위하여 복수의 포토마스크공정으로 각각 다른 도전형의 이온주입을 반도체기판에 실시하게 된다. 예를 들면, 제 1 포토마스킹 공정으로 제 1 이온주입 마스크를 형성한 다음 n형 이온주입으로 이온주입 마스크로 보호되지 않는 부위의 반도체기판 소정 부위에 n형 웰을 형성하고, 제 1 이온주입 마스크를 제거한 다음 제 2 포토마스킹 공정으로 제 2 이온주입 마스크를 형성한 다음 p형 이온주입을 반도체기판에 실시하여 p형 웰을 형성하게 된다.In general, in order to form semiconductor devices such as CMOS devices, devices of different conductivity types are formed to manufacture devices. However, in order to form such wells, ion implantation of different conductivity types is performed on a semiconductor substrate by a plurality of photomask processes. For example, a first ion implantation mask is formed by a first photomasking process, and then an n-type well is formed on a predetermined portion of a semiconductor substrate at a portion that is not protected by an ion implantation mask by an n-type ion implantation, and a first ion implantation mask. After removing the second ion implantation mask is formed by a second photomasking process, p-type implantation is performed on the semiconductor substrate to form a p-type well.
따라서, 소자제조를 위한 기본 공정으로 웰 형성공정은 각각 상이한 도전형의 웰을 형성하기 위하여 두 번에 걸친 포토마스킹 공정을 진행하게 된다.Therefore, as a basic process for fabricating a device, the well forming process performs two times of photomasking processes to form wells of different conductivity types.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 웰 형성방법 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a well of a semiconductor device according to the related art.
도 1a를 참조하면, 제 1 도전형 실리콘 기판인 p형의 반도체기판(10) 표면의 소정 부분에 LOCOS(Local Oxidation of Silicon), 트렌치 격리(shallow trench isolation) 등의 통상적인 선택산화방법에 의해 필드산화막(11)을 형성하여 소자의 활성영역 및 필드영역을 한정한다.Referring to FIG. 1A, a predetermined portion of the surface of a p-type semiconductor substrate 10, which is a first conductivity type silicon substrate, is formed by a conventional selective oxidation method such as LOCOS (local oxide of silicon), trench trench isolation, or the like. A field oxide film 11 is formed to define an active region and a field region of the device.
그리고, 제 1 도전형 웰인 p형 웰을 형성하기 위하여 p형 웰 형성지역을 노출시키는 제 1 이온주입 마스크(12)를 포토레지스트를 이용하여 형성한다. 이때, 제 1 이온주입 마스크는 소정의 두께로 기판(10) 표면에 도포한 다음 노광 및 현상공정으로 형성한다.Then, a first ion implantation mask 12 exposing the p-type well formation region is formed using a photoresist to form a p-type well that is a first conductivity type well. In this case, the first ion implantation mask is applied to the surface of the substrate 10 to a predetermined thickness, and then formed by an exposure and development process.
따라서, p형 웰 형성지역의 기판(10) 표면이 노출된다.Thus, the surface of the substrate 10 in the p-type well formation region is exposed.
도 1b를 참조하면, 반도체기판(10)의 전면에 p형 이온주입을 실시하여 제 1 이온주입 마스크(12)로 보호되지 않는 부위의 기판(10) 소정 깊이에 p형 이온 매몰층(13)을 형성한다. 이때, 이온 주입 에너지는 이온 주입되는 이온 들이 제 1 이온주입 마스크(12)를 투과하지 못할 정도의 에너지로 실시한다.Referring to FIG. 1B, a p-type ion buried layer 13 is formed at a predetermined depth of a substrate 10 at a portion which is not protected by the first ion implantation mask 12 by performing p-type ion implantation on the entire surface of the semiconductor substrate 10. To form. In this case, the ion implantation energy is performed at such a degree that the ions implanted with the ions cannot penetrate the first ion implantation mask 12.
도 1c를 참조하면, 제 1 이온주입 마스크를 산소 애슁(O2ashing) 등으로 제거한 다음, 다시 기판(10)의 전면에 포토레지스트를 도포한 다음, 제 2 도전형 웰인 n형 웰이 형성될 지역을 노출시키는 제 2 이온주입 마스크(14)를 노광 및 현상으로 포토레지스트패턴(14)을 잔류시켜 형성한다.Referring to FIG. 1C, the first ion implantation mask is removed by oxygen ashing (O 2 ashing) or the like, and then photoresist is applied to the entire surface of the substrate 10, and then an n-type well which is a second conductivity type well is formed. The second ion implantation mask 14 exposing the region is formed by remaining the photoresist pattern 14 by exposure and development.
도 1d를 참조하면, 반도체기판(10)의 전면에 n형 이온주입을 실시하여 제 2 이온주입 마스크(114)로 보호되지 않는 부위의 기판(10) 소정 깊이에 n형 이온 매몰층(15)을 형성한다. 이때, 이온 주입 에너지는 이온 주입되는 n형 이온 들이 제 2 이온주입 마스크(14)를 투과하지 못할 정도의 에너지로 실시한다.Referring to FIG. 1D, an n-type ion buried layer 15 is formed at a predetermined depth of a substrate 10 at a portion which is not protected by the second ion implantation mask 114 by performing n-type ion implantation on the entire surface of the semiconductor substrate 10. To form. At this time, the ion implantation energy is performed at such a level that the n-type ions implanted with the ion cannot be transmitted through the second ion implantation mask 14.
따라서, 기판(10)의 소정 부위에 각각 p형 이온 매몰층(13)과 n형 이온 매몰층(15)이 형성되었다.Accordingly, the p-type ion buried layer 13 and the n-type ion buried layer 15 are formed at predetermined portions of the substrate 10, respectively.
이후, 도시되지는 않았지만, 제 2 이온주입 마스크(14)를 제거한 다음, 어닐링(annealing) 등의 적절한 열공정을 기판(10)에 실시하여 이온 매몰층(13,15)의 각기 다른 불순물 이온이 확산되도록 하여 제 1 도전형 웰인 p형 웰과 제 2 도전형 웰인 n형 웰 등을 형성한다.Subsequently, although not shown, the second ion implantation mask 14 is removed, and then an appropriate thermal process such as annealing is performed on the substrate 10 so that different impurity ions of the ion buried layers 13 and 15 are removed. The diffusion is performed to form a p-type well as a first conductivity type well and an n-type well as a second conductivity type well.
그러나, 상술한 바와 같이 종래 기술에서는 NMOS 소자와 PMOS 소자 등을 형성하기 위한 p형 웰과 n형 웰을 별도의 마스킹 공정을 실시하여 형성하여야 하므로 공정시간, 공정 단순화 및 원가 절감에 있어서 불리한 문제점이 있다.However, as described above, since the p-type well and the n-type well for forming the NMOS device and the PMOS device must be formed by performing a separate masking process, disadvantageous problems in process time, process simplification, and cost reduction are caused. have.
따라서, 본 발명의 목적은 한 번의 포토마스크공정으로 각기 다른 도전형의 웰을 이온주입으로 형성하므로서 공정단순화, 공정시간을 단축하고 원가를 절감하도록 한 반도체장치의 자기정렬된 웰 형성방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for forming a self-aligned well of a semiconductor device, which can simplify the process, reduce the process time, and reduce the cost by forming ion-implanted wells in a single photomask process. have.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 웰 형성방법은 활성영역 및 필드영역을 정의하는 필드절연막이 형성된 제 1 도전형 기판의 제 2 도전형 웰 형성영역을 노출시키고 제 1 도전형 웰 형성영역을 덮는 이온주입 마스크를 기판 소정부위에 형성하는 단계와, 기판에 제 1 도전형 이온주입을 실시하여 이온주입 마스크 하부에 위치한 제 1 도전형 웰 형성영역의 기판 부위에 제 1 도전형 이온 매몰층을 형성하는 단계와, 이온주입 마스크를 다시 이용하여 기판에 제 2 도전형 이온주입을 실시하여 제 2 도전형 웰 형성영역에 제 2 도전형 이온 매몰층을 형성하는 단계와, 제 1 및 제 2 도전형 이온 매몰층의 이온들을 확산시켜 각각 제 1 도전형 웰과 제 2 도전형 웰을 형성하는 단계를 포함하여 이루어진다.A well forming method of a semiconductor device according to the present invention for achieving the above object exposes a second conductivity type well forming region of a first conductivity type substrate on which a field insulating film defining an active region and a field region is formed and exposes the first conductivity type well. Forming an ion implantation mask covering a formation region on a predetermined portion of the substrate; and applying a first conductivity type ion implantation on the substrate to the substrate portion of the first conductivity type well formation region under the ion implantation mask. Forming a buried layer, forming a second conductive ion buried layer in a second conductive well forming region by performing second conductive ion implantation on a substrate again using an ion implantation mask; Diffusing ions of the second conductive ion buried layer to form a first conductive well and a second conductive well, respectively.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 웰 형성방법 공정단면도1A to 1D are cross-sectional views of a well forming method of a semiconductor device according to the related art.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 웰 형성방법 공정단면도2A to 2C are cross-sectional views of a well forming method of a semiconductor device according to the present invention.
본 발명은 먼저 종래의 기술에서의 n웰 형성용 포토마스킹 공정을 실시하여 이온주입 마스크를 형성한 다음 이를 이용하여 p웰 형성용 이온주입을 형성한다. 즉, 이온주입 마스크를 종래기술에서 보다 두껍게 형성한 다음 이온주입 에너지를 높게하여 이온주입 프로파일의 최고 농도점이 기판 깊숙히 형성되도록 한다. 따라서, n웰 형성영역에 형성되는 p형 이온매몰층은 실리콘기판 깊숙히 위치하게 되어 p형 실리콘기판의 이온들에 더해져 n웰의 농도에 영향을 끼치지 않는다. 또한, n웰 형성용 이온주입 마스크 하부에 형성되는 p웰 형성용 이온매몰층은 적절한 기판 깊이에 위치하게 되어 자동적으로 정렬된다.The present invention first performs an n well forming photomasking process in the prior art to form an ion implantation mask, and then forms an ion implantation for p well formation using the same. That is, the ion implantation mask is formed thicker than in the prior art and then the ion implantation energy is made high so that the highest concentration point of the ion implantation profile is formed deep into the substrate. Therefore, the p-type ion buried layer formed in the n-well formation region is located deep in the silicon substrate and is added to the ions of the p-type silicon substrate so as not to affect the concentration of the n well. In addition, the p well forming ion buried layer formed under the n well forming ion implantation mask is positioned at an appropriate substrate depth and is automatically aligned.
그리고, 동일한 이온주입 마스크를 이용하여 n웰 이온주입을 기판에 실시하여 n형 이온매몰층을 n웰 형성영역에 형성하고 적절한 확산공정을 실시하여 각각 n웰 및 p웰을 형성한다.Then, n well ion implantation is performed on the substrate using the same ion implantation mask to form an n-type ion buried layer in an n well formation region and an appropriate diffusion process to form n wells and p wells, respectively.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 웰 형성방법 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a well in a semiconductor device according to the present invention.
도 2a를 참조하면, 제 1 도전형 실리콘 기판인 p형의 반도체기판(20) 표면의 소정 부분에 LOCOS(Local Oxidation of Silicon), 트렌치 격리(shallow trench isolation) 등의 통상적인 선택산화방법에 의해 필드산화막(21)을 형성하여 소자의 활성영역 및 필드영역을 한정한다.Referring to FIG. 2A, a predetermined portion of the surface of a p-type semiconductor substrate 20, which is a first conductivity type silicon substrate, is formed by a conventional selective oxidation method such as LOCOS (local oxide of silicon), trench trench isolation, or the like. A field oxide film 21 is formed to define the active and field regions of the device.
그리고, 제 1 도전형 웰인 p형 웰 및 제 2 도전형 웰인 n형 을 형성하기 위하여 n형 웰 형성지역을 노출시키는 이온주입 마스크(22)를 포토레지스트를 이용하여 형성한다. 이때, 이온주입 마스크(22)는 종래 기술에서 보다 두껍게 형성하는데, 이는 기판(20) 표면에 포토레지스트를 도포한 다음 n웰 형성영역을 노출시키도록 하는 노광 및 현상공정을 도포된 포토레지스트에 실시하여 p웰 형성영역을 덮는 포토레지스트패턴(22)을 형성하여 만든다. 또한, 형성되는 이온주입 마스크(22)의 두께는 이온주입 에너지를 고려하여 p형 이온주입시 기판에 형성되는 p형 이온매몰층의 농도 프로파일 최고점이 p형 웰을 형성하기 적절한 위치에 오도록 하여 결정한다. 즉, 종래 기술에서 보다 두껍게 형성하게 된다.In order to form the p-type well as the first conductivity type well and the n-type as the second conductivity type well, an ion implantation mask 22 exposing the n-type well formation region is formed using a photoresist. At this time, the ion implantation mask 22 is formed thicker than in the prior art, and the photoresist is applied to the surface of the substrate 20 and then exposed and developed to expose the n well forming region to the coated photoresist. The photoresist pattern 22 is formed to cover the p well forming region. In addition, the thickness of the ion implantation mask 22 to be formed is determined in consideration of the ion implantation energy so that the peak of the concentration profile of the p-type ion buried layer formed on the substrate at the time of p-type ion implantation is at a suitable position for forming the p-type well. do. That is, it is formed thicker than in the prior art.
따라서, n형 웰 형성지역의 기판(20) 표면이 노출된다.Thus, the surface of the substrate 20 in the n-type well formation region is exposed.
도 2b를 참조하면, 반도체기판(20)의 전면에 p형 이온주입을 실시하여 이온주입 마스크(22)로 보호되는 부위의 기판(20) 소정 깊이에 제 1 p형 이온 매몰층(230)을 형성하고, 동시에, 노출된 기판(20) 부위인 n웰 형성영역에서는 제 2 p형 이온매몰층(231)이 수직적으로 n웰 영역을 벗어난 기판 깊숙한 곳에 위치하도록 한다. 이때, 이온 주입 에너지는 이온 주입되는 이온 들이 이온주입 마스크(22)를 투과하도록 고 에너지로 실시한다. 따라서, n웰 영역에 하부에 형성되는 제 2 p형 이온 매몰층(231)은 p형 기판(20)의 이온들과 합해져서 이후 형성되는 n웰 영역에 영향을 주지 않는다.Referring to FIG. 2B, the first p-type ion buried layer 230 is formed at a predetermined depth of the substrate 20 at a portion protected by the ion implantation mask 22 by performing p-type ion implantation on the entire surface of the semiconductor substrate 20. At the same time, the second p-type ion buried layer 231 is located deep in the substrate, which is vertically out of the n well region, in the n well formation region, which is an exposed portion of the substrate 20. In this case, the ion implantation energy is performed at high energy so that the ions implanted with the ion pass through the ion implantation mask 22. Therefore, the second p-type ion buried layer 231 formed below the n-well region is combined with the ions of the p-type substrate 20 so as not to affect the n-well region formed later.
도 2c를 참조하면, 노출된 기판(20)의 전면에 제 2 도전형인 n형 이온주입을 실시하여 노출된 기판(20)의 적절한 깊이에 n형 이온 매몰층(24)을 형성한다. 이때, 이온주입 에너지는 n형 이온들이 이온주입 마스크(22)를 투과하지 않도록 결정한다.Referring to FIG. 2C, the n-type ion buried layer 24 is formed at an appropriate depth of the exposed substrate 20 by performing an n-type ion implantation, which is the second conductivity type, on the entire surface of the exposed substrate 20. At this time, the ion implantation energy is determined so that the n-type ions do not penetrate the ion implantation mask 22.
따라서, 기판(20)의 소정 부위에 각각 제 1 p형 이온 매몰층(230)과 n형 이온 매몰층(24)이 형성되었다.Accordingly, the first p-type ion buried layer 230 and the n-type ion buried layer 24 are formed at predetermined portions of the substrate 20, respectively.
이후, 도시되지는 않았지만, 이온주입 마스크(22)를 제거한 다음, 어닐링(annealing) 등의 적절한 열공정을 기판(20)에 실시하여 이온 매몰층(230,24)의 각기 다른 불순물 이온이 확산되도록 하여 제 1 도전형 웰인 p형 웰과 제 2 도전형 웰인 n형 웰 등을 형성한다.Thereafter, although not shown, the ion implantation mask 22 is removed, and then an appropriate thermal process such as annealing is performed on the substrate 20 so that different impurity ions of the ion buried layers 230 and 24 are diffused. P-type wells, which are the first conductivity type wells, and n-type wells, which are the second conductivity type wells, are formed.
상술한 본 발명의 실시예에서는 제 1 도전형과 제 2 도전형을 서로 바꾸어 실시할 수도 있다. 즉, n형 기판 또는 n형 웰에 p형 웰 영역을 노출시키는 이온주입 마스크를 형성한 다음, n형 이온주입을 고에너지로 실시하여 이온주입 마스크 하단의 기판 소정 부위에 n형 이온 매몰층을 형성한 후, 동일한 이온주입 마스크를 이용하여 p형 이온주입을 실시하여 p형 이온 매몰층을 형성한 다음, 적절한 확산공정을 실시하여 각각 다른 도전형의 웰을 형성할 수도 있다.In the above-described embodiment of the present invention, the first conductivity type and the second conductivity type may be interchanged. That is, after forming an ion implantation mask exposing a p-type well region on an n-type substrate or an n-type well, and performing n-type ion implantation at high energy, an n-type ion buried layer is formed on a predetermined portion of the substrate under the ion implantation mask. After the formation, the p-type ion implantation layer may be formed using the same ion implantation mask to form a p-type implant buried layer, and then an appropriate diffusion process may be performed to form wells of different conductivity types.
따라서, 본 발명은 한 번의 포토마스크공정으로 각기 다른 도전형의 웰을 이온주입으로 형성하므로서 공정단순화, 공정시간을 단축하고 원가를 절감하는 장점이 있다.Therefore, the present invention has the advantage of simplifying the process, shortening the process time and reducing the cost by forming ion-implanted wells of different conductivity types in one photomask process.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990035435A KR20010019155A (en) | 1999-08-25 | 1999-08-25 | Method of forming wells in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990035435A KR20010019155A (en) | 1999-08-25 | 1999-08-25 | Method of forming wells in semiconductor device |
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| KR20010019155A true KR20010019155A (en) | 2001-03-15 |
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| KR1019990035435A KR20010019155A (en) | 1999-08-25 | 1999-08-25 | Method of forming wells in semiconductor device |
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1999
- 1999-08-25 KR KR1019990035435A patent/KR20010019155A/en not_active Application Discontinuation
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