KR930020576A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR930020576A
KR930020576A KR1019920003761A KR920003761A KR930020576A KR 930020576 A KR930020576 A KR 930020576A KR 1019920003761 A KR1019920003761 A KR 1019920003761A KR 920003761 A KR920003761 A KR 920003761A KR 930020576 A KR930020576 A KR 930020576A
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South Korea
Prior art keywords
photoresist
pattern
film
forming
device isolation
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KR1019920003761A
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Korean (ko)
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KR0183047B1 (en
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김학력
최용근
황준
박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019920003761A priority Critical patent/KR0183047B1/en
Publication of KR930020576A publication Critical patent/KR930020576A/en
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Publication of KR0183047B1 publication Critical patent/KR0183047B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로 제1감광막 마스크를 이용하여 다수의 콘택홀을 형성하고, 제1감광막을 포함하는 전체구조에 다수의 콘택홀중 일부 콘택홀을 노출시킨 제2감광막 마스크를 형성하여 일부의 예정된 콘택홀에 불순물을 이온주입하고, 상기 제1감광막 마스크와 제2감광막 마스크를 동시에 제거한 다음, 콘택을 형성하므로써 공정을 간단히 할수있는 반도체 소자의 제조방법에 관하여 기술한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, wherein a plurality of contact holes are formed using a first photoresist mask, and a second photoresist mask is formed by exposing a part of the plurality of contact holes to a whole structure including the first photoresist film. The present invention relates to a method for manufacturing a semiconductor device which can simplify the process by forming a contact by simultaneously implanting impurities into some predetermined contact holes, simultaneously removing the first photoresist mask and the second photoresist mask, and forming a contact.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도 내지 제1c도는 본 발명의 제1실시예에 의한 반도체 소자의 콘택홀에 선택적으로 불순물을 이온주입한 후 콘택을 제조하는 단계를 도시한 단면도.1A to 1C are cross-sectional views illustrating steps of fabricating a contact after selectively implanting impurities into a contact hole of a semiconductor device according to a first embodiment of the present invention.

제2a도 내지 제2c도는 본 발명의 제3실시예에 의한 CMOS의 P-웰 영역에만 불순물을 이온주입한후 필드산화막을 형성하는 단계를 도시한 단면도.2A to 2C are cross-sectional views illustrating a step of forming a field oxide film after ion implantation of impurities into a P-well region of a CMOS according to a third embodiment of the present invention.

Claims (3)

반도체 소자의 제조방법에 있어서, 반도체 기판상에 절연층을 증착하고, 상기 절연층 상부에 제1감광막을 도포한 후, 예정된 부분에 다수의 콘택홀을 형성하기 위하여 콘택홀 마스크용 제1감광막 패턴을 형성하는 단계와, 상기 제1감광막 패턴 하부의 노출된 절연층을 식각하여 반도체 기판이 노출된 다수의 콘택홀을 형성하고, 상기 다수의 콘택홀 및 상기 제1감광막 패턴 상부에 전반적으로 제2감광막을 도포한후, 다수의 콘택홀중에서 예정된 일부 콘택홀에 불순물 이온을 주입하기 위하여 제2감광막 패턴을 형성하는 단계와, 상기 제2감광막 패턴하부의 노출된 콘택홀에 불순물을 이온주입한 후에 상기 제1감광막 패턴과 상기 제2감광막 패턴을 동시에 제거하는 단계와, 어닐링공정을 실시하여 상기 콘택홀에 주입된 불순물 이온을 반도체 기판으로 확산시켜 불순물 확산영역을 형성하고, 전체구조의 상부에 도전층을 증착하여 패턴공정으로 도전층 패턴을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.In the method of manufacturing a semiconductor device, after depositing an insulating layer on a semiconductor substrate, applying a first photosensitive film on the insulating layer, the first photosensitive film pattern for a contact hole mask to form a plurality of contact holes in a predetermined portion Forming a plurality of contact holes through which the semiconductor substrate is exposed by etching the exposed insulating layer under the first photoresist pattern, and forming a plurality of contact holes and the second photoresist on the first photoresist pattern. After applying the photoresist film, forming a second photoresist film pattern for implanting impurity ions into a predetermined contact hole among a plurality of contact holes, and implanting impurities into the exposed contact hole under the second photoresist film pattern. Simultaneously removing the first photoresist layer pattern and the second photoresist layer pattern, and performing an annealing process to expand impurity ions implanted into the contact hole into a semiconductor substrate. Forming an impurity diffusion region by acid, and depositing a conductive layer on top of the entire structure to form a conductive layer pattern by a pattern process. 제1항에 있어서, 상기 절연층은 층간 절연층, 로드산화막 및 절연막으로 적층되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the insulating layer is laminated with an interlayer insulating layer, a rod oxide film, and an insulating film. 반도체 소자의 제조방법에 있어서, P-웰 및 N-웰이 형성된 반도체 기판상에 산화막 및 질화막을 형성한 후에 상기 질화막상에 제1감광막을 도포한 다음, 소자분리 마스크용 제1감광막 패턴을 형성하는 단계와, 상기 소자분리 마스크용 제1감광막 패턴하부의 노출된 질화막을 식각하고, 제1감광막 패턴을 포함하는 전체구조상에 제2감광막을 도포한후, P-웰 상부의 제2감광막이 제거된 제2감광막 패턴을 형성하는 단계와, 소자분리 기능을 향상시키는 P+ 불순물을 P-웰의 소자분리 영역에 주입한 다음, 상기 소자분리 마스크용 제1감광막 패턴과 제2감광막 패턴을 동시에 제거하는 단계와, 산화공정으로 P-웰 및 N-웰의 소자분리 영역에 각각의 필드산화막을 형성하는 단계로 이루어져 상기P-웰에 형성된 필드산화막 저부에 P+영역을 형성하는 것을 특징으로 하는 반도체 소자의 제조방법In the method of manufacturing a semiconductor device, after forming an oxide film and a nitride film on a semiconductor substrate formed with P-wells and N-wells, a first photosensitive film is coated on the nitride film, and then a first photosensitive film pattern for device isolation mask is formed. And etching the exposed nitride film under the first photoresist pattern for the device isolation mask, applying a second photoresist on the entire structure including the first photoresist pattern, and then removing the second photoresist over the P-well. Forming a second photoresist pattern, implanting P + impurities to improve device isolation, into the device isolation region of the P-well, and simultaneously removing the first photoresist pattern and the second photoresist pattern for the device isolation mask. And forming a respective field oxide film in the device isolation regions of the P-well and the N-well by an oxidation process to form a P + region at the bottom of the field oxide film formed in the P-well. The method of producing a semiconductor device ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920003761A 1992-03-07 1992-03-07 Manufacturing method of semiconductor device KR0183047B1 (en)

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KR1019920003761A KR0183047B1 (en) 1992-03-07 1992-03-07 Manufacturing method of semiconductor device

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KR1019920003761A KR0183047B1 (en) 1992-03-07 1992-03-07 Manufacturing method of semiconductor device

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KR930020576A true KR930020576A (en) 1993-10-20
KR0183047B1 KR0183047B1 (en) 1999-04-15

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KR100443079B1 (en) * 2002-08-19 2004-08-02 삼성전자주식회사 Method of manufacturing semiconductor device

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