CN111430307B - Well preparation method and well injection photomask set of semiconductor integrated device - Google Patents

Well preparation method and well injection photomask set of semiconductor integrated device Download PDF

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CN111430307B
CN111430307B CN201911303991.XA CN201911303991A CN111430307B CN 111430307 B CN111430307 B CN 111430307B CN 201911303991 A CN201911303991 A CN 201911303991A CN 111430307 B CN111430307 B CN 111430307B
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well
mask layer
ion implantation
mask
device region
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CN111430307A (en
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蒲甜松
李庆民
陈信全
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a well preparation method and a well injection photomask group of a semiconductor integrated device, which can utilize a special photomask to finally realize that different wells are formed in different device areas at one time, for example, a special photomask is utilized to finally manufacture wells required by each device area in different device areas with different required well depths, such as a medium-voltage device area, a low-voltage device area and the like, or a special photomask is utilized to manufacture wells required by each device area in different device areas with the same required well depths, such as a low-voltage device area, a standard-voltage device area, a storage device area and the like. Further, after wells of different well depths are fabricated in different device regions using one mask, wells of the same well depth may be fabricated in sub-device regions of a device region using another mask. The technical scheme of the invention can save the photomask, simplify the process flow and greatly save the manufacturing cost of the device.

Description

Well preparation method and well injection photomask set of semiconductor integrated device
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a well preparation method and a well injection photomask set of a semiconductor integrated device.
Background
A conventional CMOS integrated circuit process flow generally includes a Medium Voltage (MV) device, a Low Voltage (LV) device, a standard voltage (RV) device, and a memory device (e.g., SRAM), and a semiconductor manufacturing process at present needs to form a corresponding well in a specific device region of a substrate through corresponding photolithography and ion implantation processes for different devices, so as to finally form a required device in the specific device region. For example, when each device includes NMOS and PMOS transistors, the process for fabricating such CMOS devices includes a P-well CMOS process, an N-well CMOS process to fabricate N-wells and P-wells, before the corresponding PMOS and NMOS transistors can be fabricated in N, P wells, respectively. Therefore, when a Medium Voltage (MV) device, a Low Voltage (LV) device, a standard voltage (RV) device, and an N-well and a P-well of a memory device (e.g., SRAM) of a standard low power platform need to be formed, eight different well ion implantations need to be performed to complete the fabrication of the N-well and the P-well of the Medium Voltage (MV) device, the N-well and the P-well of the Low Voltage (LV) device, the N-well and the P-well of the standard voltage (RV) device, and the N-well and the P-well of the memory device, respectively, wherein, referring to fig. 1A to 1D, a specific process of an N-well CMOS process for forming the Medium Voltage (MV) device, the Low Voltage (LV) device, the standard voltage (RV) device, and the memory device of the standard low power platform includes:
referring to fig. 1A, after photo-etching a photoresist PR1 on a substrate using an N-well (MVN well) Mask (Mask) of a medium voltage device, performing corresponding ion implantation using the photo-etched photoresist PR1 as a Mask, and then removing the photoresist PR1 to form an N-well (MVN) of the medium voltage device;
referring to fig. 1B, after photo-etching the photoresist PR2 on the substrate using an N-well (LVN well) mask of the low voltage device, performing corresponding ion implantation using the photo-etched photoresist PR2 as a mask, and then removing the photoresist PR2 to form an N-well (LVN) of the low voltage device;
then, referring to fig. 1C, after photo-etching the photoresist PR3 on the substrate using an N-well (RVN well) mask of the standard voltage device, performing corresponding ion implantation using the photo-etched photoresist PR3 as a mask, and then removing the photoresist PR3 to form an N-well (RVN) of the standard voltage device;
referring to fig. 1D, after photo-etching the photoresist PR4 on the substrate using a N-well (NSRAM well) mask of the memory device, corresponding ion implantation is performed using the photo-etched photoresist PR4 as a mask, and then the photoresist PR4 is removed to form an N-well (NSRAM) of the memory device.
As can be seen from the above process, 4 photomasks are required to form each N-well of a standard low power platform, and another 4 photomasks are required to form each P-well of the standard low power platform similar to the above N-well formation process. Thus, a total of 8 photomasks are required to form each of the N-well and P-well of a standard low power platform. However, the processes of photolithography, ion implantation, and photoresist stripping in the process of fabricating CMOS devices have a very large proportion, and as the process is further developed, the cost for fabricating the mask will be a large expenditure. Therefore, how to reduce the number of layers of the photomask and reduce the processes of cyclic exposure, ion implantation and photoresist stripping can greatly reduce the production cost, shorten the manufacturing period and improve the competitiveness of the product.
Therefore, it is necessary to optimize the well fabrication process and the well implantation mask set of the conventional CMOS device to save the mask during the well formation process, and finally achieve the purpose of saving the cost.
Disclosure of Invention
The invention aims to provide a well preparation method and a well injection photomask set of a semiconductor integrated device, which save photomasks in the well forming process.
In order to achieve the above object, the present invention provides a well preparation method of a semiconductor integrated device, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with at least two device areas;
forming a patterned first mask layer on the semiconductor substrate by using a photomask, wherein the first mask layer is provided with a corresponding ion implantation opening on each device area, and the opening ratios of the first mask layer on the device areas are different;
performing first trap ion implantation on the semiconductor substrate by taking the first mask layer as a mask;
annealing the semiconductor substrate to simultaneously form different wells in different device regions.
Optionally, when the semiconductor substrate has two device regions with different required well depths, before forming the first mask layer on the semiconductor substrate, the well preparation method further includes:
forming a patterned second mask layer complementary to the first mask layer on the semiconductor substrate by using the photomask;
performing second trap ion implantation on the semiconductor substrate by taking the second mask layer as a mask, wherein the depth of the second trap ion implantation is different from that of the first trap ion implantation;
removing the second mask layer;
and after annealing the semiconductor substrate, the ions of the first trap ion implantation and the second trap ion implantation in each device region are diffused to form a trap with corresponding trap depth.
Optionally, the first mask layer is formed by performing photolithography on a positive photoresist through the photomask, and the second mask layer is formed by performing photolithography on a negative photoresist through the photomask.
Optionally, after the first well ion implantation is performed on the semiconductor substrate and before the annealing is performed on the semiconductor substrate, a plurality of sub-wells with the same well depth are further formed in the well of one of the device regions.
Optionally, the step of further forming a plurality of sub-wells having the same well depth in the well of one of the device regions includes:
removing the first mask layer;
forming a patterned third mask layer on the semiconductor substrate by using another photomask, wherein the device region comprises at least two sub-device regions, the third mask layer is provided with corresponding ion implantation openings in each sub-device region of the device region, the opening ratios of the third mask layer in each sub-device region are not equal, and the third mask layer also masks other device regions except the device region;
performing third trap ion implantation on each sub-device region by taking the third mask layer as a mask;
and after annealing the semiconductor substrate, forming wells with different well depths in the device region and other device regions, and forming sub-wells with the same well depth in the wells of the device region.
Optionally, when each of the sub-device regions includes a low-voltage device region, a voltage indicator region, and a memory device region, the aperture ratios of the another mask corresponding to the low-voltage device region, the voltage indicator region, and the memory device region are sequentially increased.
Optionally, when the required well depths of the respective device regions of the semiconductor substrate are the same, before forming the patterned first mask layer on the semiconductor substrate, the well preparation method further includes: performing fourth well ion implantation on the semiconductor substrate, wherein the depth of the fourth well ion implantation is greater than that of the first well ion implantation, so as to form a deep well in each device region; and forming a corresponding well in the deep well in each device region after annealing the semiconductor substrate.
Optionally, when the semiconductor substrate comprises a low-voltage device region, a standard device region and a storage device region with the same required well depth, the aperture ratio of the photomask on the low-voltage device region, the standard device region and the storage device region is increased in sequence; when the semiconductor substrate comprises a low-voltage device area and a medium-voltage device area which have different required trap depths, the aperture ratio of the photomask corresponding to the medium-voltage device area is smaller than that of the low-voltage device area.
Optionally, when a plurality of ion implantation openings are formed in two or more device regions, the size of each ion implantation opening in the two or more device regions is the same, but the size of the stopper located between any two adjacent ion implantation openings in different device regions is different; alternatively, the size of each stopper on the two or more device regions is the same, but the size of the ion implantation opening on different device regions is different.
Based on the same inventive concept, the invention further provides a well implantation mask set for implementing the well preparation method of the semiconductor integrated device, wherein the well implantation mask set comprises a mask, the mask is used for forming a patterned first mask layer on a semiconductor substrate so as to respectively define corresponding well ion implantation areas on at least two device areas of the semiconductor integrated device, and the aperture ratios of the mask corresponding to the device areas in the at least two device areas are not equal.
Optionally, the openings in the one reticle are formed by providing corresponding dummy lithographic patterns, and each opening corresponds to a region on the corresponding device region for trap ion implantation or a region not for trap ion implantation.
Optionally, the set of well implantation masks further includes another mask, where the another mask is used to form a patterned third mask layer on the semiconductor substrate to define a corresponding well ion implantation region on each sub-device region of at least one of the device regions, and the aperture ratios of the another mask corresponding to each sub-device region are not equal.
Optionally, the openings in the other reticle are formed by setting respective dummy lithographic patterns, and the openings in the other reticle correspond to regions on the respective sub-device regions that are or are not used for trap ion implantation.
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
1. the technical scheme of the invention can utilize a photomask to form a patterned first mask layer on the semiconductor substrate, the first mask layer has corresponding ion implantation openings in each device region, and the opening ratios are not equal, when the first mask layer is used as a mask, after the first trap ion implantation and the annealing are carried out on the semiconductor substrate, different traps can be formed in different device areas at the same time, for example, a special mask is used to fabricate wells required by each device region in different device regions with different well depths, such as the medium-voltage device region and the low-voltage device region, or a special mask is used, the method comprises the steps of manufacturing wells required by all device regions in different device regions with the same well depth, such as a low-voltage device region, a standard device region, a storage device region and the like. Compared with the prior art, the technical scheme of the invention can save the photomask, simplify the process flow and greatly save the manufacturing cost of the device on the basis of realizing the same device characteristics as the prior art.
2. According to the technical scheme, after the light shield is used for manufacturing the wells with different well depths in different device areas, the other light shield can be used for manufacturing the wells with the same well depths in the sub-device areas of one device area, so that more light shields are saved compared with the prior art, the process flow is further simplified, and the manufacturing cost is reduced.
3. The well injection photomask set can be used for realizing the well preparation method of the semiconductor integrated device and is easy to manufacture.
Drawings
FIGS. 1A-1D are schematic cross-sectional views of a device structure in a well forming method in a CMOS process of a conventional standard low power platform;
fig. 2 is a flowchart of a well preparation method of a semiconductor integrated device according to an embodiment of the present invention;
fig. 3A to 3C are schematic cross-sectional views of device structures in a well preparation method of the semiconductor integrated device shown in fig. 2;
fig. 4 is a flowchart of a well preparation method of a semiconductor integrated device according to another embodiment of the present invention;
fig. 5A to 5C are schematic cross-sectional views of device structures in a well preparation method of a semiconductor integrated device according to a second embodiment of the present invention;
fig. 6 is a flowchart of a well preparation method of a semiconductor integrated device according to still another embodiment of the present invention;
fig. 7A to 7D are schematic cross-sectional views of device structures in a well preparation method of the semiconductor integrated device shown in fig. 6.
Detailed Description
As described in the background art, the well fabrication process of the conventional CMOS device has a complicated flow, a large number of required mask layers, and a high fabrication cost. Based on this, the core idea of the technical scheme of the present invention is to provide a new well preparation method for a semiconductor integrated device and a well injection mask set for implementing the method, which can form different wells in different device regions through a customized mask, so as to achieve the purposes of saving masks in the well formation process, simplifying the process flow, reducing the cost, and implementing the device characteristics equivalent to those of the existing process. The core steps of the technical scheme of the invention comprise: firstly, providing a semiconductor substrate, wherein the semiconductor substrate is provided with at least two device areas; then, a first mask layer is formed on the semiconductor substrate by utilizing a photomask, the first mask layer is provided with corresponding ion implantation openings in each device area, and the opening ratios of the first mask layer in the device areas are not equal; then, taking the first mask layer as a mask, and carrying out first trap ion implantation on the semiconductor substrate; thereafter, the semiconductor substrate is annealed to simultaneously form different wells in different of the device regions. It should be noted that, the aperture ratio of the mask layer referred to herein is in the same plane, and a ratio between a total area of all openings in the mask layer on a certain device region and an entire area of the mask layer before the opening is opened (i.e., a surface area of the device region), when ion implantation is performed on the device region by using the mask layer having the opening as a mask, if the aperture ratio of the mask layer is larger, the surface area of the device region is less blocked by the mask layer (i.e., the smaller the total area of all stoppers in the mask layer is, the larger the total area of all openings is, i.e., the larger the sum of the surface areas of the device region exposed by all openings is), and at this time, more ions are implanted into the device region.
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, an embodiment of the invention provides a well preparation method of a semiconductor integrated device, including the following steps:
s11, providing a semiconductor substrate, wherein the semiconductor substrate is provided with two device regions with different required trap depths;
s12, forming a second mask layer on the semiconductor substrate by using a photomask, wherein the second mask layer covers one device region and is provided with a corresponding ion implantation opening on the other device region;
s13, performing second trap ion implantation on the semiconductor substrate by taking the second mask layer as a mask;
s14, removing the second mask layer;
s15, forming a first mask layer complementary to the second mask layer on the semiconductor substrate by using the photomask, the first mask layer exposing the one device region and having a corresponding ion implantation opening on the other device region;
s16, taking the first mask layer as a mask, and carrying out first trap ion implantation on the semiconductor substrate;
and S17, annealing the semiconductor substrate to form corresponding wells in the two device regions at the same time, wherein the wells in the two device regions have different well depths.
Referring to fig. 3A, in step S11, the semiconductor substrate 200 provided may be any suitable substrate material known to those skilled in the art, such as a silicon substrate, a silicon-on-insulator substrate, etc. The semiconductor substrate 200 has a device region I and a device region II with different required well depths, the two device regions I, II can be separated by a device isolation structure (not shown) such as a shallow trench isolation structure, the device region I can be a medium voltage device region, and the device region II can be a low voltage device region. In addition, the pad oxide layer 201 may be formed on the surface of the semiconductor substrate 200 through a thermal oxidation process or a chemical vapor deposition process, which may enhance the adhesion of the photoresist coated subsequently, thereby preventing the photoresist from wrinkling and chapping after exposure, and thus may affect the photolithography effect, and may protect the semiconductor substrate 200 in the subsequent photolithography process and the process of removing the photoresist.
With continued reference to fig. 3A, in step S12, first, a negative photoresist may be coated on the surface of the pad oxide layer 201, the negative photoresist covers the device region I and the device region II and a series of photolithography processes such as exposure and development are performed on the negative photoresist by using a special mask 100 to form a patterned second mask layer 203, the special mask 100 has a specially designed dummy photolithography pattern (i.e., mainly composed of 100a and 100 b), so that the formed patterned second mask layer 203 completely covers the surface of the pad oxide layer 201 of the device region II and has a plurality of ion implantation openings 203A in the device region I exposing the surface of the pad oxide layer 201, and each ion implantation opening 203A corresponds to a stopper (i.e., a masking body) 100b between two openings in the mask 100. That is to say, with the special mask 100, the aperture ratio of the patterned second mask layer 203 formed after the photolithography in the device region I is greater than the aperture ratio of the patterned second mask layer 203 in the device region II, each ion implantation opening 203a in the second mask layer 203 is used for subsequently implanting trap ions into the semiconductor substrate 200 in the device region I, and the second mask layer 203 outside all the ion implantation openings 203a is used as a masking body for forming a masking effect on the subsequent trap ion implantation process and preventing the trap ions from being implanted into the coverage area of the second mask layer 203. It should be noted that, in other embodiments of the present invention, the second mask layer 203 may also be a dielectric material layer such as silicon nitride, silicon oxynitride, or the like, at this time, the second mask layer 203 and the negative photoresist layer may be sequentially covered on the pad oxide layer 201, the negative photoresist layer is patterned by using the photomask 100, and then the second mask layer 203 is etched by using the negative photoresist layer as a mask to form the patterned second mask layer 203, so that the patterned second mask layer 203 completely covers the surface of the pad oxide layer 201 in the device region II, and the device region I has a plurality of ion implantation openings 203a exposing the surface of the pad oxide layer 201.
With reference to fig. 3A, in step S13, a second trap ion implantation is performed on the semiconductor substrate 200 by using the patterned second mask layer 203 as a mask, so as to form a plurality of ion-doped regions 204 in the device region I. The ion type adopted by the second trap ion implantation can be reasonably selected according to the type of the trap required by the device region I, when an N trap needs to be formed, the element corresponding to the ion implanted by the second trap ion implantation can be phosphorus, arsenic or antimony, and when a P trap needs to be formed, the element corresponding to the ion implanted by the second trap ion implantation can be boron. The energy and dose of the second well ion implantation may be appropriately selected according to the well depth of the well to be formed in the device region I.
Referring to fig. 3B, in step S14, a suitable removal process may be selected according to the material of the second mask layer 203 to remove the second mask layer 203, for example, when the second mask layer 203 is a negative photoresist, a conventional photoresist removal process such as an oxygen ashing process may be used to remove the second mask layer 203, and when the second mask layer 203 is a dielectric material such as silicon nitride, silicon oxynitride, or the like, a wet etching process or a chemical mechanical polishing process may be used to remove the second mask layer 203.
With reference to fig. 3B, in step S15, first, a positive photoresist is coated on the surface of the pad oxide layer 201, the positive photoresist covers the device region I and the device region II, and a series of photolithography processes such as exposure and development are performed on the positive photoresist by using the special mask 100 to form a patterned first mask layer 205, the formed patterned first mask layer 205 is complementary to the patterned second mask layer 203 formed in step S12, the patterned first mask layer 205 completely exposes the surface of the device region II, and the device region I has a plurality of ion implantation openings 205a exposing the pad oxide layer 201, the ion implantation openings 205a exactly correspond to the openings 100a in the mask 100, and the ion implantation openings 205a and the ion implantation openings 203a in step S12 are exactly staggered. That is to say, with the special mask 100, the aperture ratio of the patterned first mask layer 205 formed after the photolithography in the device region I is smaller than the aperture ratio of the patterned first mask layer 205 in the device region II, each ion implantation opening 205a in the patterned first mask layer 205 is used for subsequently implanting well ions into the semiconductor substrate 200 in the device region I, an ion implantation opening (not shown) in the patterned first mask layer 205 for exposing the device region II is used for subsequently implanting well ions into the semiconductor substrate 200 in the device region II, and the first mask layers 205 outside all the ion implantation openings are used as masking bodies for forming a masking effect on the subsequent well ion implantation process to prevent the well ions from being implanted into the semiconductor substrate region covered by the patterned first mask layer 205. It should be noted that, in other embodiments of the present invention, the first mask layer 205 may also be a dielectric material layer such as silicon nitride, silicon oxynitride, etc., at this time, the first mask layer 205 and the positive photoresist layer may be sequentially covered on the pad oxide layer 201, the photoresist layer is patterned by photolithography using the photomask 100, and then the first mask layer 205 is etched by using the positive photoresist layer as a mask to form the patterned first mask layer 205, so that the patterned first mask layer 205 completely exposes the surface of the device region II and has a plurality of ion implantation openings 205a in the device region I, which expose the pad oxide layer 201.
With continued reference to fig. 3B, in step S16, a first trap ion implantation is performed on the semiconductor substrate 200 with the patterned first mask layer 205 as a mask. Wherein the ion type used for the first well ion implantation is the same as the ion type used for the second well ion implantation, and the energy of the first well ion implantation is smaller than the energy of the second well ion implantation, so that the depth of the ion doped region 206 formed in the device regions I and II is smaller than the depth of the ion doped region 204 formed in step S13.
Referring to fig. 3C, in step S17, first, a suitable removal process may be selected according to the material of the first mask layer 205 to remove the first mask layer 205, for example, when the first mask layer 205 is a positive photoresist, a conventional photoresist removal process such as an oxygen ashing process may be used to remove the first mask layer 205, and when the first mask layer 205 is a dielectric material such as silicon nitride, silicon oxynitride, or the like, a wet etching process or a chemical mechanical polishing process may be used to remove the first mask layer 205. Next, high temperature annealing (e.g., 1100-1500 ℃, 90-120 min) may be performed to diffuse the ions implanted into the semiconductor substrate 200 by the first well and the second well to a suitable depth, and the ion doped region 204 and the ion doped region 206 in the device region I are integrated by ion diffusion, and because the depth of the ion doped region 204 is relatively deep, the average well depth H1 of the finally formed well 207 in the device region I is larger than the average well depth H2 of the finally formed well 208 in the device region II.
It should be noted that, in this embodiment, only the formation process of the wells (for example, N wells) of the same conductivity type in the device region I and the device region II is described, but the technical solution of the present invention is not limited thereto, and the device region I and the device region II not only need to form N wells, but also need to form P wells, at this time, the ion implantation required for the N wells may be completed by using the above steps S11 to S16, then, under the technical teaching of the N well preparation method, another special mask for making P wells is used to complete the ion implantation required for the P wells in a similar manner, and finally, after the annealing process of step S17, the required N wells and P wells may be formed in the device region I and the device region II. Thereafter, the pad oxide layer 201 may be removed by wet etching (e.g., a mixed hydrofluoric acid and nitric acid solution) or Chemical Mechanical Polishing (CMP). Generally, the well implementation process belongs to the previous process of the integrated circuit, and after the well is manufactured, devices such as diodes, triodes, MOS transistors, resistors, capacitors and the like can be manufactured in and on the surface layer of the well.
Referring to fig. 3A and 3B, the present embodiment further provides a well implantation mask set for implementing the well preparation method of the semiconductor integrated device, where the well implantation mask set includes a mask 100, the mask 100 is used to form a patterned first mask layer 205 on a semiconductor substrate 200 to define regions for first well ion implantation on two device regions I and II of the semiconductor integrated device, respectively, and to form a patterned second mask layer 203 on the semiconductor substrate 200 to define regions for second well ion implantation on the two device regions I and II of the semiconductor integrated device, respectively. The aperture ratios of the mask 100 corresponding to the device regions I and II are not equal. Alternatively, the openings 100a in the photomask 100 are formed by setting corresponding dummy lithography patterns, and each of the openings 100a corresponds to a region on the device region I for the first well ion implantation (as shown in fig. 3B) and a region on the device region I not for the second well ion implantation (as shown in fig. 3A).
To sum up, the well preparation method and the well implantation mask set for the semiconductor integrated device according to the embodiment can utilize a special mask to form the patterned first mask layer on the semiconductor substrate, the patterned first mask layer has corresponding ion implantation openings on each device region, and the opening ratios of the patterned first mask layer are different. Compared with the semiconductor integrated device trap process in the prior art, the technical scheme of the embodiment can save the photomask, simplify the process flow and greatly save the manufacturing cost of the device on the basis of realizing the same device characteristics as the prior art. For example, one mask may be saved when only N-wells or P-wells are formed in both device regions, and two masks may be saved when both N-wells and P-wells need to be formed in both device regions. Obviously, the more the number of device regions is, and the more the number of wells and well depths are, the more the number of layers of the photomask can be saved by applying the technical solution of the present embodiment, and the greater the degree of simplification of the process flow is.
It should be noted that, in the above embodiments, although the well preparation method and the well implantation mask set of the semiconductor integrated device are described by taking two device regions with different required well depths as an example in the semiconductor substrate, the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, the semiconductor substrate may further have more device regions with different required well depths, at this time, corresponding multi-layer masks may be manufactured to form the well implantation mask set, the number of masks in the well implantation mask set is less than the number of device regions, and each mask 100 has a specific dummy pattern design in each device region, so that the aperture ratios of the formed mask layers in each device region are different, each mask may be used to manufacture one mask layer or two mask layers for corresponding well ion implantation, and finally, after the annealing in step S17, the ion implantation of each step trap can form a trap with required trap depth in each device region after the ion diffusion.
In addition, the well preparation method and the well implantation mask set of the semiconductor integrated device in the above embodiments can form wells with different well depths in different device regions, but the technical solution of the present invention is not limited thereto, and wells with the same well depth may be formed in different device regions in another embodiment of the present invention. Specifically, referring to fig. 4, another embodiment of the present invention provides a well preparation method of a semiconductor integrated device, including the following steps:
s21, providing a semiconductor substrate, wherein the semiconductor substrate is provided with at least two device regions with the same required well depth;
s22, performing fourth well ion implantation to the semiconductor substrate to form deep wells in the respective device regions;
s23, forming a patterned first mask layer on the semiconductor substrate by using a photomask, wherein the opening ratios of the first mask layer on each device area are different;
s24, taking the first mask layer as a mask, and carrying out first trap ion implantation on the semiconductor substrate;
and S25, annealing the semiconductor substrate to simultaneously form corresponding wells in the deep wells of the device regions, wherein the well depths of the wells in the device regions are the same.
Referring to fig. 5A, in step S21, the semiconductor substrate 300 provided may be any suitable substrate material known to those skilled in the art, such as a silicon substrate, a silicon-on-insulator substrate, etc. The semiconductor substrate 300 has a device region I, a device region II and a device region III, which have the same required well depth, the three device regions may be defined and isolated from each other by a device isolation structure (not shown) such as a shallow trench isolation structure, the device region I may be a low voltage device region, the device region II may be a standard device region, and the device region III may be a memory device region (e.g., an SRAM device region). In addition, the pad oxide layer 301 may be formed on the surface of the semiconductor substrate 300 through a thermal oxidation process or a chemical vapor deposition process, which may enhance the adhesion of the photoresist coated subsequently and prevent the photoresist from wrinkling and chapping after exposure to affect the photolithography effect, and may protect the semiconductor substrate 300 in the subsequent photolithography process and the process of removing the photoresist.
With continued reference to fig. 5A, in step S22, when the semiconductor substrate 200 further has a device region I, a device region II, and a device region other than the device region III, a positive photoresist may be coated on the surface of the pad oxide layer 301, and a series of photolithography processes such as exposure and development may be performed on the positive photoresist using a conventional photomask to form a patterned photoresist (not shown), which exposes the device region I, the device region II, and the device region III and masks the device region other than the device region I, the device region II, and the device region III. Thereafter, the patterned photoresist is used as a mask, and fourth well ion implantation is performed on the semiconductor substrate 300 to form a deep well 302 in the device region I, the device region II, and the device region III. The ion type adopted by the fourth well ion implantation can be reasonably selected according to the types of wells required by the device region I, the device region II and the device region III, and when N wells need to be formed in the device region I, the device region II and the device region III, elements corresponding to the ions implanted by the fourth well ion implantation can be P-type elements such as boron and the like or N-type elements such as phosphorus, arsenic or antimony and the like. Thereafter, the patterned photoresist is removed.
Referring to fig. 5B, in step S23, a positive photoresist may be coated on the surface of the pad oxide layer 301, and a special mask 500 is used to perform a series of photolithography processes such as exposure and development on the positive photoresist, so as to form a patterned first mask layer (i.e., a combination of 303a and 303B and corresponding openings in the figure), where the patterned first mask layer completely exposes the surface of the device region III, and a plurality of ion implantation openings exposing the pad oxide layer 301 are formed in the device region I and the device region II, and each ion implantation opening exactly corresponds to the opening 500a in the mask 500. As an example, the tailored photomask 500 has the same size, shape, etc. of each opening 500a in the device regions I and II, but has an aperture ratio in the device region I smaller than that in the device region II, so that the line width of the stopper 500b between the adjacent openings 500a corresponding to the device region I is larger than that of the stopper 500c between the adjacent openings 500a corresponding to the device region II. That is, the specially-made mask 500 may be used to sequentially increase the aperture opening ratios of the patterned first mask layer formed after the photolithography in the device region I, the device region II, and the device region III, the line widths of the stoppers 303a (corresponding to the stoppers 500b of the mask 500 one by one) of the patterned first mask layer in the device region I are greater than the line widths of the stoppers 303b (corresponding to the stoppers 500c of the mask 500 one by one) in the device region II, the line width W1 of the ion implantation openings of the patterned first mask layer in the device region I is equal to the line width W2 of the ion implantation openings in the device region II, and when the surface areas of the device region I and the device region II are the same, the number of the ion implantation openings of the patterned first mask layer in the device region I is less than the number of the ion implantation openings in the device region II. As another example, the openings of the special mask 500 in the device regions I and II are different in size, but the size and shape of the stop 500b in the device region I and the stop 500c in the device region II are the same, so that the aperture ratio of the mask 500 in the device region I is still smaller than that in the device region II. That is, the specially-made photomask 500 is utilized to sequentially increase the aperture opening ratios of the patterned first mask layer formed after the photolithography in the device region I, the device region II and the device region III, the line width of the stop 303a of the patterned first mask layer in the device region I is equal to the line width of the stop 303b of the patterned first mask layer in the device region II, the line width W1 of the ion implantation opening of the patterned first mask layer in the device region I is smaller than the line width W2 of the ion implantation opening in the device region II, and when the surface areas of the device region I and the device region II are the same, the number of the ion implantation openings of the patterned first mask layer in the device region I is greater than the number of the ion implantation openings in the device region II. In summary, when the surface areas and the opening sizes of the device region I and the device region II are the same, the smaller the number of the openings, the wider the stoppers, the larger the total area occupied by all the stoppers, and the smaller the opening ratio; when the surface areas and the stop sizes of the device region I and the device region II are the same, the more the number of the openings is, the more the number of the stops is, the larger the total area occupied by all the stops is, the smaller the opening ratio is, and the smaller the opening is at the moment. In addition, in other embodiments of the present invention, the patterned first mask layer may also be a dielectric material layer such as silicon nitride, silicon oxynitride, or the like, and at this time, the pad oxide layer 301 may be sequentially covered with the first mask layer and a positive photoresist layer, and then the positive photoresist layer is subjected to photolithography patterning by using the photomask 500, and then the first mask layer is etched by using the positive photoresist layer as a mask to form the patterned first mask layer.
With reference to fig. 5B, in step S24, a first trap ion implantation is performed on the semiconductor substrate 300 by using the patterned first mask layer as a mask. The ion type adopted by the ion implantation of the first trap is the same as that adopted by the ion implantation of the fourth trap, and can also be opposite. And the energy of the first well ion implantation is less than the energy of the fourth well ion implantation so that the depth of the ion-doped region 304 formed in the device regions I to III is less than the depth of the deep well 302 formed in step S22. And as the aperture opening ratios of the first mask layer 205 in the device region I, the device region II and the device region III are sequentially increased, the ion dose of the fourth well ion implantation doped into the device region I, the device region II and the device region III is sequentially increased.
Referring to fig. 5C, in step S25, first, a suitable removal process may be selected according to the material of the first mask layer to remove the first mask layer, for example, when the first mask layer is a positive photoresist, the first mask layer may be removed by a conventional photoresist removal process such as oxygen ashing, and when the first mask layer is a dielectric material such as silicon nitride, silicon oxynitride, or the like, the first mask layer may be removed by a process such as wet etching or chemical mechanical polishing. Then, high temperature annealing (e.g. 1100-1500 ℃, 90-120 min) may be adopted, such that the ions implanted into the semiconductor substrate 300 by the fourth well and the first well are diffused to a suitable depth, and the ion doped region 304 in the device region I forms a well 305 in the deep well 302 of the region, the ion doped region 304 in the device region II forms a well 306 in the deep well 302 of the region, the ion doped region 304 in the device region III forms a well 307 in the deep well 302 of the region, and the well depths of the wells 305-307 are the same. And because the ion dose of the first trap ion implantation doped into the device region I, the device region II and the device region III is the same, and the ion dose of the fourth trap ion implantation doped into the device region I, the device region II and the device region III is increased in sequence, the total ion doping concentration in the trap 305, the trap 306 and the trap 307 is increased in sequence.
It should be noted that, in this embodiment, only the formation process of the wells (for example, N wells) of the same conductivity type in the device regions I to III is described, but the technical solution of the present invention is not limited thereto, and the device regions I to III need to form not only N wells but also P wells, at this time, the ion implantation required for the N wells may be completed by the above steps S21 to S24, then, the ion implantation required for the P wells may be completed by another special mask for fabricating the P wells in a similar manner under the technical teaching of the N well preparation method by those skilled in the art, and finally, after the annealing process of step S25, the required N wells and P wells may be formed in the device regions I to III. Thereafter, the pad oxide layer 301 may be removed by wet etching (e.g., a mixed hydrofluoric acid and nitric acid solution) or Chemical Mechanical Polishing (CMP). Generally, the well implementation process belongs to the previous process of the integrated circuit, and after the well is manufactured, devices such as diodes, triodes, MOS transistors, resistors, capacitors and the like can be manufactured in and on the surface layer of the well.
Referring to fig. 5B, the present embodiment further provides a well implantation mask set for implementing the well preparation method of the semiconductor integrated device, where the well implantation mask set includes a mask 500, and the mask 500 is used to form a patterned first mask layer on the semiconductor substrate 300, so as to define first well ion implantation regions on the device regions I to III of the semiconductor integrated device, respectively. The aperture ratios of the mask 500 corresponding to the device regions I to III are not equal. Optionally, the openings 500a in the photomask 500 are formed by setting corresponding dummy lithography patterns, and each of the openings 500a corresponds to a region of the device regions I to III for the first well ion implantation.
To sum up, the well preparation method and the well implantation mask set for the semiconductor integrated device according to the embodiment can utilize a special mask to form the patterned first mask layer on the semiconductor substrate, the patterned first mask layer has corresponding ion implantation openings on each device region, and the opening ratios of the patterned first mask layer are different. Compared with the semiconductor integrated device trap process in the prior art, the technical scheme of the embodiment can save the photomask, simplify the process flow and greatly save the manufacturing cost of the device on the basis of realizing the same device characteristics as the prior art. For example, when the N well or the P well is formed only in three device regions, namely, the low-voltage device region, the voltage indicator device region and the memory device region, two layers of masks can be saved, and when the N well and the P well are required to be formed in all three device regions, namely, the low-voltage device region, the voltage indicator device region and the memory device region, four layers of masks can be saved. Obviously, the greater the number of device regions and the greater the number of wells required, the greater the number of mask layers that can be saved by applying the technical solution of the present embodiment, the greater the degree of simplification of the process flow.
The well preparation method and the well implantation mask set of the semiconductor integrated device in the two embodiments can form wells with different well depths or wells with the same well depth in different device regions, but the technical scheme of the invention is not limited to this, and in another embodiment of the invention, wells with different well depths can be formed in different device regions, or wells with the same well depth can be further formed in some device regions. Specifically, referring to fig. 6, another embodiment of the present invention provides a well preparation method of a semiconductor integrated device, including the following steps:
s31, providing a semiconductor substrate, wherein the semiconductor substrate is provided with two device areas, and one device area is provided with at least two sub device areas;
s32, forming a second mask layer on the semiconductor substrate by using a photomask, wherein the second mask layer covers one device region and is provided with a corresponding ion implantation opening on the other device region;
s33, performing second trap ion implantation on the semiconductor substrate by taking the second mask layer as a mask;
s34, removing the second mask layer;
s35, forming a first mask layer complementary to the second mask layer on the semiconductor substrate by using the photomask, the first mask layer exposing the one device region and having a corresponding ion implantation opening on the other device region;
s36, taking the first mask layer as a mask, and carrying out first trap ion implantation on the semiconductor substrate;
s37, forming a patterned third mask layer on the semiconductor substrate by using another photomask, where the third mask layer covers the another device region and has corresponding ion implantation openings in each sub-device region of the one device region, and the opening ratios of the third mask layer in each sub-device region are different;
s38, taking the third mask layer as a mask, and carrying out third well ion implantation on the semiconductor substrate;
s39, annealing the semiconductor substrate to simultaneously form wells with different respective well depths in the two device regions, and forming sub-wells with the same well depth corresponding to the respective sub-device regions in the well of the one device region.
Referring to fig. 7A, in step S31, the semiconductor substrate 400 provided may be any suitable substrate material known to those skilled in the art, such as a silicon substrate, a silicon-on-insulator substrate, etc. The semiconductor substrate 400 has a device region I and a device region II with different required well depths, the device region II has three sub-device regions III, IV, V, two device regions I, II and three sub-device regions III, IV, V can be isolated by a device isolation structure (not shown) such as a shallow trench isolation structure, the device region I can be a medium voltage device region, and the sub-device regions III, IV, V can be a low voltage device region, a voltage scaling device region and a memory device region in sequence. In addition, the pad oxide layer 401 may be formed on the surface of the semiconductor substrate 400 by a thermal oxidation process, a chemical vapor deposition process, or the like.
With continued reference to fig. 7A, in step S32, a negative photoresist may be first coated on the surface of the pad oxide layer 401, the negative photoresist covers the device region I and the device region II, and a special mask 100 is used to perform a series of photolithography processes such as exposure and development on the negative photoresist to form a patterned second mask layer 403, the special mask 100 has a specially designed dummy photolithography pattern, so that the formed patterned second mask layer 403 completely covers the surface of the device region II, and the device region I has a plurality of ion implantation openings 403a exposing the pad oxide layer 401, and each ion implantation opening 403a exactly corresponds to a stop between two openings in the mask 100. That is, the specially-made mask 100 can make the aperture ratio of the patterned second mask layer 403 formed after photolithography in the device region I larger than that in the device region II. It should be noted that, in other embodiments of the present invention, the second mask layer 403 may also be a dielectric material layer such as silicon nitride, silicon oxynitride, or the like, at this time, the pad oxide layer 401 may be sequentially covered with the second mask layer 403 and the negative photoresist layer, the negative photoresist layer is then patterned by using the photomask 100, and then the second mask layer 403 is etched by using the negative photoresist layer as a mask to form the patterned second mask layer 403, so that the patterned second mask layer 403 completely covers the surface of the device region II and the device region I has a plurality of ion implantation openings 403a exposing the pad oxide layer 401.
With reference to fig. 7A, in step S33, a second trap ion implantation is performed on the semiconductor substrate 400 by using the patterned second mask layer 403 as a mask, so as to form a plurality of ion-doped regions 404 in the device region I. The ion type adopted by the second trap ion implantation can be reasonably selected according to the type of the trap required by the device region I, when an N trap needs to be formed, the element corresponding to the ion implanted by the second trap ion implantation can be phosphorus, arsenic or antimony, and when a P trap needs to be formed, the element corresponding to the ion implanted by the second trap ion implantation can be boron. The energy and dose of the second well ion implantation may be appropriately selected according to the well depth of the well to be formed in the device region I.
Referring to fig. 7B, in step S24, a suitable removal process may be selected according to the material of the second mask layer 403 to remove the second mask layer 403, for example, when the second mask layer 403 is a negative photoresist, the second mask layer 403 may be removed by a conventional photoresist removal process such as oxygen ashing, and when the second mask layer 403 is a dielectric material such as silicon nitride and silicon oxynitride, the second mask layer 403 may be removed by a wet etching process or a chemical mechanical polishing process.
With reference to fig. 7B, in step S35, a positive photoresist may be coated on the surface of the pad oxide layer 401, the positive photoresist covers the device region I and the device region II, and a series of photolithography processes such as exposure and development are performed on the positive photoresist by using the special mask 100 to form a patterned first mask layer 405, the formed patterned first mask layer 405 is complementary to the patterned second mask layer 403 formed in step S32, the patterned first mask layer 405 completely exposes the surface of the device region II, and has a plurality of ion implantation openings 405a exposing the pad oxide layer 401 in the device region I, the ion implantation openings 405a correspond to the openings in the mask 100, and the ion implantation openings 405a and the ion implantation openings 403a in step S32 are staggered with each other. That is, the specially-made mask 100 can make the aperture ratio of the patterned first mask layer 405 formed after photolithography on the device region I smaller than that on the device region II. It should be noted that, in other embodiments of the present invention, the first mask layer 405 may also be a dielectric material layer such as silicon nitride, silicon oxynitride, etc., at this time, the first mask layer 205 and the positive photoresist layer may be sequentially covered on the pad oxide layer 401, the photoresist layer is patterned by photolithography using the photomask 100, and then the first mask layer 405 is etched by using the positive photoresist layer as a mask to form the patterned first mask layer 405, so that the patterned first mask layer 405 completely exposes the surface of the device region II, and the device region I has a plurality of ion implantation openings 405a exposing the pad oxide layer 401.
With reference to fig. 7B, in step S36, a first trap ion implantation is performed on the semiconductor substrate 400 by using the patterned first mask layer 405 as a mask. Wherein the ion type used for the first well ion implantation is the same as the ion type used for the second well ion implantation, and the energy of the first well ion implantation is less than the energy of the second well ion implantation, so that the depth of the ion doped region 406 formed in the device regions I and II is less than the depth of the ion doped region 404 formed in step S33.
Referring to fig. 7C, in step S37, first, a suitable removal process may be selected according to the material of the first mask layer 405 to remove the first mask layer 405, for example, when the first mask layer 405 is a positive photoresist, the first mask layer 405 may be removed by a conventional photoresist removal process such as oxygen ashing, and when the first mask layer 405 is a dielectric material such as silicon nitride and silicon oxynitride, the first mask layer 405 may be removed by a wet etching process or a chemical mechanical polishing process. Next, a positive photoresist may be coated on the surface of the pad oxide layer 301, and a series of photolithography processes such as exposure and development are performed on the positive photoresist by using a special mask 500 to form a patterned third mask layer 407, where the patterned third mask layer 407 completely exposes the surface of the sub-device region V and completely covers the surface of the device region I, and a plurality of ion implantation openings (not labeled in fig. 7C) exposing the pad oxide layer 401 are formed in the sub-device regions III and IV, and each ion implantation opening corresponds to an opening (not labeled in fig. 7C) in the mask 500. As an example, the tailored photomask 500 has the same size, shape, etc. of each opening in the sub-device regions III and IV, but has an opening ratio in the sub-device region III that is smaller than that in the sub-device region IV, so that the line width of the stopper between adjacent openings corresponding to the sub-device region III is larger than that of the stopper between adjacent openings corresponding to the device region IV. That is, with the special mask 500, the aperture ratios of the patterned third mask layer 407 in the device region I and the device region II after photolithography are sequentially increased, the aperture ratios in the sub-device regions III to V are also sequentially increased, the line width of the stopper 407a of the patterned third mask layer 407 in the sub-device region III is greater than the line width of the stopper 407b in the sub-device region IV, the line width W1 of the ion implantation opening of the patterned third mask layer 407 in the sub-device region III is equal to the line width of the ion implantation opening in the sub-device region IV, and the number of the ion implantation openings of the patterned third mask layer 407 in the sub-device region III is less than the number of the ion implantation openings in the sub-device region IV. As another example, the openings of the tailored photomask 500 in the sub-device regions III and IV are different in size, but the size and shape of the stops in the sub-device region III and the stops in the sub-device region IV are the same, so that the aperture ratio of the photomask 500 in the sub-device region III is still smaller than that in the sub-device region IV. That is to say, with the special mask 500, the aperture opening ratios of the patterned third mask layer 407 formed after the photolithography in the device region I and the device region II sequentially increase, the aperture opening ratios in the sub-device regions III, IV, and V sequentially increase, the line widths of the stoppers of the patterned third mask layer 407 in the sub-device regions III and IV are equal, the line width of the ion implantation opening of the patterned third mask layer 407 in the sub-device region III is smaller than the line width of the ion implantation opening in the sub-device region IV, and the number of the ion implantation openings of the patterned first third mask layer 407 in the sub-device region III is greater than the number of the ion implantation openings in the sub-device region IV. It should be noted that, in other embodiments of the present invention, the patterned third mask layer may also be a dielectric material layer such as silicon nitride, silicon oxynitride, or the like, at this time, the pad oxide layer 401 may be sequentially covered with the third mask layer and the positive photoresist layer, the positive photoresist layer is then patterned by photolithography using the photomask 500, and then the patterned third mask layer is formed by etching the third mask layer with the positive photoresist layer as a mask.
With reference to fig. 7C, in step S38, a third well ion implantation is performed on the semiconductor substrate 300 by using the patterned third mask layer 407 as a mask. Wherein the ion type used by the third trap ion implantation is the same as the ion type used by the first trap ion implantation. And the energy of the third well ion implantation is less than the energy of the first well ion implantation such that the depth of the ion-doped region 408 formed in the sub-device regions III-V is less than the depth of the ion-doped region 406 formed in step S36.
Referring to fig. 7D, in step S39, first, a suitable removal process may be selected according to the material of the third mask layer 407 to remove the third mask layer 407, for example, when the third mask layer 407 is a positive photoresist, a conventional photoresist removal process such as oxygen ashing treatment may be used to remove the third mask layer 407, and when the third mask layer 407 is a dielectric material such as silicon nitride, silicon oxynitride, or the like, a wet etching process or a chemical mechanical polishing process may be used to remove the first mask layer. Then, high temperature annealing (e.g. 1100-1500 ℃, 90-120 min) may be employed to diffuse the ions implanted into the semiconductor substrate 400 by the second well ion implantation, the first well ion implantation and the third well ion implantation to a suitable depth, and the ion doped regions 404 and 406 in the device region I form a well 409 with a larger well depth in the region, the ion doped region 406 in the device region II forms a deep well with a shallower well depth in the region than the well 409, the ion doped region 408 in the sub-device region III forms a sub-well 410 in the deep well 406 in the region, the ion doped region 408 in the sub-device region IV forms a sub-well 411 in the deep well 406 in the region, the ion doped region 408 in the sub-device region V forms a sub-well 412 in the deep well 406 in the region, and the well depths of the sub-wells 410-412 are the same.
Referring to fig. 7A, 7B and 7C, the present embodiment further provides a well implantation mask set for implementing the well preparation method of the semiconductor integrated device according to the present invention, wherein the well implantation mask set includes a mask 100 and another mask 500. The photomask 100 is used for forming a patterned first mask layer 405 on a semiconductor substrate 400 to define regions for first well ion implantation on two device regions I and II of the semiconductor integrated device, respectively, and forming a patterned second mask layer 403 on the semiconductor substrate 400 to define regions for second well ion implantation on the two device regions I and II of the semiconductor integrated device, respectively. The aperture ratios of the mask 100 corresponding to the device regions I and II are not equal. Alternatively, the openings in the one reticle 100 are formed by providing corresponding dummy lithographic patterns, and each opening corresponds to a region on the device region I for the first well ion implantation (as shown in fig. 7B) and a region on the device region I not for the second well ion implantation (as shown in fig. 7A). The other photomask 500 is used for forming a patterned third mask layer 407 on the semiconductor substrate 400 to respectively define regions for third well ion implantation on the respective sub-device regions III-V of the device region II of the semiconductor integrated device. The other mask 500 covers the device region I and has unequal aperture ratios in the respective sub-device regions III-V. Alternatively, the openings in the other photo-mask 500 are formed by setting corresponding dummy photo-etching patterns, and each opening corresponds to a region of each sub-device region III-V for ion implantation of the third well (when the third mask layer is a positive photoresist) or a region not for ion implantation of the well (when the third mask layer is a negative photoresist).
To sum up, the well preparation method and the well implantation mask set of the semiconductor integrated device of the embodiment can utilize two layers of special masks to form wells with different well depths in different device regions of the semiconductor substrate and further form a plurality of sub-wells with the same well depth in the well of one device region.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (11)

1. A well preparation method of a semiconductor integrated device is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with at least two device areas;
forming a patterned first mask layer on the semiconductor substrate by using a photomask, wherein the first mask layer is provided with a corresponding ion implantation opening on each device area of the at least two device areas, and the opening ratios of the first mask layer on the device areas of the at least two device areas are different;
performing first trap ion implantation on the semiconductor substrate by taking the first mask layer as a mask;
annealing the semiconductor substrate to simultaneously form different wells in different ones of the at least two device regions;
before forming the first mask layer on the semiconductor substrate, the well preparation method further includes:
forming a patterned second mask layer complementary to the first mask layer on the semiconductor substrate by using the photomask;
performing second trap ion implantation on the semiconductor substrate by taking the second mask layer as a mask, wherein the depth of the second trap ion implantation is different from that of the first trap ion implantation;
removing the second mask layer;
and after annealing the semiconductor substrate, forming a well with a corresponding well depth after diffusing the ions of the first well ion implantation and the second well ion implantation in each of the at least two device regions.
2. The well preparation method of claim 1, wherein the first mask layer is formed by photolithography of a positive photoresist by the photomask, and the second mask layer is formed by photolithography of a negative photoresist by the photomask.
3. The well preparation method of claim 1, wherein after the first well ion implantation is performed on the semiconductor substrate and before the annealing of the semiconductor substrate, a plurality of sub-wells having the same well depth are further formed in the well of one of the at least two device regions.
4. The well preparation method of claim 3, wherein the step of further forming a plurality of sub-wells having the same well depth in the well of one of the at least two device regions comprises:
removing the first mask layer;
forming a patterned third mask layer on the semiconductor substrate by using another photomask, wherein one device region comprises at least two sub-device regions, the third mask layer is provided with corresponding ion implantation openings in each of the at least two sub-device regions, the opening ratios of the third mask layer in each sub-device region are not equal, and the third mask layer also masks device regions except the one device region in the at least two device regions;
performing third trap ion implantation on each sub-device region by taking the third mask layer as a mask;
and after annealing the semiconductor substrate, forming wells with different well depths in each of the at least two device regions, and forming sub-wells with the same well depth in the well of one device region.
5. The well preparation method according to claim 4, wherein when each of the sub-device regions includes a low-voltage device region, a marker device region and a memory device region, the aperture ratios of the other mask in the low-voltage device region, the marker device region and the memory device region are sequentially increased.
6. The well preparation method of claim 1, wherein when the semiconductor substrate includes a low-voltage device region, a tag device region and a memory device region having the same required well depth, the aperture ratio of the mask increases in order corresponding to the low-voltage device region, the tag device region and the memory device region; when the semiconductor substrate comprises a low-voltage device area and a medium-voltage device area which have different required trap depths, the aperture ratio of the photomask corresponding to the medium-voltage device area is smaller than that of the low-voltage device area.
7. The well preparation method according to claim 1, wherein when a plurality of ion implantation openings are formed in each of two or more of the at least two device regions, the size of each of the ion implantation openings in the two or more device regions is the same, but the size of the stopper between any two adjacent ion implantation openings in different device regions is different; alternatively, the size of each stopper on the two or more device regions is the same, but the size of the ion implantation opening on different device regions is different.
8. A well implantation mask set for implementing the well preparation method of the semiconductor integrated device as claimed in any one of claims 1 to 7, wherein the well implantation mask set comprises a mask for forming a patterned first mask layer on a semiconductor substrate to define respective well ion implantation regions on at least two device regions of the semiconductor integrated device, and the aperture ratios of the mask corresponding to the device regions of the at least two device regions are not equal.
9. The set of well implantation reticles of claim 8 wherein the openings in the one reticle are formed by providing a respective dummy lithographic pattern and each opening corresponds to a region on a respective device region of the at least two device regions that is or is not used for well ion implantation.
10. The set of well implantation masks according to claim 8, further comprising another mask for forming a patterned third mask layer on the semiconductor substrate to define respective well ion implantation regions on respective sub-device regions of at least one of the at least two device regions, the other mask corresponding to unequal aperture ratios of the respective sub-device regions.
11. The set of well implantation reticles of claim 10 wherein the openings in the other reticle are formed by providing a respective dummy lithographic pattern and the openings in the other reticle correspond to regions on the respective sub-device regions that are or are not used for well ion implantation.
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