JP2001272767A - Photomask and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of manufacture processes for a semiconductor device. SOLUTION: The photomask has a first light transmitting region consisting of an opening of a specified size, a second light transmitting region having a plurality of openings periodically repeated, and a third light transmitting region consisting of an opening of a specified size formed to surround the second light transmitting region on a mask substrate. The semiconductor device is manufactured by using this mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a photomask and a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a high-withstand-voltage CMOS semiconductor device and a photomask that can be suitably used for the manufacture.

[0002]

2. Description of the Related Art In a manufacturing process of a high breakdown voltage CMOS type semiconductor device, a well region (impurity diffusion layer) for forming a low breakdown voltage MOS transistor constituting the device is heavily doped with impurities in order to reduce the size of the transistor. It is necessary to form a well region (impurity diffusion layer) for forming a high-breakdown-voltage MOS transistor by ion-implanting a low-concentration impurity in order to ensure a high withstand voltage of the transistor.

An element isolation film made of a LOCOS oxide film is provided in a medium withstand voltage portion between a well region for forming a low withstand voltage MOS transistor and a well region for forming a high withstand voltage MOS transistor. In this medium-breakdown-voltage portion, it was necessary to form a high-concentration impurity diffusion layer in a region below the LOCOS oxide film in order to secure element isolation withstand voltage.

In the three impurity diffusion layers, impurities are diffused at different concentrations on the same substrate. To form these impurity diffusion layers, using three types of photomasks,
It is necessary to form three types of photoresist patterns and perform ion implantation of impurities for each pattern.

FIGS. 5A to 5F show an example of a conventional manufacturing method.

First, as shown in FIG. 5A, an insulating film (first oxide film) 2a is formed on a semiconductor substrate 1 made of P-type silicon.

[0007] Next, as shown in FIG.
In order to form a well region for forming an OS transistor, a photoresist layer formed by application is selectively opened using a photomask (not shown),
A photoresist pattern 3a is formed. Using this pattern 3a, high-concentration ion implantation of impurities (phosphorus) required for forming a low-breakdown-voltage MOS transistor is performed first.

Next, the photoresist pattern 3a used in the first ion implantation is removed. Thereafter, FIG.
In order to form a well region for forming a high withstand voltage MOS transistor, a photoresist pattern formed by coating is selectively opened using a photomask (not shown) as shown in FIG. 3b is formed. Using this pattern 3b, low-concentration ion implantation of impurities (phosphorus) required for forming a high-voltage MOS transistor is performed second.

Next, the photoresist pattern 3b used in the second ion implantation is removed. Thereafter, the semiconductor substrate 1 is subjected to a high-temperature heat treatment to diffuse the implanted impurities, thereby forming well regions (impurity diffusion layers) 4 and 6 having a necessary concentration and a necessary depth (FIG. 5D )reference).

Subsequently, as shown in FIG.
An element isolation step between transistors is performed. That is, after removing the first oxide film 2a, a second oxide film 2b is formed, and a silicon nitride film 8 is stacked thereon. Next, the silicon nitride film 8 on the second oxide film 2b in the element isolation region is removed. Next, using a photomask having an opening in a well region 6 for forming a high withstand voltage MOS transistor, a photoresist layer formed by coating is selectively opened to form a photoresist pattern 3c. afterwards,
By using this pattern 3c, the element isolation withstand voltage is ensured, and the low-concentration ion implantation of the impurity (phosphorus) is performed with the implantation energy and the dose amount that do not penetrate the silicon nitride film 8.
To do.

The photoresist pattern 3c used in the third ion implantation is removed. Thereafter, as shown in FIG. 5F, the LOCOS oxidation is performed, so that the impurity diffusion layer 5 for element isolation is formed in the well region 6 under the LOCOS oxide film together with the LOCOS oxide film 7.

Here, the N well region is formed by using phosphorus as an impurity, but the same flow can be formed when forming the P well region.

[0013]

In the above-mentioned conventional method of manufacturing a high-breakdown-voltage CMOS semiconductor device, a step of forming well regions having different concentrations required to secure low-breakdown-voltage and high-breakdown-voltage transistor breakdown voltages. In addition, a step of forming an impurity diffusion layer for element isolation is required. In these forming steps, the number of photomasks, the number of steps of forming a photoresist pattern, and the number of times of ion implantation increase because impurity diffusion layers are formed by injecting impurities in different amounts. Therefore, there has been a problem that the chip cost and the cost of the manufacturing process increase.

Japanese Patent Application Laid-Open No. H11-111855 describes a method in which two types of well regions having different concentrations are formed at once.

The manufacturing method described in the above publication is shown in FIG.
(A) and (b).

Specifically, a photomask having a first light transmitting region having one opening and a second light transmitting region having a plurality of mesh-shaped openings repeated at a specific period is formed. Next, a photoresist layer is formed on the semiconductor substrate 1 on which the LOCOS oxide film 7 has been formed by coating. A photoresist pattern 3 is formed by exposing and developing the photoresist layer using a photomask.
(A)). In the figure, reference numeral 3-1 denotes a photoresist pattern in a second region corresponding to a second light transmission region formed of a plurality of openings in a mesh shape, and is used for forming a well region for forming a high breakdown voltage MOS transistor. Is done.

Using the photoresist pattern 3, an impurity (boron) is ion-implanted. By removing the photoresist pattern 3 and then thermally diffusing the impurities, two types of well regions having different concentrations capable of realizing desired threshold values of the two types of transistors can be formed at a time ( FIG. 6 (b)).

However, even in the above method, the well region forming step and the element separating impurity diffusion layer forming step involve the following steps.
Two times of photoresist pattern formation and ion implantation are required. Therefore, the problem that the cost of the chip and the cost of the manufacturing process increase is inevitable.

[0019]

Thus, according to the present invention, a first light transmitting region having an opening of a predetermined size and a plurality of openings repeated regularly are provided on a mask substrate. There is provided a photomask having a second light transmitting region and a third light transmitting region having an opening of a predetermined size provided to surround the periphery of the second light transmitting region.

Further, according to the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a first region having an opening of a predetermined size on the insulating film and a region different from the first region. Forming a photoresist pattern including a second region having a plurality of openings that are repeatedly repeated, and a third region including openings having a predetermined size so as to surround the periphery of the second region; Using the photoresist pattern as a mask, a step of ion-implanting impurities into the semiconductor substrate, a step of removing the insulating film, and a heat treatment of the semiconductor substrate, thereby diffusing the ion-implanted impurities into the first region and the second region. And a step of simultaneously forming an impurity diffusion layer corresponding to the third region. According to the above method, it is possible to form impurity diffusion layers having three different concentrations at the same time by performing heat treatment after performing one ion implantation on the semiconductor substrate. Further, according to the present invention, there is provided a semiconductor device obtained by the above method.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic plan view showing an example of the photomask of the present invention. In FIG. 1, 15, 16 and 17 are:
It means the first light transmission region, the second light transmission region, and the third light transmission region, respectively. Reference numeral 18 denotes a light shielding portion. In FIG. 1, the second light transmission region has a plurality of mesh-shaped regularly repeated openings defined by the light shielding portions 18.

In FIG. 1, the second light transmitting region is constituted by a plurality of openings in a mesh shape, but is not limited to this, and may be constituted by a plurality of openings in a checkered pattern or a slit shape.

The photomask is formed on a mask substrate known in the art. Further, the light shielding portion may be made of a light shielding material such as chrome.

Although it depends on the use of the photomask, the second light transmitting region preferably has an aperture ratio of 25 to 55%. When a photomask having such an aperture ratio is used as a mask for forming a photoresist pattern for ion implantation of a CMOS semiconductor device, for example, two impurity diffusion layers having different concentrations can be formed. Further, at the time of this ion implantation, an impurity diffusion layer derived from the third light transmitting region can be formed at the same time.

Furthermore, the opening of the second light transmitting region preferably has a square planar shape. When one side of the square is 1 to 1.8 μm, the light-shielding portion preferably has a line width in the range of 0.4 to 1 μm. When one side of the square is 0.3 to 1 μm, the light shielding portion preferably has a line width in a range of 0.1 to 1 μm.

Next, a method for manufacturing a semiconductor device according to the present invention will be described.
This will be described with reference to FIGS.

First, an insulating film (first oxide film) 2a for reducing damage during ion implantation is formed on the semiconductor substrate 1 (see FIG. 2A). Here, the semiconductor substrate is not particularly limited, and any known substrate such as a silicon substrate can be used. Further, the semiconductor substrate may have a P or N conductivity type.

Next, a photoresist film is applied on the entire surface. Next, by exposing and developing the photoresist film using a photomask, a first region including an opening having a predetermined size, and a plurality of regularly repeated regions different from the first region. A photoresist pattern including a second region having an opening and a third region having an opening having a predetermined size is formed so as to surround the periphery of the second region (FIG. 2).
(B)). The size of the opening constituting each region is appropriately set according to the size and impurity concentration of the impurity diffusion layer formed by the subsequent ion implantation. In FIG. 2B,
3-1 indicates a photoresist pattern forming the second region.

Here, it is preferable to use the photomask of FIG. 1 as the photomask. Photomask second
The light transmitting region may be patterned in a mesh shape including, for example, a square opening having a side of 1 to 1.6 μm and a light shielding portion having a line width of 0.5 to 1.0 μm.

2A to 2E, the first region is formed in a high-concentration well forming region 4a for forming a low-breakdown-voltage MOS transistor, and the second region is formed in a high-breakdown-voltage MOS transistor.
The third region is formed in the high-concentration well formation region 6a for transistor formation, and the third region is formed in the formation region 5a of the high-concentration impurity diffusion layer for element isolation adjacent to the periphery of the second region. When the photomask of FIG. 1 is used, the first
The region, the second region, and the second region are a first light transmitting region, a second light
The light transmitting region and the third light transmitting region are formed simultaneously.

Next, ion implantation of impurities is performed. Here, when the semiconductor substrate is a P-type, the impurity is preferably phosphorus. Phosphorus ion implantation has an implantation energy of 40
About 0 keV, dose amount 1 × 10 ¹³ atoms / cm ²
It is preferable to carry out the reaction under the following conditions. Note that when the semiconductor substrate is an N-type, the impurity is preferably boron.

As a result of this ion implantation, a mesh-shaped photoresist pattern 3-1 exists at a high concentration in the well region for the MOS transistor having a low breakdown voltage and the region for forming the impurity diffusion layer for element isolation in accordance with the implantation amount. High withstand voltage MO
In the well region for the S transistor, the amount of implantation is reduced according to the area of the opening, and impurities are implanted at a low concentration.

Next, the photoresist pattern used for the ion implantation and the first oxide film 2a are removed. After this,
Usually, oxidation for forming a LOCOS oxide film is performed by a known method, but it is preferable to perform the following processing prior to the oxidation. That is, the second oxide film 2b is formed, and the silicon nitride film 8 is formed thereon. Furthermore, low voltage MOS
Patterning is performed through a photolithography step and an etching step so that the silicon nitride film 8 remains in the transistor well formation region 4a and the impurity diffusion layer formation region 5a for element isolation (see FIG. 2C).

Next, as shown in FIG. 2D, LOCOS oxidation is performed to form a LOCOS oxide film 7. Simultaneously with the formation of the oxide film 7, the well regions 4 and 6 having a predetermined depth and a uniform impurity concentration distribution and the impurity diffusion layer 5 for element isolation are formed by the annealing effect at the time of oxidation. .

The LOCOS oxide film 7 has a thickness of 350 to 4
It is preferably about 00 nm. Further, it is preferable that the Locos oxidation is performed, for example, at a temperature of about 1100 ° C. for about 8 hours.

Under the above conditions, the depths of the well regions 4 and 6 and the impurity diffusion layer 5 after the LOCOS oxidation are preferably about 3 μm. The width after the formation of the impurity diffusion layer 5 is 0.6 to 1.2 μm (design value is 0.6 to 1.2 μm).
m) is preferred. Note that the depth and the width can be set as appropriate depending on the desired characteristics of the semiconductor device. The implantation using this mask is performed on the LOCOS oxide film, and a desired effect can be obtained by adding a heat treatment at a temperature of about 1100 ° C. for 8 hours.

Next, as shown in FIG. 2E, for example, a P-type MOS transistor (1) is formed in the well regions 4 and 6.
0, 11, 12) can be formed using existing methods. In the figure, 13 indicates a source and 14 indicates a drain.

Thereafter, steps such as formation of an interlayer insulating film, formation of a metal wiring, formation of a cover insulating film, and the like are performed on the semiconductor substrate using a known method, whereby a semiconductor device can be formed.

Next, the photomask of FIG.
When used to form a high-concentration well region for forming an OS transistor, a high-concentration well region for forming a high-withstand-voltage MOS transistor, and a high-concentration impurity diffusion layer for element isolation, an opening in the second light transmission region is used. MO with high efficiency
The relationship with the impurity concentration of the high concentration well region for forming the S transistor is examined. In this specification, the aperture ratio means a ratio of the sum of the areas of the square openings to the entire area of the second light transmission region.

FIG. 3 shows the results. The ion implantation conditions of the impurity for forming the well region are as follows. Phosphorus is used as the impurity, the implantation energy is 400 keV, and the dose is 1 × 1.
0 ¹³ atoms / cm ² .

FIG. 4 shows an element isolation withstand voltage and a high withstand voltage MOS.
The relation of the concentration of the well region 6 for forming a transistor is shown. Here, as shown in FIG. 2E, the element isolation withstand voltage is equal to the source 13 of the P-type MOS transistor 10 and the P-type MOS transistor 10.
+ / P of the drain 14 of the MOS transistor 11
It means the breakdown voltage between +.

The following can be seen from FIGS.

First, in the presence of the impurity diffusion layer 5, as the concentration of the well region 6 decreases, it becomes possible to increase the element isolation withstand voltage. The concentration of the well region 6 can be realized by reducing the aperture ratio, as shown in FIG.

For example, the element isolation withstand voltage is about 15 V to 30 V.
And set the width of the impurity diffusion layer for element isolation to 1 μm.
4, the impurity concentration of the well region 6 is 3 ×
10 ¹⁶~ 5 × 10¹⁶atom / cm^ThreeNeed a degree
You. The impurity concentration is 25 to 55% as shown in FIG.
Is equivalent to

From these results, the combination of one side of the square opening of the photomask and the line width of the light-shielding portion can be appropriately selected so as to obtain a desired element isolation breakdown voltage as described below. 1: Line width of 0.4 to 1 μm when one side of square is 1 to 1.8 μm 2: Line width of 0.1 to 1 μm when one side of square is 0.3 to 1 μm More specifically, Can be combined as follows. a: When one side of the square is 1.8 μm, the line width is 0.7
１1 μm b: line width 0.6 when one side of a square is 1.5 μm
１1 μm c: When one side of the square is 1.25 μm, the line width is 0.1 μm.
5-1 μm d: When one side of the square is 1 μm, the line width is 0.4-1.
μm e: line width 0.2 when one side of a square is 0.6 μm
.About.0.6 .mu.m f: line width 0.1 when one side of a square is 0.3 .mu.m
The impurity concentration of the well region 4 corresponds to the case where the aperture ratio in FIG. 3 is 100%, and is 10 ¹⁷ atoms / cm ^3.
It is. The element isolation breakdown voltage at this concentration is about 8 V from FIG. It can be seen that this withstand voltage can be increased by reducing the impurity concentration, as shown in FIG.

[0047]

When the photomask of the present invention is used for forming a well region of a semiconductor device and an impurity diffusion layer for element isolation, ion implantation for forming these can be performed at once. Further, heat treatment for diffusing impurities and heat treatment for forming a LOCOS oxide film can be performed in one step. Therefore, the number of photomasks can be greatly reduced and the number of manufacturing steps can be reduced as compared with the related art.

Specifically, according to the present invention,
Although one photolithography step and three ion implantation steps have been performed, the number can be reduced to one photolithography step and one ion implantation step. Further, the heat treatment for diffusing the impurities, which has been performed for each ion implantation, can be performed simultaneously with the LOCOS oxidation. Therefore, the number of heat treatment steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a photomask of the present invention.

FIG. 2 is a schematic sectional view of a process in a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a diagram illustrating a relationship between an aperture ratio of a photomask and an impurity concentration of a well region.

FIG. 4 is a diagram showing a relationship between an element isolation breakdown voltage and an impurity concentration in a well region.

FIG. 5 is a schematic sectional view of a process in a method for manufacturing a conventional semiconductor device.

FIG. 6 is a schematic sectional view of a process in a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2a insulating film (first oxide film) 2b second oxide film 3, 3a, 3b, 3c photoresist pattern 3-1 second region photoresist pattern 4, 6 well region (impurity diffusion layer) 4a , 6a High-concentration well formation region 5 Element isolation impurity diffusion layer 5a Element isolation impurity diffusion layer formation region 7 Locos oxide film 8 Silicon nitride film 10, 11, 12 MOS transistor 13 Source 14 Drain 15 First light transmission Region 16 Second light transmitting region 17 Third light transmitting region 18 Light shielding portion

Claims (9)

[Claims] 1. A first light transmission region having a predetermined size of an opening, a second light transmission region having a plurality of regularly repeated openings, and a second light transmission on a mask substrate. A third light transmitting region having an opening of a predetermined size provided so as to surround the periphery of the region. 2. The photomask according to claim 1, wherein the second light transmitting region has a plurality of openings formed in a mesh shape by a light shielding portion. 3. The photomask according to claim 2, wherein the second light transmitting region has an aperture ratio of 25 to 55%. 4. When the opening of the second light transmitting region has a square planar shape, and one side of the square is 1 to 1.8 μm,
When the light-shielding portion has a line width in the range of 0.4 to 1 μm and one side of the square is 0.3 to 1 μm, the light-shielding portion is 0.1 to 1 μm.
3. The photomask according to claim 1, having a line width in a range of μm. 5. A step of forming an insulating film on a semiconductor substrate; a first region having an opening of a predetermined size on the insulating film;
A second region having a plurality of openings regularly repeated in a region different from the first region, and a third region having an opening of a predetermined size so as to surround the periphery of the second region; A step of forming a photoresist pattern, a step of ion-implanting impurities into a semiconductor substrate using the photoresist pattern as a mask, a step of removing an insulating film, and a step of heat-treating the semiconductor substrate to diffuse the ion-implanted impurities. And simultaneously forming impurity diffusion layers corresponding to the first region, the second region, and the third region. 6. A photo-resist pattern formed on a mask substrate, a first light-transmitting region corresponding to a first region and having an opening having a predetermined size, and a plurality of regularly-repeated regions corresponding to a second region. And a third light transmitting region having an opening of a predetermined size provided corresponding to the third region and surrounding the periphery of the second light transmitting region. The method according to claim 5, wherein the photoresist is formed by exposing and developing a photoresist layer formed on a semiconductor substrate using a photomask. 7. A first region is formed in a high-concentration well formation region for forming a low breakdown voltage MOS transistor, and a second region is formed in a high-concentration well formation region for forming a high breakdown voltage MOS transistor. 7. The method according to claim 5, wherein the three regions are formed adjacent to the periphery of the second region in a region where a high-concentration impurity diffusion layer for element isolation is formed. 8. A plurality of P-type MOs are formed on a semiconductor substrate in a second region.
The method according to any one of claims 5 to 7, wherein S transistors are formed, and a device isolation breakdown voltage between the transistors is 15V to 30V. 9. A semiconductor device obtained by the method according to claim 5.