JPH1050859A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture method of a semiconductor device which can considerably reduce influence on the other element at the time of incorporating a high withstand voltage-type element in a well area whose conduction type is opposite to that of a substrate. SOLUTION: At the time of forming the N-type well area 13 in the P substrate 11, the half of the well area 13 is diffused by heat treatment for the first time and impurities forming the lightly doped drain area 15 of high withstand voltage MOS are ion-implanted. Then, the N-type well area 13 is diffused and the lightly doped drain area 15 is diffused by heat treatment for the second time. Then, a channel stopper area 18, a LOCOS oxidized film and respective MOS transistors are formed. Since the lightly doped drain area 15 is diffused by using a part of the heat diffusion treatment of the N-type well area 13, heat history is prevented from being excessively increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a high-voltage MOS transistor and a low-voltage MOS transistor are integrated.

[0002]

2. Description of the Related Art When constructing a CMOS type semiconductor integrated circuit, there are a method using a P substrate and a method using an N substrate, but an appropriate conductivity type is sometimes determined according to the characteristics of elements to be mounted. . For example, a SAMOS type EEPROM
In order to simplify the configuration, an N-channel type is used, so that a P region is required. Further, since writing of information to the floating gate is performed by hot electron injection, a large current flows from the source to the drain at the time of writing.
At this time, the substrate potential is easily affected by the current. Therefore, in order to stabilize the substrate potential by the back electrode of the chip, instead of using the P-type well region of the N-substrate as the above-mentioned P-region, the above-mentioned element is formed by using the surface of the P-type substrate itself as the above-mentioned P-region. This is a good example of using a substrate.

On the other hand, there is a demand for coexistence of these low-breakdown-voltage elements and high-breakdown-voltage elements for constituting an output transistor. As the high breakdown voltage element, a P-channel type element is frequently used because of its ease of fabrication and ease of circuit configuration. If a P-channel element is to be formed on the surface of a P-type substrate, it will be formed in an N-type well region where the conductivity type is reversed.

Conventionally, an example of an apparatus in which such a high breakdown voltage type element and a low breakdown voltage type element are integrated and coexisted with a P-type substrate (for example, Japanese Patent Application Laid-Open No. 03-257862) will be described below. First, as shown in FIG. 7A, a resist mask 2 is formed on the surface of a P-type semiconductor substrate 1 and phosphorus is selectively ion-implanted. A well region (3) is formed, an oxide film is formed on the surface as shown in FIG. 7B, and a silicon nitride film 3 is formed thereon.
Then, a photoresist film 4 is formed on the surface as shown in FIG. 8A, and boron for forming a channel stopper 5 is ion-implanted into the surface of the P substrate 1 as shown in FIG. A LOCOS oxide film 6 for element isolation is formed by selective oxidation as shown in FIG.
As shown in FIG. 9A, a resist mask 7 is formed on the surface, boron for forming a low-concentration drain region 8 for a high-breakdown-voltage P-channel MOS is ion-implanted, and the low-concentration drain region 8 is diffused by heat treatment. As shown in FIG. 9B, a gate oxide film and a gate electrode 9 are formed, and as shown in FIG.
Is formed to complete the device.

[0005]

The low-concentration drain region 8 of the high breakdown voltage MOS maintains the breakdown voltage by expanding the depletion layer from the PN junction. Therefore, it is necessary to secure a space in which a depletion layer having a width commensurate with the withstand voltage can be expanded, and it is necessary to naturally increase the diffusion depth and lower the impurity concentration.

However, since the well region 2 itself has an impurity concentration that inverts the impurity concentration of the substrate 1 (approximately one order of magnitude higher than that of the substrate), deep diffusion at such a low impurity concentration requires a high temperature Time heat treatment is required.
In this case, the higher the withstand voltage to be obtained, the higher the temperature and the longer the process. Therefore, in the conventional manufacturing method, the N-well region 2 and the channel stopper 5 are re-diffused in the step of forming the low-concentration drain region 8, so that the impurity profiles of both are destroyed. Therefore, there is a disadvantage that the inversion voltage below the LOCOS oxide film 6 is reduced, and the breakdown voltage between elements of the transistor is reduced in both the N-channel and the P-channel.

In addition, since the N-well region 2 is rediffused in the step of forming the low-concentration drain region 8, the inversion voltage of the P-channel transistor is reduced, and the short-channel effect tends to occur. Further, as described above, since the heat treatment for incorporating the high breakdown voltage MOS affects the manufacturing conditions in all subsequent steps, for example, a dedicated manufacturing process is established for each of the products incorporating the high breakdown voltage MOS and the products not incorporating the same. This not only complicates the process management but also has the disadvantage that the development time of the product cannot be reduced.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has a heat diffusion step for an N-well region.
The first heat treatment diffuses half of the N-well region, then forms a low-concentration drain region, and performs the second heat treatment to diffuse the low-concentration drain region and the N-well region.

In this step, the heat diffusion process for the low-concentration drain region is completed by using a part of the heat diffusion process for the N-well region. Therefore, a new heat treatment for forming the low-concentration drain region is not required. The overall heat history can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. First, referring to FIG. 1A, a P-type single-crystal silicon substrate 11 having an impurity concentration of about 1E15 is prepared. A surface of the substrate 11 is initially oxidized to form an oxide film, a photoresist film is applied thereon, and a resist mask 12 is formed by exposure and development. Phosphorus is ion-implanted from above under the conditions of a dose of 1E13 atoms · cm−2 and an acceleration voltage of 100 KeV.

Referring to FIG. 1B, a resist mask 1
After removing 2, 1 was applied to the substrate 11 as a first heat treatment.
Thermal diffusion is performed at 150 ° C. for 6 hours. In this step, the N-well region 13 is diffused from the surface of the substrate 11 to a depth of about 4 μ. After the first heat treatment, the wafer is taken out of the diffusion furnace, a resist mask 14 is formed on the surface, and boron for forming a low-concentration drain region 15 on the surface of the N-well region 13 is doped with a dose of 1E13 atoms. cm-
2. Ion implantation is performed under the condition of an acceleration voltage of 50 KeV.

Referring to FIG. 2A, resist mask 1
After removing 4, the wafer is placed in a diffusion furnace and a second heat treatment is performed at 1150 ° C. for 1 hour. In this step, the low concentration drain region 15 is formed with a diffusion depth of about 2 μ,
N well region 12 is formed with a diffusion depth of about 5 μ. Referring to FIG. 2B, after forming a clean oxide film on the surface, a silicon nitride film 16 is deposited thereon by CVD.
This is patterned to form an oxidation resistant film 16. A resist mask 17 is formed on the oxidation-resistant film 16 to cover the N-well region 13, and boron is formed only on the surface of the P-type substrate 11 to form the channel stopper region 18 using the oxidation-resistant film 16 as a mask at a dose of 1E13 atoms.・ Cm-
2. Ion implantation is performed under the condition of an acceleration voltage of 40 KeV.

Referring to FIG. 3A, resist mask 1
7 is removed, and the entire substrate 11 is subjected to a heat treatment at about 1000 ° C. for 5 to 8 hours to form a LOCOS oxide film 19 for element isolation. A channel stopper region 18 is formed below the LOCOS oxide film 19 by the impurities implanted in the previous step. Referring to FIG. 3B, the oxidation-resistant film 16 is removed, the oxide film on the surface of the element region surrounded by the LOCOS oxide film 19 is removed, and the surface is oxidized again to a clean film thickness of about 150 °. A gate oxide film (not shown) is formed, a polysilicon layer or a polysilicon / silicide film is formed thereon, and the gate electrode 20 is formed by patterning this.

Referring to FIG. 4A, an NSG film is formed on gate electrode 20 by a CVD method, and the entire surface is etched back by anisotropic etching such as RIE to form gate electrode 2.
The spacers 21 are formed on both sides of 0. Referring to FIG. 4B, N well region 1 is formed to form an N channel MOS.
3 is coated with a resist mask 22 and the gate electrode 2
0 is used as a mask, phosphorus is ion-implanted first, and then arsenic is ion-implanted.
A drain region 23 is formed.

Referring to FIG. 5, a P-type source / drain region is formed by coating the surface of P substrate 11 with a resist mask 24 to form a P-channel MOS and implanting boron ions using gate electrode 20 as a mask. 25 are formed. Then, the resist mask 24 is removed, and an annealing process for activating the impurities that have been ion-implanted into the whole is performed to obtain the apparatus shown in FIG. Thereafter, the process shifts to the step of forming the insulating film and the electrode wiring. Note that a backing electrode is formed on the back side of the P substrate 11, and a back gate voltage VDD is applied to the P substrate 11 via the backing electrode.

As a result, the P-lightly doped drain region 15 is formed with a diffusion depth of about 5 μm from the surface. It is formed with an impurity concentration of 3.
The breakdown voltage between the gate and the drain is maintained by expanding the depletion layer at the PN junction between the low-concentration drain region 15 and the N-well region 13.

According to the present invention, since a sufficient high-temperature heat treatment can be applied to the P-low-concentration drain region 15, the impurity concentration can be reduced and a sufficient diffusion depth can be obtained. Therefore, a region where the depletion layer is to be enlarged can be secured, and a high breakdown voltage MOS transistor having a gate-drain breakdown voltage of several tens of volts can easily coexist.

Furthermore, since the channel stopper region 18 below the LOCOS oxide film 1 is formed after the thermal diffusion of the P-lightly doped drain region 15 is completed, the channel stopper region 18 is not exposed to a high-temperature heat treatment. Deterioration of the element isolation withstand voltage of the N-channel MOS transistor can be avoided. Further, the N-well region 13
Since the P-low-concentration drain region 15 is formed by utilizing a part of the heat treatment for forming the N-well region, the processing time of the process can be reduced, and the formation of the low-concentration drain region 13 affects the impurity profile of the N-well region. Do not give. Accordingly, there is no deterioration in the element isolation breakdown voltage of the P-channel transistor, and there is no influence on the gate inversion voltage of the P-channel transistor.

As described above, in the present invention, the formation of the low-concentration drain region 13 does not affect other elements.
This means that, for example, the manufacturing flow of another element (low-voltage MOS) and its conditions can be made common between a model in which the high-voltage MOS is incorporated and a model in which the high-voltage MOS is not incorporated. In addition, there is an advantage that the development time of the model can be reduced.

To further develop, for example, when it is desired to change the breakdown voltage of the output transistor, it means to change the diffusion depth of the P-lightly doped drain region 15. The first diffusion time is shortened and the second diffusion time is lengthened accordingly. By making the sum of the first and second diffusion times the same, various characteristics of other elements can be obtained. Can be selectively changed without changing the diffusion depth.

[0021]

As described above, according to the present invention,
Since a sufficient heat treatment at a high temperature for a long time can be applied to the P-low-concentration drain region 15, there is an advantage that a high-breakdown-voltage element can be easily incorporated into the well region 13 of the opposite conductivity type to the substrate 11. This is particularly advantageous when a high-withstand-voltage element whose channel type is also determined by other factors is incorporated into the substrate 11 whose conductivity type is determined by other factors.

Further, since the P-low-concentration drain region 15 is formed by utilizing a part of the heat treatment for forming the N-well region 13, the formation of the P-low-concentration drain region 15 is different from other elements. No need to change properties. This means that the manufacturing flow of other elements (low-breakdown-voltage MOS) and its conditions can be made common between the model in which the high-breakdown-voltage MOS is incorporated and the model in which the high-breakdown-voltage MOS is not incorporated. This has the advantage of reducing development time.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a plan view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a plan view for explaining the present invention.

FIG. 7 is a plan view for explaining a conventional example.

FIG. 8 is a plan view for explaining a conventional example.

FIG. 9 is a plan view for explaining a conventional example.

FIG. 10 is a plan view for explaining a conventional example.

Claims (2)

[Claims] A step of forming a first photoresist film on a surface of a semiconductor substrate of one conductivity type and ion-implanting impurities of a reverse conductivity type for forming the well region; removing the first photoresist film; A first diffusion step of diffusing the well region to a first diffusion depth by a first heat treatment; forming a second photoresist film on the surface of the substrate; Ion-implanting one conductivity type impurity for forming a concentration drain region, removing the second photoresist film, diffusing the low concentration drain region by a second heat treatment, and simultaneously diffusing the well region with a second diffusion A second step of diffusing to a depth; a step of forming a LOCOS oxide film for element isolation on the surface of the semiconductor substrate; a step of forming a gate electrode; Forming source / drain regions,
Forming a high withstand voltage transistor having the low-concentration drain region as a drain. 2. The method according to claim 1, wherein said semiconductor substrate is P-type, and said low-concentration drain region is P-type.