JPH11150181A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a guttering site at a lower part of an element separation region with no effect on a semiconductor element for a minimum number of manufacturing processes, by oxidizing a semiconductor substrate, with an oxidation-resistant film as a mask, to form the element separation region while ion-implanting with the oxidation-resistant film as a mask. SOLUTION: On a semiconductor substrate 101, a silicon oxide film 102 and then an oxidation-resistant film (silicon nitride film) 103 are deposited. By a patterning with a photoresist 104, the silicon oxide film 102 and the silicon nitride film 103 are partially removed. After the photoresist 104 has been removed, an element separation region 106 is formed. With the silicon nitride film 103 as a mask, ion-implantation 107 with boron is performed. The ion- implantation is performed with the energy in a range wherein ion projection range is smaller that the total thickness of the silicon nitride film 103 and the silicon oxide film 102. After the completion of ion-implantation for forming a guttering site, the silicon nitride film 103 and the silicon oxide film 102 are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a gettering technique for removing contaminants which may deteriorate the element characteristics of a semiconductor device from an element region.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, it has been known that heavy metal contaminants such as Fe and Ni are mixed during various manufacturing processes and adversely affect element characteristics, thereby lowering the yield of semiconductor devices. ing.

As a technique for removing the heavy metal contaminants from the element region so that the element characteristics are not adversely affected, a crystal defect or a polycrystalline silicon film is formed on the back surface of the semiconductor substrate, or a high-concentration phosphorus is diffused. Accordingly, a gettering technique has been used to prevent the semiconductor element from being adversely affected as a contaminant trapping place (gettering site).

As a gettering technique, a semiconductor substrate is provided with gettering ability. For example, as shown in FIG. 2, a polycrystalline silicon film 202 is adhered to the back side of a semiconductor substrate 201, and A method is used in which a contaminant introduced into a semiconductor element in the film 202 is moved by thermal diffusion and taken into the polycrystalline silicon 202 so that the semiconductor element is not adversely affected.

However, in this conventional method, it is necessary to diffuse contaminants introduced from the surface of the substrate to gettering sites on the back surface of the substrate mainly by thermal diffusion.

With the recent miniaturization and high integration of semiconductor devices, the heat treatment during the semiconductor manufacturing process has been shortened and the temperature has been reduced, and contaminants have been sufficiently diffused from the semiconductor element region to the gettering site. Is no longer possible. For this reason, even if the diffusion distance of the contaminant is short, it is important that the gettering site exists near the semiconductor element so that the gettering can exert a sufficient effect.

As an example in which a gettering site is formed in the vicinity of a semiconductor element, for example, Japanese Patent Application Laid-Open No. 8-8262 discloses a field oxide film 302 at a position away from a pn junction of an element region as shown in FIG. A method of providing a gettering site in a region directly below has been proposed.

In this conventional manufacturing method, the semiconductor substrate 30
After patterning an oxidation resistant film on 1, an oxide film is formed on the entire surface, and this oxide film is anisotropically etched to form a sidewall oxide film on the side wall of the oxidation resistant film. A crystal defect 305 serving as a gettering site is formed in the semiconductor substrate using the oxidation resistant film and the sidewall oxide film as a mask.
Thereafter, the semiconductor substrate is thermally oxidized using the oxidation-resistant film as a mask to form the element isolation region 302. After that, a gate electrode 304 and a side wall 303 are formed to manufacture a semiconductor device.

On the other hand, LOCOS in order to electrically separate the elements each other on the semiconductor device (Loc al O xidat
ion of S ilion) technology for dividing oxidizing the silicon substrate that the method has been used.

However, this method alone does not provide sufficient isolation between elements, so that a technique called a "channel stopper" is also used. Regarding this technology, for example, a document (S. Wolf, SILICON PROCES)
SING FOR VLSIERA VOLUME I
I, published by LATTICE PRESS). This technique will be described with reference to FIG.

As a channel stopper, arsenic and phosphorus are implanted into the PMOS and boron is implanted into the NMOS below the element isolation region (405 in FIG. 4). By forming ions having a conductivity type opposite to that of a channel formed at the time of the MOS operation in the lower portion of the element isolation region 402, electric conduction through the lower portion of the element isolation region during the MOS operation is prevented. There is a purpose to prevent. At this time, the ion implantation is performed at a dose of 1 × 10 ¹² to 1 × 10 ¹³ atoms / cm.
² , which has no gettering effect due to its low concentration. However, in order to achieve the effect, higher concentration ion implantation is required.

[0012]

However, the above-mentioned prior art has the following problems.

As a first problem, the above-mentioned Japanese Patent Application Laid-Open No. 8-82
In the manufacturing method described in JP-A-62-62, it is necessary to form a crystal defect in a semiconductor substrate after forming an oxide film serving as a sidewall in order to form a crystal defect at a position away from an element region. This means that the number of steps for manufacturing the semiconductor device is increased, and the manufacturing cost is increased.

Further, as a second problem, when a channel stopper formed immediately below LOCOS is made to have a high concentration to give a gettering effect, the above-mentioned reference (S.
ILICON PROCESSING FOR VLS
As described in I ERA VOLUME II), a large capacitance is generated between the source / drain and the substrate, and the breakdown voltage at the junction between the source / drain and the semiconductor substrate is reduced.

Accordingly, the present invention has been made in view of the above problems, and has as its object to minimize the number of manufacturing steps and to have no adverse effect on a semiconductor element.
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a gettering site can be provided below an element isolation region.

[0016]

In order to achieve the above object, a method of manufacturing a semiconductor substrate according to the present invention comprises the steps of: depositing a film having oxidation resistance on a semiconductor substrate; Removing the oxide film, using the oxidation-resistant film as a mask, oxidizing the semiconductor substrate to form an element isolation region, and performing ion implantation using the oxidation-resistant film as a mask.

The ion implantation energy at this time is characterized in that the projected range of the ions does not exceed the thickness of the oxidation-resistant film.

[0018]

Embodiments of the present invention will be described below. In a preferred embodiment of the method for manufacturing a semiconductor device of the present invention, in a preferred embodiment, (a) a step of depositing a film having oxidation resistance on a semiconductor substrate (see FIG. 1A)
And (b) a step of partially removing the oxidation resistant film (FIG. 1)
(B)) and (c) forming a device isolation region by oxidizing the semiconductor substrate using the oxidation-resistant film as a mask (FIG. 1)
(C)) and (d) a step of performing ion implantation using the oxidation-resistant film as a mask (see FIG. 1 (d)).

In the embodiment of the present invention, after the element isolation region is formed using the oxidation-resistant film as a mask, high-concentration ion implantation is performed using the oxidation-resistant film as a mask. Oxidation progresses to the point where the oxide film becomes a bird's beak (bird's beak) (Figure 1)
(C)), and the ion implantation energy is set so that the projected range of the ions is equal to or less than the thickness of the oxidation-resistant film. Create an area.

Thereafter, by removing the oxidation-resistant film, a gettering site can be provided immediately below the element isolation film by increasing the number of steps of only the ion implantation step. Since it is formed at least apart from the region of the semiconductor element by the width of the bird's beak, it does not adversely affect the driving of the semiconductor element.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing the steps of a manufacturing method according to an embodiment of the present invention. First, as shown in FIG. 1A, a silicon oxide film 102
Subsequently, a silicon nitride film 103 which is an oxidation resistant film is deposited.

Subsequently, as shown in FIG. 1B, by patterning using a photoresist 104, the silicon oxide film 102 and the silicon nitride film 103 are partially removed to expose the semiconductor substrate 101. Is implanted in order to form a channel stopper in the presence of the above. The implantation energy at this time depends on the thickness of the element isolation region to be formed next. For example, when the thickness of the element isolation region is 300 nm, it is 100 keV, and the implantation dose is 10 ¹² to 10 ¹³ atoms / cm ^2. It is. At this time, the silicon oxide film 102 and the silicon nitride film 103 are not limited to specific thicknesses. Normally, the silicon oxide film 102 plays a role of stress relaxation at the time of oxidation, and the silicon oxide film 102 does not need to be present as long as crystal defects due to stress do not occur in the semiconductor substrate.

Subsequently, as shown in FIG. 1C, after removing the photoresist 104, an oxidation treatment is performed at about 1000 ° C. to form an element isolation region 106. At this time, due to the effect of the silicon nitride film 103, oxidation is
03, forming a so-called bird's beak.

Subsequently, as shown in FIG. 1D, boron ion implantation 10 is performed using the silicon nitride film 103 as a mask.
Perform Step 6. The energy of the ion implantation is set so that the projected range of the ions is smaller than the total thickness of the silicon nitride film 103 and the silicon oxide film 102. Specifically, for example, when the silicon nitride film 103 is 200 nm and the silicon oxide film 102 is 20 nm, the implantation energy 4
0 keV or less. When implantation is performed with such energy, as shown in the drawing, the phenomenon that the oxide film 105 for element isolation gradually becomes thinner toward the semiconductor element portion due to bird's beak, and the element formation region Region 107 having a partially high impurity concentration
Are formed, which serve as gettering sites for metal contaminants.

Although the region 107 is shown as a portion subjected to ion implantation, the structure is exactly the same as that shown in FIG. 1C and does not hinder the driving of the semiconductor device. The dose amount of the ion implantation is 10 ¹⁴ atoms.
/ Cm ² , in the semiconductor substrate 101,
Although crystal defects caused by implantation are not introduced, when crystal defects themselves are used as gettering sites, implantation may be performed at a higher concentration.

In this embodiment, boron is used as an example of the ion species to be implanted, but boron ion or phosphorus may be used. However, when ions having the opposite conductivity are implanted as a channel stopper, the concentration of the implantation needs to be increased correspondingly so that gettering has an effect. Even in this case, since the implantation region formed for gettering is only a part, the effect of the channel stopper is not canceled.

Subsequently, as shown in FIG. 1E, after the ion implantation for forming the gettering site is completed, the silicon nitride film 103 and the silicon oxide film 102 are removed. Then, a device may be manufactured by manufacturing a gate electrode and a wiring. Metal contaminants mixed during device fabrication during device fabrication are captured by the heat treatment process during device fabrication at the gettering sites formed according to the present embodiment.

In this embodiment, the number of steps is increased by only one step of ion implantation, and the number of steps is reduced as compared with the conventional example.

[0030]

As described above, according to the present invention,
There is an effect that a gettering site can be provided below the element isolation region with a minimum number of manufacturing steps and without adversely affecting the semiconductor element. The reason is that, in the present invention, ion implantation is performed using an oxidation-resistant film (for example, a silicon nitride film) used when forming an oxide film for element isolation as a mask. The range is set so that the range does not exceed the thickness of the oxidation-resistant film, and a bird's beak is used at the time of forming the element isolation film.Therefore, an ion-implanted layer is formed at a position away from the element isolation end. It is because it becomes.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view of a semiconductor device for explaining a conventional technique.

FIG. 3 is a cross-sectional view of a semiconductor device for explaining a conventional technique.

FIG. 4 is a cross-sectional view of a semiconductor device for explaining a conventional technique.

[Explanation of symbols]

 101, 201, 301, 404 Semiconductor substrate 102 Silicon oxide film 103 Silicon nitride film 104 Photo resist 105 Ion implantation for channel stopper 106, 302, 402 Element isolation silicon oxide film 107 Ion implantation 108 Schematically shown ion implantation region 109, 303,403 Side wall 110,304,404 Gate electrode 202 Polycrystalline silicon 305 Crystal defect 405 Channel stopper ion implantation region

Claims (6)

[Claims] A step of depositing a film having an oxidation-resistant property on a semiconductor substrate; and a step of partially removing the oxidation-resistant film. A method for manufacturing a semiconductor device, comprising: oxidizing to form an element isolation region, and then performing ion implantation using the oxidation-resistant film as a mask. 2. A method comprising: depositing a film having oxidation resistance on a semiconductor substrate; and partially removing the oxidation resistant film and the semiconductor substrate, wherein the oxidation resistant film is used as a mask. A method of manufacturing a semiconductor device, comprising: oxidizing a semiconductor substrate to form an element isolation region, and then performing ion implantation using the oxidation-resistant film as a mask. 3. A step of depositing a film having an oxidation-resistant property on a semiconductor substrate, and after partially removing the oxidation-resistant film and the semiconductor substrate,
A method of manufacturing a semiconductor device, comprising: depositing an insulating film to form an element isolation region; and then performing ion implantation using the oxidation-resistant film as a mask. 4. The ion implantation according to claim 1, wherein the implantation energy is set so that the projected range of the ions does not exceed the thickness of the oxidation-resistant film.
3. The method for manufacturing a semiconductor device according to any one of 3. 5. An ion implantation is performed using an oxidation resistant film used for forming an insulating film for element isolation as a mask, wherein the implantation energy is such that the projected range of the ion is a film of the oxidation resistant film. A thickness not exceeding the thickness, an ion-implanted layer is formed at a position distant from the element isolation end by utilizing the shape of the insulating film at the time of forming the element isolation insulating film, and this is set as a gettering site. A method for manufacturing a semiconductor device. 6. The method according to claim 5, wherein the oxidation-resistant film is a silicon nitride film.