JP3250298B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device which is an N-type transistor and a P-type transistor.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device is shown in FIG.
(A) to FIG. 2 (e). This step will be described sequentially. Note that both N-type and P-type transistors are LDD transistors (Light
(ly Doped Drain transistor) structure will be described.

[0003] First, as shown in FIG.
An oxide film is formed thereon to a thickness of 30 nm, a first silicon nitride film is formed thereon, and the first silicon nitride film in a region to be an N well 215 is removed by photo and etching. Then, the N well 215 is formed on the semiconductor substrate 201.
Is formed by ion implantation at 1 × 10
Drive in at about ¹³ atoms / cm ² . Phosphorus does not enter the region to be the P well 214 because the first silicon nitride film serves as a mask. Then, it is oxidized in a steam atmosphere at 1000 ° C. The first silicon nitride film is not oxidized under the first silicon nitride film because the first silicon nitride film serves as a mask. Then, the first silicon nitride film is removed and boron is ion-implanted into a region of 1 × 10 ¹³ at to form the P well 214 by ion implantation.
about oms / cm ² . Then, heat treatment is performed for about 10 hours in a dry atmosphere at 1100 ° C. to diffuse the phosphorus and boron to form the P well 214 and the N well 215. Next, a second silicon nitride film is formed on the semiconductor substrate 201 in a predetermined shape. Then, thermal oxidation is performed to form a field insulating film 202. The field insulating film 2
02 is formed in a thickness of about 600 nm to 800 nm. The second silicon nitride film is removed, and a first insulating film 203 is formed on the semiconductor substrate 201 by a thermal oxidation method. For example, oxidation is performed in a steam atmosphere at 850 ° C. The first insulating film 203 is used as a gate insulating film of a transistor. Then, in order to control the threshold value of the transistor, a conductive impurity such as phosphorus, arsenic, or boron is used in an amount of 1 × 10 ¹¹ to 1 × 10 ¹² by ion implantation.
Atoms · cm ⁻² is implanted into the semiconductor substrate 201. Then, a first polycrystalline silicon film 2 is formed on the field insulating film 202 and the first insulating film 203 by a CVD method.
04 is formed to a thickness of about 400 nm. Normally, monosilane gas is thermally decomposed at about 620 ° C. to deposit the first polycrystalline silicon film 204. Then, unnecessary portions of the first polycrystalline silicon film 204 are removed by a photo and etching method. This is used as a gate electrode. Then, a first resist mask 205 is formed in a region of the semiconductor substrate 201 to be a P-type transistor. Then, 1 × 10 ¹³ to 1 × 10 ¹⁴ is formed by ion implantation in order to form an N-type drain and source 206 having a low impurity concentration in a region to be an N-type transistor of the semiconductor substrate 201.
Phosphorus is implanted at about atoms · cm ⁻² . Then, the first resist mask 205 is removed.

[0004] Next, as shown in FIG.
First, a second resist mask 207 is formed in a region 01 to be the N-type transistor. And the semiconductor substrate 20
1 × 10 ¹³ to 1 × 10 ¹⁴ at using an ion implantation method to form a P-type drain and source 208 having a low impurity concentration in a region to be the P-type transistor 1
About oms · cm ⁻² boron is implanted. And the second
The resist mask 207 is removed.

Next, as shown in FIG. 2C, the first insulating film 2 is formed.
03 and a second insulating film 209 is formed on the first polycrystalline silicon film 204. It would be appropriate to form a silicon oxide film of about 400 nm by the CVD method. Then, the second insulating film 209 is subjected to isotropic etching to
Etching is performed so that only the side wall of the polycrystalline silicon film 204 is left. Then, a third resist mask 210 is formed on the semiconductor substrate 201 in a region to be the P-type transistor. Then, an ion implantation method is used to form an N-type drain and source 211 having a high impurity concentration in a region to be the N-type transistor of the semiconductor substrate 201.
Implant phosphorus or arsenic at least 1 × 10 ¹⁵ atoms · cm ⁻² . Since the second insulating film 209 on the side wall of the first polycrystalline silicon film 204 serves as a mask, the second insulating film 2
No phosphorus or arsenic is implanted into the semiconductor substrate 201 below the area 09. Then, the third resist mask 210 is removed.

Next, as shown in FIG.
A fourth resist mask 212 is formed in a region 01 of the N-type transistor. And the semiconductor substrate 20
1 × 10 ¹⁵ atoms · cm using an ion implantation method to form a P-type drain and source 213 having a high impurity concentration in a region where the P-type transistor 1 is to be formed.
^{-Inject 2} or more boron. The first polycrystalline silicon film 20
Since the second insulating film 209 on the side wall of No. 4 serves as a mask,
Boron is not implanted into the semiconductor substrate 201 below the second insulating film 209. Then, the fourth resist mask 212 is removed.

Finally, as shown in FIG. 2E, the fourth resist mask 212 is removed to complete the semiconductor device.

Further, an SD transistor (Single)
In the case of a drain transistor) structure, the drain and source 206 and 208 having a low impurity concentration and the second
No insulating film 209 is formed.

The above process is a conventional method for manufacturing a semiconductor device.

[0010]

However, in the above-mentioned conventional technique, when forming a drain and a source with a low impurity concentration and a drain and a source with a high impurity concentration in an N-type transistor and a P-type transistor, respectively, separate resists are used. Since the mask is formed on the semiconductor substrate, there is a problem that the number of manufacturing steps is very large. The fact that the number of manufacturing steps is large means that the number of defects due to dust and misalignment of the mask during photolithography increases and the number of defects increases. Accordingly, the present invention is intended to solve such a problem. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the drain and source of an N-type transistor and a P-type transistor can be formed in a very small number of manufacturing steps. Is to provide.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a transistor of a first conductivity type;
A method of manufacturing a semiconductor device having a transistor of a second conductivity type opposite to the conductivity type of (a), wherein (a) forming a gate insulating film on a semiconductor substrate; and (b) the gate insulating film. Forming a gate electrode of the first conductivity type transistor and a gate electrode of the second conductivity type transistor thereon; and (c) forming a first mask on the second conductivity type transistor formation region. (D) implanting the first conductivity type impurity into the first conductivity type transistor forming region to form the first conductivity type impurity;
(E) removing the first mask; and (f) forming a second mask on the first conductive type transistor forming region. g) implanting the second conductivity type impurity into the second conductivity type transistor formation region;
(H) removing the second mask; and (i) forming the gate insulating film, the first conductivity type transistor, and the second conductivity type transistor. Forming a first insulating film so as to cover the gate electrode; and (j) etching the first insulating film,
The first conductive type transistor and the second conductive type transistor may include the first conductive type transistor on the side wall of the gate electrode.
(K) implanting an impurity of the second conductivity type to form a third impurity region in the transistor formation region of the first conductivity type, and Forming a fourth impurity region in the transistor formation region of (a), (l) forming a third mask on the transistor formation region of the second conductivity type, and (m) forming the third impurity region. By implanting the impurity of the first conductivity type at a higher concentration than the impurity concentration of the region deeper than the third impurity region, a fifth impurity region is formed in the transistor formation region of the first conductivity type. And a step of forming

[0012]

[0013]

[0014]

[0015]

[0016]

1A to 1D show a first embodiment of the present invention.
It is a principal sectional view for every process of the manufacturing method of the semiconductor device in the Example of FIG. In all the drawings of the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. Hereinafter, description will be made in order according to FIGS. 1A to 1D.

First, as shown in FIG.
An oxide film is formed thereon to a thickness of 30 nm, a first silicon nitride film is formed thereon, and the first silicon nitride film in a region to be the N well 115 is removed by photo and etching. Then, the N well 115 is formed on the semiconductor substrate 101.
Is formed by ion implantation at 1 × 10
Drive in at about ¹³ atoms / cm ² . Phosphorus does not enter the region to be the P well 114 because the first silicon nitride film serves as a mask. Then, it is oxidized in a steam atmosphere at 1000 ° C. The first silicon nitride film is not oxidized under the first silicon nitride film because the first silicon nitride film serves as a mask. Then, the first silicon nitride film is removed, and boron is ion-implanted in a region of 1 × 10 ¹³ at to form the P well 114 by ion implantation.
about oms / cm ² . Then, heat treatment is performed for about 10 hours in a dry atmosphere at 1100 ° C. to diffuse the phosphorus and boron to form the P well 114 and the N well 115. Next, a second silicon nitride film is formed on the semiconductor substrate 101 in a predetermined shape. Then, thermal oxidation is performed to form the field insulating film 102. The field insulating film 102
Is formed to a thickness of about 600 nm to 800 nm. The second silicon nitride film is removed, and a first insulating film 103 is formed on the semiconductor substrate 101 by a thermal oxidation method. For example, 8
Oxidizes in a steam atmosphere at 50 ° C. The first insulating film 103 is used as a gate insulating film of a semiconductor device.
Then, in order to control the threshold value of the transistor, a conductive impurity such as phosphorus, arsenic, or boron is ion-implanted, for example, from 1 × 10 ¹¹ to 1 × 10 ¹² atoms.
^-Implant into the semiconductor substrate 201 by about cm ^-2 . Then, the field insulating film 102 and the first insulating film 103
The first polycrystalline silicon film 104 is formed on the
It is formed to a thickness of about 0 nm. Normally monosilane gas at 620 ° C
The first and second polycrystalline silicon films 104 are deposited by thermal decomposition before and after. Then, unnecessary portions of the first polycrystalline silicon film 104 are removed by a photo and etching method.
This is used as a gate electrode.

Next, as shown in FIG.
01 × 10 ¹⁵ atoms using the ion implantation method
Arsenic is implanted at a dose of s / cm ² to 3 × 10 ¹⁵ atoms / cm ² to form an N-type drain and source 105 having a high impurity concentration. The driving energy is 40 ke
A degree of v would be appropriate.

This is used as the N-type drain and source of the N-type transistor.

Next, as shown in FIG.
First, a first resist mask 106 is formed in a region 01 to be the N-type transistor. And the semiconductor substrate 10
Boron is implanted at a dose of 4 × 10 ¹⁵ atoms / cm ² or more into a region to be a P-type transistor by ion implantation. At this time, the impurity is implanted deeper than the N-type drain and source 105 having a higher impurity concentration. An implantation energy of about 60 keV would be appropriate.

Finally, as shown in FIG. 1D, the first resist mask 106 is removed.

The above manufacturing steps are the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

As described above, an N-type impurity having a relatively high impurity concentration is implanted into both sides of the region for forming the N-type transistor and the region for forming the P-type transistor. By deeply implanting a P-type impurity having a higher impurity concentration than the impurity, the N-type impurity can be used as an N-type drain and source of the N-type transistor. In the region to be the P-type transistor, the concentration of the P-type impurity is higher than that of the N-type impurity.
The type impurity is canceled out to form a P-type impurity region. Therefore, the P-type impurity region corresponds to the P-type transistor of the P-type transistor.
It can be used as a mold drain and source.

As described above, according to the method of manufacturing a semiconductor device of the present invention, the drain and source of the N-type SD transistor and the P-type SD transistor can be formed with a very small number of manufacturing steps.

In this embodiment, an N-type impurity having a relatively high impurity concentration is implanted into both sides of a region to be an N-type transistor and a region to be a P-type transistor. Also shown is a case where a P-type impurity having a high impurity concentration is deeply implanted. However, when the polarity is reversed, that is, a P-type impurity having a relatively high impurity concentration is implanted into both sides of the region to be an N-type transistor and the region to be a P-type transistor, and then the P-type impurity is injected into the region to be an N-type transistor. This is also possible even when an N-type impurity having a high impurity concentration is deeply implanted.

FIGS. 3A to 3E are main cross-sectional views for each step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. In all the drawings of the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. Hereinafter, FIGS. 3A to 3E
Will be described in order.

First, as shown in FIG.
An oxide film is formed thereon to a thickness of 30 nm, a first silicon nitride film is formed thereon, and the first silicon nitride film in a region where the N well 315 is to be formed is removed by photo-etching. Then, the N well 315 is formed on the semiconductor substrate 301.
Is formed by ion implantation at 1 × 10
Drive in at about ¹³ atoms / cm ² . Phosphorus does not enter the region to be the P well 314 because the first silicon nitride film serves as a mask. Then, it is oxidized in a steam atmosphere at 1000 ° C. The first silicon nitride film is not oxidized under the first silicon nitride film because the first silicon nitride film serves as a mask. Then, the first silicon nitride film is removed and boron is ion-implanted into a region of 1 × 10 ¹³ at to form the P well 314 by ion implantation.
about oms / cm ² . Then, heat treatment is performed for about 10 hours in a dry atmosphere at 1100 ° C. to diffuse the phosphorus and boron to form the P well 314 and the N well 315. Next, a second silicon nitride film is formed on the semiconductor substrate 301 in a predetermined shape. Then, thermal oxidation is performed to form a field insulating film 302. The field insulating film 302
Is formed to a thickness of about 600 nm to 800 nm. The second silicon nitride film is removed, and a first insulating film 303 is formed on the semiconductor substrate 301 by a thermal oxidation method. For example, 8
Oxidizes in a steam atmosphere at 50 ° C. The first insulating film 303 is used as a gate insulating film of a semiconductor device.
Then, in order to control the threshold value of the transistor, a conductive impurity such as phosphorus, arsenic, or boron is ion-implanted, for example, from 1 × 10 ¹¹ to 1 × 10 ¹² atoms.
^{Implanting the} semiconductor substrate 301 into about cm ⁻² . Then, the field insulating film 302 and the first insulating film 303
The first polycrystalline silicon film 304 is formed on the
It is formed to a thickness of about 0 nm. Normally monosilane gas at 620 ° C
The first polycrystalline silicon film 304 is deposited by thermal decomposition before and after. Then, unnecessary portions of the first polycrystalline silicon film 304 are removed by a photo and etching method.
This is used as a gate electrode. Then, 5 × 10 ¹² atoms are applied to the semiconductor substrate 301 by ion implantation.
Arsenic is implanted at a dose of 5 × 10 ¹³ atoms / cm ² to 5 × 10 ¹³ atoms / cm ² to form an N-type drain and source 305 having a low impurity concentration. The driving energy is 40k
An ev degree would be appropriate.

Next, as shown in FIG. 3B, the first insulating film 3 is formed.
03 and a second insulating film 306 is formed on the first polycrystalline silicon film 304. It would be appropriate to form a silicon oxide film of about 400 nm by the CVD method. Then, the second insulating film 306 is subjected to isotropic etching to
Etching is performed so that only the side wall of the polycrystalline silicon film 304 is left.

Next, as shown in FIG.
First, a first resist mask 307 is formed in a region 01 to be the P-type transistor. And the semiconductor substrate 30
In order to form an N-type drain and source 308 having a high impurity concentration in a region to be used as the N-type transistor 1 described above, 2 × 10 ¹⁵ atoms / cm ² by ion implantation.
Above, phosphorus is implanted. An implantation energy of about 70 keV would be appropriate. Since the second insulating film 306 on the side wall of the first polycrystalline silicon film 304 serves as a mask, phosphorus is not implanted into the semiconductor substrate 301 below the second insulating film 306. Then, the first resist mask 307 is formed.
Is removed.

Next, as shown in FIG.
First, a second resist mask 309 is formed in a region 01 to be the N-type transistor. And the semiconductor substrate 30
In order to form a P-type drain and source 310 having a high impurity concentration in a region to be the P-type transistor 1 described above, 2 × 10 ¹⁵ atoms / cm ² by ion implantation.
Thus, boron is implanted. At this time, boron is implanted deeper than the N-type drain and source 305 having a low impurity concentration. An implantation energy of about 70 keV would be appropriate. The second insulating film 306 is formed on the side wall of the first polycrystalline silicon film 304. However, since boron is more deeply implanted than the arsenic of the N-type drain and source 305 having a low impurity concentration, the P-type drain and source 31 having the high impurity concentration are diffused in the lateral direction.
0 surrounds the N-type drain and source 305 having a low impurity concentration.

Finally, as shown in FIG. 3E, the second resist mask 309 is removed.

The above-described manufacturing process is a method of manufacturing a semiconductor device according to the second embodiment of the present invention.

As described above, an N-type impurity having a low impurity concentration is implanted into both sides of the region for forming the N-type transistor and the region for forming the P-type transistor. By deeply implanting a P-type impurity having a high impurity concentration, the P-type impurity has a higher concentration than the N-type impurity having a low impurity concentration in a region to be formed as the P-type transistor. The thin N-type impurity is canceled out to form a P-type impurity region. Therefore, the P-type impurity region can be used as a drain and a source of the P-type transistor.

As described above, according to the method of manufacturing a semiconductor device of the present invention, the drain and source of the N-type LDD transistor and the P-type SD transistor can be formed with a very small number of manufacturing steps.

In this embodiment, an N-type impurity having a low impurity concentration is implanted into both sides of a region to be an N-type transistor and a region to be a P-type transistor. The case where a high concentration P-type impurity is deeply implanted is shown. However, when the polarity is reversed, that is, a P-type impurity having a low impurity concentration is implanted into both sides of the region to be an N-type transistor and the region to be a P-type transistor, and then the region to be an N-type transistor is more doped than the P-type impurity. This is possible even when deeply implanted heavily doped N-type impurities.

FIGS. 4A to 4E are main cross-sectional views for each step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention. In all the drawings of the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. Hereinafter, FIGS. 4 (a) to 4 (e)
Will be described in order.

First, as shown in FIG.
An oxide film is formed thereon to a thickness of 30 nm, a first silicon nitride film is formed thereon, and the first silicon nitride film in a region where the N well 415 is to be formed is removed by photo-etching. Then, the N well 415 is formed on the semiconductor substrate 401.
Is formed by ion implantation at 1 × 10
Drive in at about ¹³ atoms / cm ² . Phosphorus does not enter the region to be the P well 414 because the first silicon nitride film serves as a mask. Then, it is oxidized in a steam atmosphere at 1000 ° C. The first silicon nitride film is not oxidized under the first silicon nitride film because the first silicon nitride film serves as a mask. Then, the first silicon nitride film is removed and boron is ion-implanted in a region of 1 × 10 ¹³ at to form the P well 414 by ion implantation.
about oms / cm ² . Then, heat treatment is performed for about 10 hours in a dry atmosphere at 1100 ° C. to diffuse the phosphorus and boron to form the P well 414 and the N well 415. Next, a second silicon nitride film is formed on the semiconductor substrate 401 in a predetermined shape. Then, thermal oxidation is performed to form a field insulating film 402. The field insulating film 402
Is formed to a thickness of about 600 nm to 800 nm. The second silicon nitride film is removed, and a first insulating film 403 is formed on the semiconductor substrate 401 by a thermal oxidation method. For example, 8
Oxidizes in a steam atmosphere at 50 ° C. The first insulating film 403 is used as a gate insulating film of a semiconductor device.
Then, in order to control the threshold value of the transistor, a conductive impurity such as phosphorus, arsenic, or boron is ion-implanted, for example, from 1 × 10 ¹¹ to 1 × 10 ¹² atoms.
-Implant into the semiconductor substrate 401 at about cm ^-2 . Then, the field insulating film 402 and the first insulating film 403
The first polycrystalline silicon film 404 is formed on the
It is formed to a thickness of about 0 nm. Normally monosilane gas at 620 ° C
The first polycrystalline silicon film 404 is deposited by thermal decomposition before and after. Then, unnecessary portions of the first polycrystalline silicon film 404 are removed by a photo and etching method.
This is used as a gate electrode. Then, 5 × 10 ¹² ato is applied to the semiconductor substrate 401 by ion implantation.
Arsenic is implanted at a dose of 5 × 10 ¹³ atoms / cm ² to 5 × 10 ¹³ atoms / cm ² to form N-type drain and source 405 having a low impurity concentration. The driving energy is 40k
An ev degree would be appropriate.

Next, as shown in FIG.
A first resist mask 406 is formed in a region to be an N-type transistor 01. Then, boron is implanted at 2 × 10 ¹⁵ atoms / cm ² or more by ion implantation in order to form a P-type drain and a source 407 having a high impurity concentration in a region of the semiconductor substrate 401 to be the P-type transistor. . At this time, the impurity concentration of N
Boron is implanted deeper than the drain and source 305 of the mold. An implantation energy of about 70 keV would be appropriate. N-type drain and source 4 having a low impurity concentration
Since the boron is more deeply implanted than that of arsenic 05, the P-type drain and source 407 having a high impurity concentration by lateral diffusion surround the N-type drain and source 405 having a low impurity concentration.

Next, as shown in FIG. 4C, the first insulating film 4 is formed.
03 and a second insulating film 408 on the first polycrystalline silicon film 404. It would be appropriate to form a silicon oxide film of about 400 nm by the CVD method. Then, the second insulating film 408 is subjected to isotropic etching to form the first insulating film 408.
Etching is performed so that only the side wall of the polycrystalline silicon film 404 is left.

Next, as shown in FIG.
First, a second resist mask 409 is formed in a region 01 of the P-type transistor. And the semiconductor substrate 40
In order to form an N-type drain and source 410 having a high impurity concentration in a region to be used as the N-type transistor 1 described above, 2 × 10 ¹⁵ atoms / cm ² by ion implantation.
Above, phosphorus is implanted. An implantation energy of about 70 keV would be appropriate. Since the second insulating film 408 on the side wall of the first polycrystalline silicon film 404 serves as a mask, phosphorus is not implanted into the semiconductor substrate 401 below the second insulating film 408.

Finally, as shown in FIG. 4E, the second resist mask 409 is removed.

The above-described manufacturing process is a method of manufacturing a semiconductor device according to the third embodiment of the present invention.

As described above, an N-type impurity having a low impurity concentration is implanted into both sides of the region for forming the N-type transistor and the region for forming the P-type transistor. By deeply implanting a P-type impurity having a high impurity concentration, the P-type impurity has a higher concentration than the N-type impurity having a low impurity concentration in a region to be formed as the P-type transistor. The thin N-type impurity is canceled out to form a P-type impurity region. Therefore, the P-type impurity region can be used as a drain and a source of the P-type transistor.

As described above, by using the method for manufacturing a semiconductor device of the present invention, it is possible to form the drain and the source of the N-type LDD transistor and the P-type SD transistor in a very small number of manufacturing steps.

In this embodiment, an N-type impurity having a low impurity concentration is implanted into both sides of a region to be an N-type transistor and a region to be a P-type transistor. The case where a high concentration P-type impurity is deeply implanted is shown. However, when the polarity is reversed, that is, a P-type impurity having a low impurity concentration is implanted into both sides of the region to be an N-type transistor and the region to be a P-type transistor, and then the region to be an N-type transistor is more doped than the P-type impurity. This is possible even when deeply implanted heavily doped N-type impurities.

FIGS. 5A to 5E are main cross-sectional views for each step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. In all the drawings of the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. Hereinafter, FIGS. 5A to 5E
Will be described in order.

First, as shown in FIG. 5A, a semiconductor substrate 501 is formed.
An oxide film is formed thereon to a thickness of 30 nm, a first silicon nitride film is formed thereon, and the first silicon nitride film in a region to be an N well 515 is removed by photo and etching. Then, the N well 515 is placed on the semiconductor substrate 501.
Is formed by ion implantation at 1 × 10
Drive in at about ¹³ atoms / cm ² . Phosphorus does not enter the region to be the P well 514 because the first silicon nitride film serves as a mask. Then, it is oxidized in a steam atmosphere at 1000 ° C. The first silicon nitride film is not oxidized under the first silicon nitride film because the first silicon nitride film serves as a mask. Then, the first silicon nitride film is removed and boron is ion-implanted in a region of 1 × 10 ¹³ at to form the P well 514 by ion implantation.
about oms / cm ² . Then, heat treatment is performed for about 10 hours in a dry atmosphere at 1100 ° C. to diffuse the phosphorus and boron to form the P well 514 and the N well 515. Next, a second silicon nitride film is formed on the semiconductor substrate 501 in a predetermined shape. Then, thermal oxidation is performed to form a field insulating film 502. The field insulating film 502
Is formed to a thickness of about 600 nm to 800 nm. The second silicon nitride film is removed, and a first insulating film 503 is formed on the semiconductor substrate 501 by a thermal oxidation method. For example, 8
Oxidizes in a steam atmosphere at 50 ° C. The first insulating film 503 is used as a gate insulating film of a semiconductor device.
Then, in order to control the threshold value of the transistor, a conductive impurity such as phosphorus, arsenic, or boron is ion-implanted, for example, from 1 × 10 ¹¹ to 1 × 10 ¹² atoms.
-Implant into the semiconductor substrate 501 by about cm ^-2 . Then, the field insulating film 502 and the first insulating film 503
On the first polycrystalline silicon film 504 is deposited 40
It is formed to a thickness of about 0 nm. Normally monosilane gas at 620 ° C
The first polycrystalline silicon film 504 is deposited by thermal decomposition before and after. Then, unnecessary portions of the first polycrystalline silicon film 504 are removed by a photo and etching method.
This is used as a gate electrode. Then, 5 × 10 ¹² ato is applied to the semiconductor substrate 501 by ion implantation.
Arsenic is implanted at a dose of 5 × 10 ¹³ atoms / cm ² to 5 × 10 ¹³ atoms / cm ² to form N-type drain and source 505 having a low impurity concentration. The driving energy is 40k
An ev degree would be appropriate.

Next, as shown in FIG. 5B, the first insulating film 5 is formed.
03, and a second insulating film 506 is formed on the first polycrystalline silicon film 504. It would be appropriate to form a silicon oxide film of about 400 nm by the CVD method. Then, the second insulating film 506 is subjected to isotropic etching to
Etching is performed so that only the side wall of the polycrystalline silicon film 504 is left.

Next, as shown in FIG.
01 × 10 ¹⁵ atoms using the ion implantation method
Phosphorus is implanted at a dose of s / cm ² to 3 × 10 ¹⁵ atoms / cm ² to form N-type drain and source 507 having a high impurity concentration. The driving energy is 40 keV
The degree would be appropriate.

This is used as the N-type drain and source of the N-type transistor.

Next, as shown in FIG.
A first resist mask 508 is formed in a region to be an N-type transistor 01. Then, boron is implanted at 6 × 10 ¹⁵ atoms / cm ² or more by ion implantation in order to form a P-type drain and source 509 having a high impurity concentration in a region to be a P-type transistor of the semiconductor substrate 501. At this time, boron is implanted deeper than the N-type drain and source 507 having the higher impurity concentration.
An implantation energy of about 70 keV would be appropriate.
N-type drain and source 507 having a high impurity concentration
Since boron is more deeply implanted than that of arsenic, the P-type drain and source 509 having a higher impurity concentration surround the N-type drain and source 507 having a higher impurity concentration due to lateral diffusion.

Finally, as shown in FIG. 5E, the first resist mask 508 is removed.

The above manufacturing steps are the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

As described above, an N-type impurity having a low impurity concentration and an N-type impurity having a high impurity concentration are implanted into both sides of the region for forming the N-type transistor and the region for forming the P-type transistor. The N-type impurity having a low impurity concentration and the P-type impurity having a higher impurity concentration than the N-type impurity having a higher impurity concentration are deeply implanted into the region to be doped, so that the N-type impurity having a higher impurity concentration Since the concentration of the P-type impurity is higher than that of the P-type impurity, the N-type impurity having the higher impurity concentration is canceled out to form a P-type impurity region.
Therefore, the P-type impurity region can be used as a drain and a source of the P-type transistor.

As described above, by using the method of manufacturing a semiconductor device according to the present invention, it is possible to form the drain and source of the N-type LDD transistor and the P-type SD transistor with a very small number of manufacturing steps.

In this embodiment, an N-type impurity having a low impurity concentration and an N-type impurity having a high impurity concentration are implanted into both sides of a region to be an N-type transistor and a region to be a P-type transistor, and then a P-type transistor is formed. The case where the N-type impurity having a lower impurity concentration and the P-type impurity having a higher impurity concentration than the N-type impurity having a higher impurity concentration are deeply implanted into the region is shown. However, when the polarity is reversed, that is, a P-type impurity having a low impurity concentration and a P-type impurity having a high impurity concentration are implanted into both sides of a region to be an N-type transistor and a region to be a P-type transistor, and then an N-type transistor is formed. In the region, a P-type impurity having a lower impurity concentration and N having a higher impurity concentration than a P-type impurity having a higher impurity concentration are used.
This is possible even when the type impurity is deeply implanted.

FIGS. 6A to 6E are main cross-sectional views for each step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. In all the drawings of the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. Hereinafter, FIGS. 6A to 6E
Will be described in order.

First, as shown in FIG. 6A, a semiconductor substrate 601 is formed.
An oxide film is formed thereon to a thickness of 30 nm, a first silicon nitride film is formed thereon, and the first silicon nitride film in a region where the N well 615 is to be formed is removed by photo-etching. Then, the N well 615 is placed on the semiconductor substrate 601.
Is formed by ion implantation at 1 × 10
Drive in at about ¹³ atoms / cm ² . Phosphorus does not enter the region to be the P well 614 because the first silicon nitride film serves as a mask. Then, it is oxidized in a steam atmosphere at 1000 ° C. The first silicon nitride film is not oxidized under the first silicon nitride film because the first silicon nitride film serves as a mask. Then, the first silicon nitride film is removed and boron is ion-implanted in a region of 1 × 10 ¹³ at to form the P well 614 by ion implantation.
about oms / cm ² . Then, heat treatment is performed for about 10 hours in a dry atmosphere at 1100 ° C. to diffuse the phosphorus and boron to form the P well 614 and the N well 615. Next, a second silicon nitride film is formed on the semiconductor substrate 601 in a predetermined shape. Then, thermal oxidation is performed to form a field insulating film 602. The field insulating film 602
Is formed to a thickness of about 600 nm to 800 nm. The second silicon nitride film is removed, and a first insulating film 603 is formed on the semiconductor substrate 601 by a thermal oxidation method. For example, 8
Oxidizes in a steam atmosphere at 50 ° C. The first insulating film 603 is used as a gate insulating film of a semiconductor device.
Then, in order to control the threshold value of the transistor, a conductive impurity such as phosphorus, arsenic, or boron is ion-implanted, for example, from 1 × 10 ¹¹ to 1 × 10 ¹² atoms.
-Implant into the semiconductor substrate 601 at about cm ^-2 . Then, the field insulating film 602 and the first insulating film 603
The first polycrystalline silicon film 604 is deposited on the
It is formed to a thickness of about 0 nm. Normally monosilane gas at 620 ° C
The first polycrystalline silicon film 604 is deposited by thermal decomposition before and after. Then, unnecessary portions of the first polycrystalline silicon film 604 are removed by a photo and etching method.
This is used as a gate electrode.

Then, a first resist mask 605 is formed in a region of the semiconductor substrate 601 to be a P-type transistor. Then, 5 × 10 ¹² atoms / cm ² to 5 × 10
Arsenic is implanted at a dose of ¹³ atoms / cm ² to form an N-type drain and source 606 having a low impurity concentration. An implantation energy of about 40 keV would be appropriate.

Next, as shown in FIG.
A second resist mask 607 is formed in a region to be an N-type transistor 01. Then, an ion implantation method is used to form a P-type drain and source 608 having a low impurity concentration in a region to be a P-type transistor of the semiconductor substrate 601 by using an ion implantation method to form 5 × 10 ¹² atoms / cm ² to 5 ×
Boron is implanted at a dose of 10 ¹³ atoms / cm ² . An implantation energy of about 30 keV would be appropriate.

Next, as shown in FIG. 6C, the first insulating film 6 is formed.
03 and a second insulating film 609 is formed on the first polycrystalline silicon film 604. It would be appropriate to form a silicon oxide film of about 400 nm by the CVD method. Then, the second insulating film 609 is subjected to isotropic etching to
Etching is performed so that only the side wall of the polycrystalline silicon film 604 is left. Then, 1 × 10 ¹⁵ atoms / cm ² to 3 × 10 5
Boron is implanted at a dose of ¹⁵ atoms / cm ² to form a P-type drain and source 610 having a high impurity concentration. An implantation energy of about 30 keV would be appropriate.

Next, as shown in FIG.
A third resist mask 611 is formed in a region 01 of the P-type transistor. And the semiconductor substrate 60
Phosphorus is implanted at 4 × 10 ¹⁵ atoms / cm ² or more by ion implantation in order to form an N-type drain and source 612 having a high impurity concentration in a region to be one N-type transistor. At this time, phosphorus is implanted deeper than the P-type drain and source 610 having a higher impurity concentration.
An implantation energy of about 60 keV would be appropriate.
The P-type drain and source 610 having a high impurity concentration
Since phosphorus is implanted deeper than boron, the N-type drain and source 6 having a higher impurity concentration are formed by lateral diffusion.
Reference numeral 12 surrounds the P-type drain and source 610 having a high impurity concentration.

Finally, as shown in FIG. 6E, the third resist mask 611 is removed.

The above-described manufacturing process is a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention.

As described above, a P-type impurity having a high impurity concentration is implanted into both sides of the region for forming the N-type transistor and the region for forming the P-type transistor. By deeply implanting an N-type impurity having a higher impurity concentration than a P-type impurity, the N-type impurity has a higher concentration than the P-type impurity having a higher impurity concentration in a region to be the N-type transistor. The P-type impurity having a high impurity concentration is canceled out to form an N-type impurity region. Therefore, the N-type impurity region can be used as the N-type drain and source of the N-type transistor.

As described above, according to the method of manufacturing a semiconductor device of the present invention, an N-type LDD transistor and a P-type LDD
The drain and source of the transistor can be formed with a very small number of manufacturing steps.

In this embodiment, a P-type impurity having a high impurity concentration is implanted into both sides of a region to be an N-type transistor and a region to be a P-type transistor. The case where the N-type impurity having a higher impurity concentration than the impurity is deeply implanted is shown. However, when the polarity is reversed, that is, an N-type impurity with a high impurity concentration is implanted into both sides of a region to be an N-type transistor and a region to be a P-type transistor, and then a region with a high impurity concentration is injected into a region to be a P-type transistor. This is possible even when a P-type impurity having a higher impurity concentration than the impurity is deeply implanted.

Although the invention made by the present inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, but may be modified without departing from the scope of the invention. Of course you can.

[0069]

According to the present invention, the first conductive type impurity region having a relatively low impurity concentration is formed, and then the second conductive type impurity region having a relatively high impurity concentration is formed.
It is not necessary to separately form a resist mask for impurity ion implantation on a semiconductor substrate. That is, the number of manufacturing steps can be reduced. Since the number of manufacturing steps is small, defects due to dust and misalignment of a mask at the time of photolithography are reduced, so that defects are reduced and the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a main cross-sectional view for describing a first embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 2 is a main cross-sectional view for describing a conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 3 is a main cross-sectional view for describing a second embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.

FIG. 4 is a main cross-sectional view for describing a third embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.

FIG. 5 is a main cross-sectional view for describing a fourth embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.

FIG. 6 is a main cross-sectional view for describing a fifth embodiment of the method of manufacturing the semiconductor device according to the present invention in the order of steps.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 field insulating film 103 first insulating film 104 first polycrystalline silicon film 105 N-type drain and source with high impurity concentration 106 first resist mask 107 P-type drain and source with high impurity concentration 114 P well 115 N well 201 Semiconductor substrate 202 Field insulating film 203 First insulating film 204 First polycrystalline silicon film 205 First resist mask 206 N-type drain and source with low impurity concentration 207 Second resist mask 208 P-type with low impurity concentration Drain and source 209 Second insulating film 210 Third resist mask 211 N-type drain and source with high impurity concentration 212 Fourth resist mask 213 P-type drain and source with high impurity concentration 214 P well 215 N well 301 Semiconductor substrate 302 Field insulating film 303 First insulating film 304 First polycrystalline silicon film 305 N-type drain and source with low impurity concentration 306 Second insulating film 307 First resist mask 308 N-type drain and source with high impurity concentration 309 Second resist mask 310 P-type drain and source with high impurity concentration 314 P-well 315 N-well 401 Semiconductor substrate 402 Field insulating film 403 First insulating film 404 First polycrystalline silicon film 405 N-type drain with low impurity concentration And source 406 first resist mask 407 P-type drain and source with high impurity concentration 408 second insulating film 409 second resist mask 410 N-type drain and source with high impurity concentration 414 P well 415 N well 501 Semiconductor substrate 50 2 Field insulating film 503 First insulating film 504 First polycrystalline silicon film 505 N-type drain and source with low impurity concentration 506 Second insulating film 507 N-type drain and source with high impurity concentration 508 First resist mask 509 Impurity P-type drain and source 514 P-well 515 N-well 601 Semiconductor substrate 602 Field insulating film 603 First insulating film 604 First polycrystalline silicon film 605 First resist mask 606 N-type drain and source with low impurity concentration 607 Second resist mask 608 P-type drain and source with low impurity concentration 609 Second insulating film 610 P-type drain and source with high impurity concentration 611 Third resist mask 612 N-type drain and source with high impurity concentration 614 P Well 61 5 N well

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-58-74070 (JP, A) JP-A-62-160755 (JP, A) JP-A-63-217655 (JP, A) JP-A-63-217655 252461 (JP, A) JP-A-61-56448 (JP, A) JP-A-3-102867 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8238 H01L 27 / 092

Claims (1)

(57) [Claims] 1. A method for manufacturing a semiconductor device having a transistor of a first conductivity type and a transistor of a second conductivity type opposite to the first conductivity type, comprising: Forming a gate insulating film; (b) forming a gate electrode of the transistor of the first conductivity type and a gate electrode of the transistor of the second conductivity type on the gate insulating film; Forming a first mask on the two-conductivity-type transistor formation region; and (d) implanting the first-conductivity-type impurity into the first-conductivity-type transistor formation region.
(E) removing the first mask; and (f) forming a second mask on the first conductive type transistor forming region. g) implanting the second conductivity type impurity into the second conductivity type transistor formation region;
(H) removing the second mask; and (i) forming the gate insulating film, the first conductivity type transistor, and the second conductivity type transistor. Forming a first insulating film so as to cover the gate electrode; and (j) etching the first insulating film,
The first conductive type transistor and the second conductive type transistor may include the first conductive type transistor on the side wall of the gate electrode.
(K) implanting an impurity of the second conductivity type to form a third impurity region in the transistor formation region of the first conductivity type, and Forming a fourth impurity region in the transistor formation region of (a), (l) forming a third mask on the transistor formation region of the second conductivity type, and (m) forming the third impurity region. By implanting the impurity of the first conductivity type at a higher concentration than the impurity concentration of the region deeper than the third impurity region, a fifth impurity region is formed in the transistor formation region of the first conductivity type. Forming a semiconductor device, and a method for manufacturing a semiconductor device.