JP3423161B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3423161B2 JP3423161B2 JP27004196A JP27004196A JP3423161B2 JP 3423161 B2 JP3423161 B2 JP 3423161B2 JP 27004196 A JP27004196 A JP 27004196A JP 27004196 A JP27004196 A JP 27004196A JP 3423161 B2 JP3423161 B2 JP 3423161B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- diffusion layer
- conductivity
- type
- drain diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title description 11
- 238000000034 method Methods 0.000 title description 7
- 238000009792 diffusion process Methods 0.000 claims description 65
- 239000000758 substrate Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 10
- -1 Arsenic ions Chemical class 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置とその
製造方法に関するものであり、更に詳しく言えば、ＬＣ
Ｄドライバーに用いる高電源電圧（ＨＶ−ＶDD）用の高
耐圧ＭＯＳトランジスタのトランジスタ性能の向上を図
る技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, more specifically, an LC device.
The present invention relates to a technique for improving the transistor performance of a high voltage MOS transistor for a high power supply voltage (HV-VDD) used in a D driver.
【０００２】[0002]
【従来の技術】高耐圧ＭＯＳトランジスタは、例えば５
Ｖ系の通常ＭＯＳトランジスタと同一チップ上に混載さ
れている。以下で、従来例に係わる半導体装置について
説明する。図７に示すＬＤＤ型高耐圧ＭＯＳトランジス
タの断面図を参照しながら説明すると、Ｎ型の半導体基
板（ＮSub ）５１内に形成されたＰ型ウエル５２上にゲ
ート絶縁膜５３を介してゲート電極５４が形成されてい
る。そして、前記ゲート電極５４の一端に隣接するよう
にＮ＋型ソース拡散層５５が形成されており、チャネル
領域５６を介して前記ソース拡散層５５と対向してＮ−
型ドレイン拡散層５７が形成され、更にゲート電極５４
の他端から離間され、かつＮ−型ドレイン拡散層５７に
含まれるようにＮ＋型ドレイン拡散層５８が形成されて
いる。2. Description of the Related Art A high voltage MOS transistor is, for example,
It is mixedly mounted on the same chip as the V-type normal MOS transistor. The semiconductor device according to the conventional example will be described below. Explaining with reference to the sectional view of the LDD type high voltage MOS transistor shown in FIG. 7, a gate electrode 54 is formed on a P type well 52 formed in an N type semiconductor substrate (NSub) 51 via a gate insulating film 53. Are formed. An N + type source diffusion layer 55 is formed so as to be adjacent to one end of the gate electrode 54 and faces the source diffusion layer 55 via a channel region 56 to form N−.
The drain drain layer 57 is formed, and the gate electrode 54 is formed.
The N + type drain diffusion layer 58 is formed so as to be separated from the other end and included in the N− type drain diffusion layer 57.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、前記ト
ランジスタのＰ型ウエル５２は、工程の増加を抑えるた
め、５Ｖ系ＭＯＳトランジスタ用のＰ型ウエルと同一工
程で作成している。従って、Ｐ型ウエルは１種類しか持
っていなかった。高耐圧ＭＯＳトランジスタ用のウエル
は、降伏電圧を高くするために、ウエル濃度を低くし、
拡散領域を深く形成する必要がある。However, the P-type well 52 of the transistor is formed in the same step as the P-type well for the 5V MOS transistor in order to suppress an increase in the number of steps. Therefore, there was only one P-type well. The well for the high breakdown voltage MOS transistor has a low well concentration in order to increase the breakdown voltage,
It is necessary to form the diffusion region deep.
【０００４】一方、５Ｖ系ＭＯＳトランジスタ用のウエ
ルは、短チャネル化のため、ウエルを高濃度とし、ま
た、高集積化のため拡散領域を浅くする必要がある。従
って、ウエルを１種類しか持たなければ最適化されたウ
エル濃度プロファイルとはならず、トランジスタ性能が
制限される結果となっていた。従って、本発明では製造
工程数の増大を招くことなく、高耐圧ＭＯＳトランジス
タのトランジスタ性能の向上を可能とする半導体装置と
その製造方法を提供することを目的とする。On the other hand, in the well for 5V type MOS transistor, it is necessary to make the well high concentration in order to shorten the channel and to make the diffusion region shallow for high integration. Therefore, if only one type of well is provided, the well concentration profile will not be optimized and the transistor performance will be limited. Therefore, it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof which can improve the transistor performance of a high breakdown voltage MOS transistor without increasing the number of manufacturing steps.
【０００５】[0005]
【課題を解決するための手段】そこで、本発明は一導電
型の半導体基板内に一導電型の不純物と逆導電型の不純
物をイオン注入し、同時に拡散することで逆導電型のウ
エル領域内に極低濃度の逆導電型拡散層を形成し、前記
基板上に低濃度の逆導電型ドレイン拡散層をイオン注入
により形成する。次に、前記基板全面にゲート絶縁膜を
介して前記ドレイン拡散層上方にオーバーラップするゲ
ート電極を形成した後に、前記ゲート電極の一端に隣接
する高濃度の逆導電型ソース拡散層と、前記ゲート電極
の他端から離間され、かつ前記低濃度の逆導電型ドレイ
ン拡散層に含まれる高濃度の逆導電型ドレイン拡散層と
をイオン注入により形成するものである。Therefore, according to the present invention, an impurity of one conductivity type and an impurity of opposite conductivity type are ion-implanted into a semiconductor substrate of one conductivity type and simultaneously diffused to form a well region of opposite conductivity type. Then, an extremely low concentration reverse conductivity type diffusion layer is formed, and a low concentration reverse conductivity type drain diffusion layer is formed on the substrate by ion implantation. Next, a gate electrode that overlaps the drain diffusion layer is formed on the entire surface of the substrate via a gate insulating film, and then a high-concentration reverse conductivity type source diffusion layer adjacent to one end of the gate electrode and the gate are formed. The high-concentration reverse conductivity type drain diffusion layer, which is separated from the other end of the electrode and is included in the low-concentration reverse conductivity type drain diffusion layer, is formed by ion implantation.
【０００６】また、本発明は一導電型の半導体基板内に
形成されたエピタキシャル層内に形成された逆導電型の
ウエル領域と、該ウエル領域上にゲート絶縁膜を介して
形成されたゲート電極の一端に隣接する高濃度の一導電
型ソース拡散層と、チャネル領域を介して前記ソース拡
散層と対向して形成された低濃度の一導電型ドレイン拡
散層と、前記ゲート電極の他端から離間され、かつ前記
低濃度の一導電型ドレイン拡散層に含まれる高濃度の一
導電型ドレイン拡散層とを具備するものである。Further, according to the present invention, a well region of opposite conductivity type formed in an epitaxial layer formed in a semiconductor substrate of one conductivity type and a gate electrode formed on the well region via a gate insulating film. A high-concentration one-conductivity-type source diffusion layer adjacent to one end of the gate electrode, a low-concentration one-conductivity-type drain diffusion layer formed to face the source diffusion layer through a channel region, and from the other end of the gate electrode. And a high-concentration one-conductivity-type drain diffusion layer which is separated and is included in the low-concentration one-conductivity-type drain diffusion layer.
【０００７】[0007]
【発明の実施の形態】以下、本発明の高耐圧ＭＯＳトラ
ンジスタの一実施例について、その製造方法を示す図面
を参照しながら説明する。尚、説明の便宜上、同一チッ
プ上に形成される通常のＭＯＳトランジスタの製造方法
についての説明は省略するが、高耐圧ＭＯＳトランジス
タの製造方法と平行して形成されるものである。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a high breakdown voltage MOS transistor of the present invention will be described below with reference to the drawings showing the manufacturing method thereof. For the sake of convenience of description, a description of a method for manufacturing a normal MOS transistor formed on the same chip is omitted, but it is performed in parallel with the method for manufacturing a high breakdown voltage MOS transistor.
【０００８】先ず、図１に示すように一導電型、例えば
基板濃度１Ｅ１５／ｃｍ3 （尚、１Ｅ１５は１かける１
０の１５乗の意であり、以下同様である。）程度のＮ型
の半導体基板（ＮSub ）１に例えば拡散係数Ｄ１がFirst, as shown in FIG. 1, one conductivity type, for example, a substrate concentration of 1E15 / cm3 (1E15 is 1 times 1)
It means 0 to the 15th power, and so on. ), An N type semiconductor substrate (NSub) 1 having a diffusion coefficient D1 of
【０００９】[0009]
【数１】 [Equation 1]
【００１０】のヒ素イオン（75Ａｓ+ ）をレジスト膜Ａ
をマスクにしておよそ注入量３Ｅ１２／ｃｍ2 乃至１Ｅ
１３／ｃｍ2 の条件でイオン注入し、第１のイオン注入
領域２を形成すると共に、拡散係数Ｄ２がArsenic ions (75 As +) of the resist film A
With a mask as an implantation dose of 3E12 / cm2 to 1E
Ions are implanted under the condition of 13 / cm2 to form the first ion implantation region 2, and the diffusion coefficient D2 is
【００１１】[0011]
【数２】 [Equation 2]
【００１２】のボロンイオン（11Ｂ+ ）をおよそ１Ｅ１
３／ｃｍ2 の条件でイオン注入し、第２のイオン注入領
域３を形成する。次に、およそ１２００℃のＮ2 雰囲気
中で８時間の熱拡散を行い、前述したヒ素イオン（75Ａ
ｓ+ ）及びボロンイオン（11Ｂ+ ）を同時拡散し、図２
に示すように前記基板１内にＰ型ウエル４を形成すると
共に、およそ２Ｅ１５／ｃｍ3 程度の極低濃度のＰ−−
型拡散層５を形成する（図５に示す基板の濃度プロファ
イルを参照）。このとき、図５において、前記工程によ
りイオン注入しておいたヒ素イオン（75Ａｓ+ ）が一点
鎖線（１）に示すような濃度分布となり、一方ボロンイ
オン（11Ｂ+ ）が二点鎖線（２）に示すような濃度分布
となるように拡散される際に、両者により相殺される領
域が発生する。この領域（図中（３）で示された領域）
が、本発明の特徴であるＰ型ウエル４内に形成されるＰ
−−型拡散層５となる。これにより、Ｎ−型拡散層６と
Ｐ−−型拡散層５の接合領域での接合耐圧が向上する。Approximately 1E1 of boron ion (11B +)
Ions are implanted under the condition of 3 / cm @ 2 to form the second ion implantation region 3. Next, thermal diffusion was performed for 8 hours in a N2 atmosphere at about 1200 ° C., and the arsenic ion (75 A
s +) and boron ion (11B +) are co-diffused, as shown in FIG.
As shown in FIG. 3, a P-type well 4 is formed in the substrate 1 and a P-type with an extremely low concentration of about 2E15 / cm3 is formed.
The mold diffusion layer 5 is formed (see the concentration profile of the substrate shown in FIG. 5). At this time, in FIG. 5, the arsenic ion (75As +) ion-implanted in the above step has a concentration distribution as shown by the one-dot chain line (1), while the boron ion (11B +) is two-dot chain line (2). When the light is diffused so as to have the concentration distribution as shown in (1), a region which is offset by both is generated. This area (area indicated by (3) in the figure)
Is formed in the P-type well 4 which is a feature of the present invention.
It becomes the --- type diffusion layer 5. This improves the junction breakdown voltage in the junction region between the N− type diffusion layer 6 and the P− type diffusion layer 5.
【００１３】続いて、例えばリンイオン（31Ｐ+ ）をお
よそ注入量６Ｅ１２／ｃｍ2 の条件でイオン注入し、こ
れをおよそ１１００℃で２時間熱拡散することにより、
図３に示すように前記Ｐ−−型拡散層５内にＮ−型ドレ
イン拡散層６（図５の（４）の領域参照）を形成し、そ
の後半導体基板１上の全面におよそ１０００Åの膜厚の
ゲート絶縁膜７を形成する。Then, for example, phosphorus ions (31 P +) are ion-implanted under the condition of an implantation amount of 6E12 / cm @ 2, and this is thermally diffused at about 1100.degree. C. for 2 hours,
As shown in FIG. 3, an N-type drain diffusion layer 6 (see the region (4) in FIG. 5) is formed in the P-type diffusion layer 5, and then a film of about 1000Å is formed on the entire surface of the semiconductor substrate 1. A thick gate insulating film 7 is formed.
【００１４】次に、全面に例えばポリシリコン膜を形成
した後に、当該ポリシリコン膜を周知のパターニング技
術を用いてパターニングして、図４に示すように一端が
前記Ｎ−型ドレイン拡散層６上に延在するおよそ４００
０Åの膜厚のゲート電極８を形成する。そして、図示し
ないレジスト膜をマスクにして例えばリンイオン（31Ｐ
+ ）をおよそ加速電圧８０ＫｅＶ、注入量６Ｅ１５／ｃ
ｍ2 の条件でイオン注入し、前記ゲート電極８の一端に
隣接するＮ＋型ソース拡散層９と、該ゲート電極８の他
端から離間され、かつ前記Ｎ−型ドレイン拡散層６に含
まれるＮ＋型ドレイン拡散層１０（図５の（５）の領域
参照）とを形成する。Next, for example, a polysilicon film is formed on the entire surface, and then the polysilicon film is patterned using a well-known patterning technique so that one end is on the N-type drain diffusion layer 6 as shown in FIG. Approximately 400
A gate electrode 8 having a film thickness of 0Å is formed. Then, for example, phosphorus ions (31P
+) About 80 KeV acceleration voltage, 6E15 / c injection amount
The N + type source diffusion layer 9 adjacent to one end of the gate electrode 8 and the N + type drain diffusion layer 6 separated from the other end of the gate electrode 8 are ion-implanted under the condition of m2. A drain diffusion layer 10 (see the region (5) in FIG. 5) is formed.
【００１５】以上説明したように、本発明ではヒ素イオ
ン（75Ａｓ+ ）とボロンイオン（11Ｂ+ ）の拡散係数の
差を利用して、５Ｖ系の通常のＭＯＳトランジスタと同
一工程で形成される高耐圧ＭＯＳトランジスタの高濃度
ウエル中に前記Ｎ−型ドレイン拡散層６を包み込むよう
に極低濃度のＰ−−型拡散層５（図５の濃度プロファイ
ル参照）を形成したことで、電界緩和が可能となり、高
耐圧ＭＯＳトランジスタ専用のウエル領域を形成する工
程を増やすことなしに、当該ＭＯＳトランジスタに最適
なトランジスタ性能を有する高耐圧ＭＯＳトランジスタ
を形成できる。As described above, the present invention utilizes the difference in the diffusion coefficient between arsenic ions (75As +) and boron ions (11B +) to form a high-voltage MOS transistor formed in the same step as a normal 5V MOS transistor. An electric field can be relaxed by forming an extremely low concentration P--type diffusion layer 5 (see the concentration profile in FIG. 5) so as to enclose the N--type drain diffusion layer 6 in the high concentration well of the withstand voltage MOS transistor. Therefore, it is possible to form a high breakdown voltage MOS transistor having the optimum transistor performance for the MOS transistor without increasing the step of forming a well region dedicated to the high breakdown voltage MOS transistor.
【００１６】以下、本発明の他の実施の形態について説
明する。本発明の他の実施の形態は、半導体基板上に単
結晶層であるエピタキシャル層を形成することで、本発
明を実現するものである。本発明の他の実施の形態の半
導体装置は、図６に示すような構成である。即ち、図に
おいて、２１は一導電型、例えばＮ型の半導体基板であ
り、該基板２１にノンドープでエピタキシャル成長させ
たエピタキシャル層２２が形成されている。また、前記
エピタキシャル層２２内にＰ型ウエル２３が形成され、
該Ｐ型ウエル２３上にゲート絶縁膜２４を介してゲート
電極２５が形成されている。そして、前記ゲート電極２
５の一端に隣接するようにＮ＋型ソース拡散層２６が形
成されており、チャネル領域２７を介して前記ソース拡
散層２６に対向してＮ−型ドレイン拡散層２８が形成さ
れ、更にゲート電極２５の他端から離間され、かつＮ−
型ドレイン拡散層２８に含まれるようにＮ＋型ドレイン
拡散層２９が形成されてなるものである。Another embodiment of the present invention will be described below. Another embodiment of the present invention is to realize the present invention by forming an epitaxial layer which is a single crystal layer on a semiconductor substrate. A semiconductor device according to another embodiment of the present invention has a structure as shown in FIG. That is, in the figure, 21 is a semiconductor substrate of one conductivity type, for example, N type, and an epitaxial layer 22 which is epitaxially grown without doping is formed on the substrate 21. In addition, a P-type well 23 is formed in the epitaxial layer 22,
A gate electrode 25 is formed on the P-type well 23 via a gate insulating film 24. And the gate electrode 2
5, an N + type source diffusion layer 26 is formed so as to be adjacent to one end thereof, an N− type drain diffusion layer 28 is formed facing the source diffusion layer 26 via a channel region 27, and a gate electrode 25 is further formed. Is separated from the other end of
The N + type drain diffusion layer 29 is formed so as to be included in the type drain diffusion layer 28.
【００１７】尚、本発明の実施の形態としてＮ型の半導
体基板を例として説明したが、本発明はＰ型の半導体基
板でも同様に適用できる。Although the N-type semiconductor substrate has been described as an example of the embodiment of the present invention, the present invention can be similarly applied to the P-type semiconductor substrate.
【００１８】[0018]
【発明の効果】以上、本発明によれば通常のＭＯＳトラ
ンジスタと同一工程で形成される高耐圧ＭＯＳトランジ
スタの高濃度ウエル中に最適なトランジスタ性能を有す
る高耐圧ＭＯＳトランジスタを形成できる。As described above, according to the present invention, a high breakdown voltage MOS transistor having optimum transistor performance can be formed in a high concentration well of a high breakdown voltage MOS transistor formed in the same step as a normal MOS transistor.
【図１】本発明の一実施の形態の半導体装置の製造方法
を示す第１の断面図である。FIG. 1 is a first cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施の形態の半導体装置の製造方法
を示す第２の断面図である。FIG. 2 is a second cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention.
【図３】本発明の一実施の形態の半導体装置の製造方法
を示す第３の断面図である。FIG. 3 is a third cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.
【図４】本発明の一実施の形態の半導体装置の製造方法
を示す第４の断面図である。FIG. 4 is a fourth cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.
【図５】本発明の半導体装置のＡ−Ａ断面部の濃度プロ
ファイルを示す図である。FIG. 5 is a diagram showing a concentration profile of an AA cross section of the semiconductor device of the present invention.
【図６】本発明の他の実施の形態の半導体装置を示す断
面図である。FIG. 6 is a sectional view showing a semiconductor device according to another embodiment of the present invention.
【図７】従来の半導体装置を示す断面図である。FIG. 7 is a cross-sectional view showing a conventional semiconductor device.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−141754（ＪＰ，Ａ) 特開 平７−307401（ＪＰ，Ａ) 特開 昭62−112372（ＪＰ，Ａ) 特開 平８−64690（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 21/336 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 62-141754 (JP, A) JP 7-307401 (JP, A) JP 62-112372 (JP, A) JP 8- 64690 (JP, A) (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 29/78 H01L 21/336
Claims (3)
純物と逆導電型の不純物を注入し、同時に拡散すること
で逆導電型のウエル領域を形成すると共に前記逆導電型
のウエル領域内に、前記逆導電型のウエル領域よりも低
濃度の逆導電型拡散層を形成する工程と、 前記低濃度の逆導電型拡散層に、第１の一導電型ドレイ
ン拡散層をイオン注入により形成する工程と、 前記基板全面にゲート絶縁膜を形成する工程と、 全面にポリシリコン膜を形成した後にパターニングして
少なくとも前記第１の一導電型ドレイン拡散層上方にオ
ーバーラップするゲート電極を形成する工程と、 前記ゲート電極の一端に隣接するように、前記第１の一
導電型ドレイン拡散層よりも不純物濃度の高い一導電型
ソース拡散層と、前記ゲート電極の他端から離間され、
かつ前記第１の一導電型ドレイン拡散層に含まれ、当該
第１の一導電型ドレイン拡散層よりも不純物濃度の高い
第２の一導電型ドレイン拡散層とをイオン注入により形
成する工程とを有することを特徴とする半導体装置の製
造方法。1. A well region of opposite conductivity type is formed by implanting an impurity of one conductivity type and an impurity of opposite conductivity type into a semiconductor substrate of one conductivity type and simultaneously diffusing them to form a well region of opposite conductivity type. A step of forming a reverse-conductivity-type diffusion layer having a concentration lower than that of the reverse-conductivity-type well region, and a first first-conductivity-type drain diffusion layer is ion-implanted into the low-concentration reverse-conductivity-type diffusion layer. A step of forming, a step of forming a gate insulating film on the entire surface of the substrate, and a step of forming a polysilicon film on the entire surface and then patterning to form a gate electrode which overlaps at least above the first one conductivity type drain diffusion layer. And a first conductivity type source diffusion layer having an impurity concentration higher than that of the first one conductivity type drain diffusion layer so as to be adjacent to one end of the gate electrode, and separated from the other end of the gate electrode. ,
And included in the first one conductivity type drain diffusion layer ,
And a second one-conductivity-type drain diffusion layer having a higher impurity concentration than the first one-conductivity-type drain diffusion layer is formed by ion implantation.
純物と逆導電型の不純物を注入し、同時に拡散すること
で逆導電型のウエル領域を形成すると共に前記逆導電型
のウエル領域内に、前記逆導電型のウエル領域よりも低
濃度の逆導電型拡散層を形成する工程と、 前記低濃度の逆導電型拡散層に、前記低濃度の逆導電型
拡散層よりも不純物濃度の高い第１の一導電型ドレイン
拡散層をイオン注入により形成する工程と、 前記基板全面にゲート絶縁膜を形成する工程と、 全面にポリシリコン膜を形成した後にパターニングして
少なくとも前記第１の一導電型ドレイン拡散層上方にオ
ーバーラップするゲート電極を形成する工程と、 前記ゲート電極の一端に隣接するように、前記第１の一
導電型ドレイン拡散層よりも不純物濃度の高い一導電型
ソース拡散層と、前記ゲート電極の他端から離間され、
かつ前記第１の一導電型ドレイン拡散層に含まれ、当該
第１の一導電型 ドレイン拡散層よりも不純物濃度の高い
第２の一導電型ドレイン拡散層とをイオン注入により形
成する工程とを有することを特徴とする半導体装置の製
造方法。2. A well region of opposite conductivity type is formed by implanting an impurity of one conductivity type and an impurity of opposite conductivity type into a semiconductor substrate of one conductivity type and simultaneously diffusing them to form a well region of opposite conductivity type. A step of forming a reverse conductivity type diffusion layer having a lower concentration than the reverse conductivity type well region, and an impurity concentration higher than that of the low concentration reverse conductivity type diffusion layer in the low concentration reverse conductivity type diffusion layer. A first high conductivity drain diffusion layer by ion implantation; a step of forming a gate insulating film on the entire surface of the substrate; and a step of forming a polysilicon film on the entire surface and then patterning at least the first insulating film. Forming an overlapping gate electrode above the one-conductivity type drain diffusion layer, and adhering to one end of the gate electrode, one conductivity type having a higher impurity concentration than the first one-conductivity type drain diffusion layer. A source diffusion layer, spaced from the other end of said gate electrode,
And included in the first one conductivity type drain diffusion layer ,
And a second one-conductivity-type drain diffusion layer having a higher impurity concentration than the first one-conductivity-type drain diffusion layer is formed by ion implantation.
純物と逆導電型の不純物を注入し、同時に拡散して逆導
電型のウエル領域を形成すると共に、前記一導電型の不
純物と前記逆導電型の不純物とを相殺することで前記逆
導電型のウエル領域内に、前記逆導電型のウエル領域よ
りも低濃度の逆導電型拡散層を形成する工程と、 前記低濃度の逆導電型拡散層に、第１の一導電型ドレイ
ン拡散層をイオン注入により形成する工程と、 前記基板全面にゲート絶縁膜を形成する工程と、 全面にポリシリコン膜を形成した後にパターニングして
少なくとも前記第１の一導電型ドレイン拡散層上方にオ
ーバーラップするゲート電極を形成する工程と、 前記ゲート電極の一端に隣接するように、前記第１の一
導電型ドレイン拡散層よりも不純物濃度の高い一導電型
ソース拡散層と、前記ゲート電極の他端から離間され、
かつ前記第１の一導電型ドレイン拡散層に含まれ、当該
第１の一導電型ドレイン拡散層よりも不純物濃度の高い
第２の一導電型ドレイン拡散層とをイオン注入により形
成する工程とを有することを特徴とする半導体装置の製
造方法。3. An impurity of one conductivity type and an impurity of opposite conductivity type are implanted into a semiconductor substrate of one conductivity type and diffused at the same time to form a well region of opposite conductivity type. Forming a reverse conductivity type diffusion layer having a lower concentration than the reverse conductivity type well region in the reverse conductivity type well region by canceling out the reverse conductivity type impurity; Forming a first drain layer of the first conductivity type on the conductivity type diffusion layer by ion implantation; forming a gate insulating film on the entire surface of the substrate; forming a polysilicon film on the entire surface; Forming an overlapping gate electrode above the first one-conductivity type drain diffusion layer; and having a higher impurity concentration than the first one-conductivity type drain diffusion layer so as to be adjacent to one end of the gate electrode. A one conductivity type source diffusion layer, spaced from the other end of said gate electrode,
And included in the first one conductivity type drain diffusion layer ,
And a second one-conductivity-type drain diffusion layer having a higher impurity concentration than the first one-conductivity-type drain diffusion layer is formed by ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27004196A JP3423161B2 (en) | 1996-10-11 | 1996-10-11 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27004196A JP3423161B2 (en) | 1996-10-11 | 1996-10-11 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10116983A JPH10116983A (en) | 1998-05-06 |
| JP3423161B2 true JP3423161B2 (en) | 2003-07-07 |
Family
ID=17480715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27004196A Expired - Fee Related JP3423161B2 (en) | 1996-10-11 | 1996-10-11 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3423161B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100660917B1 (en) * | 1999-02-03 | 2006-12-26 | 페어차일드코리아반도체 주식회사 | Ldmos |
| TWI288472B (en) | 2001-01-18 | 2007-10-11 | Toshiba Corp | Semiconductor device and method of fabricating the same |
| US20060097292A1 (en) * | 2004-10-29 | 2006-05-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
| WO2009090974A1 (en) * | 2008-01-16 | 2009-07-23 | Nec Corporation | Semiconductor device and method for manufacturing the same |
| JP5423269B2 (en) | 2009-09-15 | 2014-02-19 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| JP5471320B2 (en) | 2009-11-09 | 2014-04-16 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| JP5434501B2 (en) * | 2009-11-13 | 2014-03-05 | 富士通セミコンダクター株式会社 | MOS transistor, semiconductor integrated circuit device, semiconductor device |
-
1996
- 1996-10-11 JP JP27004196A patent/JP3423161B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10116983A (en) | 1998-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5548143A (en) | Metal oxide semiconductor transistor and a method for manufacturing the same | |
| US5359219A (en) | Silicon on insulator device comprising improved substrate doping | |
| KR100392901B1 (en) | Method of manufacturing an asymmetric slightly doped drain (LCD) MOS device | |
| US6897525B1 (en) | Semiconductor device and method of manufacturing the same | |
| US5888874A (en) | Bipolar transistor and method of forming BiCMOS circuitry | |
| JP2586844B2 (en) | Method for manufacturing semiconductor device | |
| US6509211B2 (en) | Semiconductor device having SOI structure and method of fabricating the same | |
| JP3423161B2 (en) | Method for manufacturing semiconductor device | |
| JP3381110B2 (en) | Method for manufacturing semiconductor device | |
| US5920784A (en) | Method for manufacturing a buried transistor | |
| US6541341B1 (en) | Method for fabricating MOS field effect transistor | |
| JP3194805B2 (en) | Semiconductor device | |
| JP3274038B2 (en) | Semiconductor device | |
| JP2757491B2 (en) | Method for manufacturing semiconductor device | |
| JP3250298B2 (en) | Method for manufacturing semiconductor device | |
| JPH0630390B2 (en) | Method for manufacturing CMOS semiconductor device | |
| JP3014138B2 (en) | Semiconductor device | |
| JPH04255233A (en) | Semiconductor device and manufacture thereof | |
| JPH08340108A (en) | Mos field effect transistor and manufacture thereof | |
| JPH02219237A (en) | Mis type semiconductor device | |
| JPH0629527A (en) | Semiconductor device and its manufacture | |
| JP2537649B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JP2808620B2 (en) | Method for manufacturing semiconductor device | |
| JPH08186252A (en) | Semiconductor device | |
| JP2682426B2 (en) | Semiconductor integrated circuit device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |