JP5434501B2 - MOS transistor, semiconductor integrated circuit device, semiconductor device - Google Patents

Description

  The present invention generally relates to semiconductor devices, and more particularly to a high voltage transistor and a method for manufacturing the same.

  High voltage transistors are used for various output applications. Conventionally, a high breakdown voltage transistor has been often used in the form of a single discrete element, but recently, it has been used as a power amplifier in the final stage of an RF circuit in portable information equipment applications such as a mobile phone and WiMAX. A high breakdown voltage transistor used in the final stage of the RF circuit requires a particularly high drain breakdown voltage.

  On the other hand, in such portable information devices, there is a strong demand for integrating a high voltage transistor with other logic elements typically made of CMOS elements.

JP 2000-68500 A JP 2003-168996 A JP-A-6-310717 JP 53-067373 A JP-A-62-045175 JP 2002-270825 A US Patent Publication No. 2007/0212838

  When a high voltage transistor is integrated on the same semiconductor substrate together with another semiconductor element such as a CMOS, the high voltage transistor is, for example, input without significantly changing the manufacturing process of the input / output CMOS element, for example, in order to reduce the cost. It is desirable to be able to manufacture simultaneously with an output CMOS element or the like. On the other hand, a high breakdown voltage transistor has a drain breakdown voltage of 6 to 7 V, but there is a demand to secure a drain breakdown voltage that exceeds the conventional drain breakdown voltage and preferably reaches 10 V.

  In such a high breakdown voltage transistor, a high voltage is applied to the drain region particularly during an off operation, and thus the off breakdown voltage characteristics are important.

  When a high breakdown voltage transistor is integrated with a CMOS element on the same semiconductor substrate, a p-type well is also formed under the high breakdown voltage transistor using the same mask during ion implantation for forming a p-type well of the CMOS element. However, in this case, the off-breakdown voltage characteristic of the high breakdown voltage transistor is substantially the same as that of the CMOS element, and further improvement is difficult.

  FIG. 1 is a cross-sectional view showing a configuration of a conventional high breakdown voltage n-channel MOS transistor 10.

  Referring to FIG. 1, the high breakdown voltage n-channel MOS transistor 10 is formed in an element region 11A defined by an element isolation region 11I on a silicon substrate 11, and a p-type well 11PW is formed in the element region 11A. Is formed.

  On the element region 11A, a gate electrode 13 is formed on the surface of the silicon substrate 11 via a gate insulating film 12, and a channel region 11CH just below the gate electrode 13 has a threshold control doped region by p-type impurities. 11NVT is formed.

  In the p-type well 11PW, an n − -type source extension region 11a is formed on the first side of the channel region 11CH by doping with an n-type impurity element, and the second side opposite to the first side is formed. On the side, an n − -type drain extension region 11b is formed by doping with the same n-type impurity element.

It said first sidewall insulation films 13W ₁ is formed on the first side of the gate electrode 13, the p-type wells 11PW, the first further first side wall insulating films 13W _1, i.e. the first An n + -type source region 11S is formed on the side opposite to the channel region 11CH with respect to _one sidewall insulating film 13W1.

The above gate electrode 13 wherein the first side second sidewall insulation film 13W ₂ on a second side opposite is formed, the in p-type well 11PW, said second sidewall insulation film 13W ₂ further, the second side, i.e. the side opposite the said channel region 11CH to said second sidewall insulation film 13W _2, n + -type drain region 11D are formed.

Since the high-voltage transistor 10 in a high electric field of Figure 1 to ensure the withstand voltage of the gate electrode a drain terminal for generating, said has a drain terminal and a drain region 11D of the gate electrode 13 is spaced, the sidewall insulation film 13W ₂ is The drain extension region 11b is covered with the gate insulating film 12 between the drain end of the gate electrode 13 and the drain region 11D.

A silicide layer 14G is formed on the gate electrode 13, a silicide layer 14S is formed on the source region 11S, and a silicide layer 14D is formed on the drain region 11D. At that time the silicide layer 14G, the are formed in the opening formed by patterning a side wall insulating film 13W _2, so that it can not be formed on the drain end of the gate electrode 13 even when the patterning is displaced, It is formed close to the first side of the gate electrode 13G, that is, the source region 11S.

  By the way, when such a high breakdown voltage n-channel MOS transistor 10 is formed on the same silicon substrate 11 together with other, for example, CMOS elements constituting an input / output circuit, at a low cost, the p-type well 11PW has a CMOS element. It is desirable to form the n-channel MOS transistor to be formed using the same mask at the same time as the p-type well. However, in this case, the formed p-type well 11PW is formed with the same impurity concentration and depth as the p-type well of the n-channel MOS transistor constituting such another CMOS element. In such a structure, there is a problem that breakdown is likely to occur at the pn junction between the n − type LDD region 11b and the p type well 11PW surrounded by FIG.

  FIG. 2 is a SIMS profile showing the depth distribution of the n-type impurity element (P: phosphorus) and the p-type impurity element (B: boron) in the silicon substrate 11 along the line AA ′ in FIG. It is.

Referring to FIG. 2, P constituting the n-type LDD region is ion-implanted with an acceleration energy of about 100 keV, and B constituting the p-type well is ion-implanted with an acceleration energy of about 150 keV. A relatively steep pn junction with an impurity concentration of about 4 × 10 ¹⁷ cm ^{−3 at a} depth of about 250 nm is formed corresponding to the portion surrounded by FIG.

  Such a steep pn junction is generated because the p-type well 11PW has a relatively high impurity concentration. However, when the drain voltage increases beyond 6 to 7 V, the pn junction is easily formed. The breakdown caused the off breakdown voltage of the high breakdown voltage MOS transistor.

  In contrast, conventionally, as shown in FIG. 3, the mask for forming the p-type well 11PW is deformed, and the p-type well 11PW is not formed under the high breakdown voltage MOS transistor except under the source region 11S. A structure to do so has been proposed. However, in FIG. 3, the parts described above are denoted by corresponding reference numerals, and the description thereof is omitted.

  However, in the high breakdown voltage MOS transistor having such a structure, although the breakdown voltage is improved, the voltage fluctuation accompanying the operation of the high breakdown voltage MOS transistor passes under the element isolation structure 11I as indicated by an arrow in FIG. May propagate outside the element region 11A and interfere with the operation of other transistors formed on the substrate 11.

  According to one aspect, a high breakdown voltage MOS transistor includes a semiconductor substrate having a first conductivity type defined by a device isolation region and a surface of the semiconductor substrate in the first device region. A gate electrode having a first side forming a source side end and a second side opposite to the first side forming a drain side end; and in the semiconductor substrate, the first side The source side end of the gate electrode between the source side end of the gate electrode in the element region and a first element isolation region portion of the element isolation region facing the source side end of the gate electrode. A source region of a second conductivity type opposite to the first conductivity type, formed to be separated from the first element by a first distance and extending to the first element isolation region portion, and the semiconductor substrate In the first element region From the drain side end of the gate electrode between the drain side end of the gate electrode and a second element isolation region portion of the element isolation region facing the drain side end of the gate electrode, A drain region of the second conductivity type formed to be spaced apart by a second distance larger than the first distance and extending to the second element isolation region portion; and In the element region, the source side end of the gate electrode is moved to a third distance from the tip of the source region facing the side in contact with the first element isolation region portion of the source region toward the drain region. A source extension region extending beyond the first conductivity type and having an impurity concentration lower than that of the source region, and in the first element region in the semiconductor substrate, Encloses the drain region and extends from the second element isolation region portion toward the source region beyond the drain side end of the gate electrode by a fourth distance greater than the third distance. A drain extension region having an impurity concentration lower than that of the drain region, and a channel region is provided between the source extension region and the drain extension region in the semiconductor substrate. A first well is formed below the source region and the source extension region in the semiconductor substrate, and a first pn junction is formed with respect to the source region and the source extension region with the first conductivity type. Formed at a depth exceeding the lower end of the element isolation region, and a second region is formed below the first well. A well having the second conductivity type and a second pn junction formed with the first well, wherein the first well and the second well include the drain extension region and It is not formed under the drain region.

  According to another aspect, a semiconductor integrated circuit device is a semiconductor integrated circuit device including the MOS transistor and a CMOS element formed on the semiconductor substrate, wherein the CMOS element is on the semiconductor substrate, An n-channel MOS transistor and a p-channel MOS transistor respectively formed in the second and third element regions defined by the element isolation region, wherein the n-channel MOS transistor is formed in the second element region; A p-channel MOS transistor including a fifth well having the first conductivity type, wherein the fifth well contains the same impurity element as the first well at substantially the same concentration and depth; Includes a sixth well formed in the third element region and having the second conductivity type, and the sixth well includes the third well. It contains substantially the same concentration and depth of the same impurity element as.

  According to the present invention, since the reverse conductivity type well is not formed immediately below the drain region and the drain extension region of the high voltage MOS transistor, a steep pn junction is not formed, and the breakdown of the pn junction can be suppressed. While the off-breakdown voltage of the withstand voltage MOS transistor is improved, a reverse conductivity type well is formed immediately below the source region and the source extension region, so that intrusion of noise from the semiconductor substrate to the source region is blocked.

  According to the present invention, since the second shallow well and the deep well therebelow are formed outside the first shallow well so as to surround the same, the high breakdown voltage MOS transistor travels the same through the semiconductor substrate. Noise leaking to other elements on the semiconductor substrate, for example, a CMOS element, or conversely, noise can be blocked by the pn junction between the first shallow well and the second shallow well. In such a configuration, noise emitted downward from the drain region and the drain extension region is not blocked, but noise that interferes with other elements in the semiconductor integrated circuit is mainly noise that propagates along the surface of the semiconductor substrate. With such a configuration, it is possible to effectively block noise that the operation of the high voltage MOS transistor has on other elements on the same semiconductor substrate or noise that other elements have on the high voltage MOS transistor.

It is a figure which shows the example of the conventional high voltage | pressure-resistant MOS transistor, and its problem. It is a figure which shows the depth distribution of P (phosphorus) and B (boron) along line A-A 'in FIG. It is a figure which shows the modification of the high voltage | pressure-resistant MOS transistor of FIG. 1, and its problem. 1 is a diagram showing a configuration of a high voltage MOS transistor according to a first embodiment. FIG. 5 is a diagram showing off breakdown voltage characteristics of the high breakdown voltage MOS transistor 20 of FIG. 4. FIG. 5 is a diagram showing a state of well formation immediately under an element isolation region of the high voltage MOS transistor of FIG. 4. FIG. 5 is a diagram (part 1) for explaining a manufacturing process of the high voltage MOS transistor of FIG. 4; FIG. 5 is a diagram (part 2) for explaining a manufacturing process of the high voltage MOS transistor of FIG. 4; FIG. 5 is a diagram (No. 3) for explaining a manufacturing process of the high voltage MOS transistor of FIG. 4; FIG. 5 is a diagram (No. 4) for explaining a production step of the high voltage MOS transistor of FIG. 4; FIG. 5 is a diagram (No. 5) for explaining a manufacturing process of the high voltage MOS transistor of FIG. 4; FIG. 6 is a diagram (No. 6) for explaining a production process of the high voltage MOS transistor of FIG. 4; FIG. 7 is a view (No. 7) for explaining a manufacturing step of the high voltage MOS transistor of FIG. 4; FIG. 8 is a diagram (No. 8) for explaining a production process of the high voltage MOS transistor of FIG. 4; FIG. 9 is a diagram (No. 9) for explaining a manufacturing process of the high voltage MOS transistor of FIG. 4; FIG. 10 is a diagram (No. 10) for explaining a production process of the high voltage MOS transistor of FIG. 4; FIG. 11 is a diagram (No. 11) for explaining a production process of the high voltage MOS transistor of FIG. 4; FIG. 13 is a view (No. 12) for explaining a production process of the high voltage MOS transistor of FIG. 4; FIG. 13 is a view (No. 13) for explaining a production process of the high voltage MOS transistor of FIG. 4; FIG. 15 is a diagram (No. 14) for explaining a production process of the high voltage MOS transistor of FIG. 4; FIG. 15 is a view (No. 15) for explaining the production process of the high voltage MOS transistor of FIG. 4; It is a figure which shows the structure of the high voltage | pressure-resistant semiconductor element by 2nd Embodiment. FIG. 9 is a diagram showing a state of well formation immediately under the element isolation region in FIG. 8. It is a figure which shows the modification of the high voltage | pressure-resistant semiconductor element of FIG. FIG. 5 is a view showing a modification of the high voltage MOS transistor of FIG. 4.

[First Embodiment]
FIG. 4 shows a configuration of the high voltage MOS transistor 20 according to the first embodiment.

Referring to FIG. 4, the high breakdown voltage MOS transistor 20 is an n-channel MOS transistor, and contains B (boron) at a concentration of 7 × 10 ¹⁴ cm ^{−3 to} 3 × 10 ¹⁵ cm ^{−3 and} a specific resistance of 5 Ωcm to It is formed on a 20 Ωcm p-type silicon substrate 21. However, it is also possible to configure a p-channel type high voltage MOS transistor by inverting the conductivity type in the following description.

  An element region 21A is defined in the silicon substrate 21 by an STI type element isolation structure 21I having a depth of, for example, 0.25 μm to 0.4 μm, and the element isolation region 21I is further formed on the silicon substrate 21. A contact region 21C for controlling the potential of the p-type silicon substrate 21 is defined apart from the element region 21A.

  In the element region 21A, the gate electrode 23G is formed on the silicon substrate 21 through a gate insulating film 22 made of a silicon oxide film having a thickness of 6 nm, for example, by an n + type polysilicon silicon pattern having a width W of 440 nm, for example. The gate electrode has a source side end on which a side wall insulating film 23WA is formed on the first side, and a side wall insulating film 23WB on the second side facing the first side. It has a drain side end.

Wherein in the silicon substrate 21, in the device region 21A, the first isolation region portion 21I ₁ which faces the source end of the gate electrode of the device isolation region 21I and the source side edge of the gate electrode 23G between the source diffusion region of the first distance d ₁ spaced apart to n + type corresponding to the thickness of the sidewall insulation films 23WA from the source side edge of the gate electrode 23G is, the first isolation region portion are formed extends to 21I _1.

Further, in the element region 21A, in the silicon substrate 21, in the element region 21A, the drain side end of the gate electrode 23G and the second element facing the drain side end of the gate electrode 23G in the element isolation region 21I. The separation region portion 21I ₂ is separated from the drain side end of the gate electrode 23 by a second distance d ₂ corresponding to a portion of the surface of the silicon substrate 21 covered with the sidewall insulating film 23WB. An n + type drain diffusion region is formed extending to the _second element isolation region portion 21I2. Here such the second distance d2 is for example 180 nm, it is set larger than the first distance _{d 1.}

Further, in the silicon substrate 21, in the element region 21A, the source region tip 21s facing the _first element isolation region portion 21I1 in the source region 21S toward the drain region 21D gate - DOO source-side end of the electrode 23G of the third, small distance d ₃ only extends beyond, and the formed source region 21S having a lower impurity concentration than n- type source extension region 21a is Yes.

During addition the p-type silicon substrate, in the device region 21A is wrapped the drain region 21D, toward the source region 21S of the second isolation region portion 21I _2, the gate - drain side of the gate electrode 23G An n − type drain extending beyond the end by a fourth distance d ₄ larger than the third distance d ₃ , for example, set to 120 nm, and having an impurity concentration lower than that of the drain region 21D An extension region 21b is formed.

  In the p-type silicon substrate 21, a channel region 21CH is formed between the source extension region 21a and the drain extension region 21b with a channel length Lg of 320 nm, for example. The channel region 21CH is channel-doped with a p-type impurity element such as B for threshold control.

  In the p-type silicon substrate 21, a p-type first shallow well 21PW is provided below the source region 21S and the source extension region 21a, and a first pn junction is formed with respect to the source region 21S and the source extension region 21a. And a depth exceeding the lower end of the element isolation structure 21I, and an n-type deep well 21DNW is formed below the first shallow well 21PW, and the n-type first shallow well A second pn junction is formed with 21PW. On the other hand, the first shallow well 21PW and the deep n-type well 21DNW are part of the drain extension region 21b and the channel region 21CH below the drain extension region 21b and the drain region 21D in the element region 21A. Note that it is not formed in the containing region / 21PW.

  The first shallow well 21PW is doped with a p-type impurity such as B at a higher impurity concentration than the p-type silicon substrate 21.

Further, with the construction of FIG. 4, the deep n-type well 21DNW is the first pass under the element isolation region portion 21I ₁ extends beyond the contact region 21C, the contact region 21C in the deep n-type well Above the 21DNW, the p-type shallow well 21PW is continuously formed. Furthermore, in the contact region 21C, an ohmic contact region 21SS made of a p + type diffusion region is formed on the shallow well 21PW.

  Further, a low-resistance silicide layer 24S is formed on the surface of the gate electrode 23G, a low-resistance silicide layer 24S is formed on the surface of the source region 21S, a low-resistance silicide layer 24D is formed on the surface of the drain region 21D, and the ohmic contact. A low resistance silicide layer 24SS is formed on the surface of the region 21SS by, for example, a salicide process. Also in this embodiment, the silicide layer 24G is formed close to the drain side end of the gate electrode 23G.

  According to the configuration of FIG. 4, since the high concentration drain region 21D is formed away from the drain side end of the gate electrode 23G, the off breakdown voltage of the high breakdown voltage MOS transistor 20 is improved, while the source region 21S has the gate It is formed close to the source side end of the electrode 23G, and a low source resistance is realized. Further, by supplying a power supply voltage, for example, a ground voltage, to the ohmic contact region 21SS, the potential of the silicon substrate 21 can be fixed to a predetermined value such as a ground potential via the shallow well 21PW and the deep n-type well 21DNW. In other words, external voltage fluctuations can be blocked from propagating through the silicon substrate 21 to the source region 21S.

At this time, in the embodiment of FIG. 4, the first shallow well 21PW and the deep well 21DNW are not formed in the region / 21PW, so that the n − type drain extension region 21b is a p− type in the region / 21PW. A pn junction is formed with the silicon substrate 21. Since the concentration of the p-type impurity element in the silicon substrate 21 is about 7 × 10 ¹⁴ cm ^{−3 to} 3 × 10 ¹⁵ cm ⁻³ as described above, the carrier concentration gradient at the pn junction is suppressed to be low. Therefore, local electric field concentration associated with the steep pn junction and the narrow depletion layer as in the configuration of FIG. 1 is avoided, and the off breakdown voltage characteristics of the high breakdown voltage transistor 20 are further improved. That is, in the high voltage MOS transistor 20 of FIG. 4, the drain leakage current is suppressed and the RF signal amplification efficiency can be improved.

  FIG. 5 is a diagram showing the off breakdown voltage characteristics of the high breakdown voltage MOS transistor 20 of FIG.

  Referring to FIG. 5, Id, Is, Isub, and Ig are a drain current, a source current, a substrate current, and a gate current when the gate voltage Vg is 0 V, respectively, but until the drain voltage Vds reaches around 11 V. It can be seen that there is no rapid increase in the drain current Id due to breakdown.

Referring again to FIG. 4, in the high voltage MOS transistor 20, the first shallow well 21PW until immediately below the first isolation region portion 21I _1, also in the second isolation region portion 21I ₂ are also formed directly below, extending the deep n-type well 21DNW a is below the first shallow well 21PW, beyond the contact region 21C exceeds the lower of the first isolation region portion 21I ₁ and is also under the second element region portion 21I _2, it should be noted that extends to the outside of the first shallow well 21PW.

On the deep n-type well 21DNW is immediately below the device isolation region 21I and the element isolation region portion 21I ₂ outside of the isolation region portion 21I ₁ (left end in FIG. 4), shallow n-type of the second A well 21NW is formed, and the second shallow well 21NW surrounds the first shallow well 21PW from the outside in a horizontal plane.

FIG. 6 is a plan view showing a state in which the second shallow well 21NW surrounds the first shallow well 21PW from the outside at a depth position immediately below the element isolation region portions 21I ₁ and 21I ₂ . However, in FIG. 6, the positions of the gate electrode 23G, the source region 21S, the drain region 21D, and the contact region 21SS are overlapped by broken lines for reference. In order to avoid the complexity of the drawing, the element isolation region 21I and the element isolation region portions 21I ₁ and 21I ₂ are not shown.

  Referring to FIG. 6, the second shallow well 21NW continuously surrounds the first shallow well 21PW from the outside in a horizontal plane, that is, a plane parallel to the main surface of the substrate, and a pn junction is interposed therebetween. It is formed. Further, since the shallow well 21PW is electrically connected to the contact region 21SS and is fixed to a predetermined, for example, ground potential, the high voltage MOS transistor 20 is operated and a large voltage fluctuation is caused in the drain region 21D. Even if it occurs in the drain extension region 21b, it propagates along the substrate surface as noise, and the problem of interfering with the operation of other semiconductor devices and other elements formed on the silicon substrate 21 is avoided. .

  Next, the manufacturing method of the high breakdown voltage MOS transistor 20 will be described with reference to FIGS. 7A to 7O in the case where an n-channel MOS transistor and a p-channel MOS transistor constituting a CMOS element are formed on the silicon substrate 21 simultaneously. explain. However, in the following description, the contact region 21C is omitted.

  Referring to FIG. 7A, in addition to the element region 20A of the high voltage MOS transistor 20, the element region 21NMOS of the n-channel MOS transistor and the p-channel MOS transistor are formed on the silicon substrate 21 by the element isolation region 21I. The device region 21PMOS is defined. Here, it is assumed that the n-channel MOS transistor and the p-channel MOS transistor are input / output transistors and form CMOS elements.

Then part of the device region 21PMOS and the device region 21A in the step of FIG. 7B, the region / 21PW, covered further part of said second element isolation region portion 21I ₂ by the first resist pattern _{R 1,} the In this state, B is ion-implanted at a dose of 2 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹³ cm ⁻² under an acceleration voltage of 100 keV to 200 keV, and the first shallow well 21PW is formed in the element region 21A. Is formed to reach a depth exceeding the lower end of the element isolation region 21I. At the same time, in the element region 21NMOS, a similar p-type well 21pw is also formed of B with the same impurity concentration and the same depth. In the step of FIG. 7B, the shallow well 21PW is partially formed in the bottom of the second isolation region 21I _2.

Next, in the step of FIG. 7C, the element region 21NMOS and the element region 21A are covered with the second resist pattern R2, and in this state, P (phosphorus) is under an acceleration voltage of 300 keV to 400 keV, 2 × 10 ¹³ cm ⁻² to Ions are implanted at a dose of 5 × 10 ¹³ cm ⁻² , the n-type second shallow well 21nw is formed in the device region 21PMOS, and the lower end of the device isolation region 21I is the same as the first shallow well 21PW. It is formed to reach a depth exceeding the lower end. At that time, the second resist pattern R ₂ is part of the device elements from the area 21A of the first and second isolation region portions 21I ₁ and 21I _2, only to the portion where the first shallow well 21PW is formed In the step of FIG. 7C, the second shallow well 21NW is continuous with the n-type well 21nw immediately below the first and second element isolation region portions 21I ₁ and 21I ₂ in the step of FIG. 7C. 1 shallow well 21PW is formed so as to surround from the outside.

Further covered with a resist pattern _{R 3} the device region 21PMOS third in steps FIG. 7D, under the acceleration voltage of in this state for example ^{B 30keV~40keV, 3 × 10 12 cm} -2 ~6 × 10 12 cm -2 Then, the channel dope region 21CH of the high voltage MOS transistor 20 is formed in the element region 21A, and the channel dope region 21Nt of the n channel MOS transistor is formed in the element region 21NMOS.

Then the device region 21NMOS and the device region 21A is covered by the fourth resist pattern _{R 4} in the step of FIG. 7E, under the acceleration voltage of the state, for example, As ^{(arsenic) 100keV~150keV, 1 × 10 12 cm} - Ions are implanted at a dose of ^{2 to} 3 × 10 ¹² cm ⁻² to form a channel doped region 21Pt of the p-channel MOS transistor on the surface portion of the element region 21PMOS.

Next, in the step of FIG. 7F, a fifth resist pattern R5 is formed on the silicon substrate 21 to cover the element regions 21A, 21NMOS and 21PMOS except for the region where the drain extension region 21b of the high voltage MOS transistor 20 is to be formed. In this state, for example, P is ion-implanted at a dose of 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ⁻² under an acceleration voltage of 50 keV to 200 keV to form the n − type drain extension region 21b. To do. A p-type layer is formed between the n − -type drain extension region 21b formed in this way and the second shallow well 21NW having the n-type just below the second element isolation region portion 21I _2. Since the first shallow well 21PW is interposed, there is no short circuit between the drain extension region 21b and the second shallow well 21NW.

Next, in the step of FIG. 7G, a sixth resist pattern R ₆ is formed on the silicon substrate 21 to cover the element regions 21NMOS and 21PMOS, and the region / 21PW of the element region 21A. For example, ions are implanted at a dose of 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ⁻² under an acceleration voltage of 600 keV to 700 keV, and the deep regions are formed under the first and second shallow wells 21PW and 21NW. An n-type well 21DNW is formed. At this time, the resist pattern R6 is preferably formed so that the deep n-type well 21DNW is separated from the drain extension region 21b of the high voltage MOS transistor 20 by about 0.2 μm.

  Next, the structure of FIG. 7G is heat-treated at a temperature of, eg, 1000 ° C. for 10 seconds to activate the introduced impurity element, and then in the step of FIG. 7H, a thermal oxide film is formed on the surface of the silicon substrate 21, eg, 7 nm. A polysilicon film is further deposited thereon with a film thickness of 100 nm, for example.

  Further, by patterning the polysilicon film thus formed together with the thermal oxide film therebelow, the gate electrode 23G is formed on the element region 21A, and the gate of the n-channel MOS transistor is formed on the element region 21NMOS. An electrode 23N is formed on the element region 21PMOS, and a gate electrode 23P of the p-channel MOS transistor is formed via a gate insulating film 22, respectively.

Then on the silicon substrate 21 in the step of FIG. 7I, the device regions 21PMOS, and the resist pattern _{R 7} covering the drain extension region 21b are formed out of the device region 21A, the acceleration of the P in this state for example 30keV Under voltage, ions are implanted at a dose of 1 × 10 ¹³ cm ⁻² , the source extension region 21a is formed in the element region 21A, and the n-channel MOS is formed on both sides of the polysilicon gate electrode 23GN in the element region 21NMOS. A source extension region 21c and a drain extension region 21d of the transistor are formed.

Further, in the step of FIG. 7J, an eighth resist pattern R ₈ covering the element regions 21A and 21NMOS is formed on the silicon substrate 21. In this state, B is 6 × 10 ¹³ under an acceleration voltage of 1 keV to 2 keV, for example. Ions are implanted at a dose of cm ^{−2 to} 6 × 10 ¹³ cm ⁻² to form the source extension region 21e and the drain extension region 21f of the p-channel MOS transistor on both sides of the polysilicon gate electrode 23GP.

  Further, in the step of FIG. 7K, a silicon oxide film having a thickness of 10 nm and a thickness are formed on the silicon substrate 21 so as to cover the exposed surface of the silicon substrate 21 and the upper surfaces and sidewall surfaces of the gate electrodes 23G, 23GN, and 23GP. An insulating film having a structure in which a 30 nm silicon nitride film is laminated is formed by a CVD method, and further etched back to form the sidewall insulating films 23WA and 23WB on the gate electrode 23G and the sidewall insulating film on the gate electrode 23GN. A sidewall insulating film 23WP is formed on the gate electrode 23GP.

Further, in the step of FIG. 7K, the device region 21PMOS is covered with a _ninth resist pattern R9, and in this state, P is applied to the device regions 21A and 21NMOS under an acceleration voltage of 8 keV to 10 keV, for example, 5 × 10 ¹⁵ cm ^−2. Ion implantation is performed at a dose of ˜8 × 10 ¹⁵ cm ^−2, the n + type source region 21S and the n + type drain region 21D are formed in the element region 21A, and the n + type of the n channel MOS transistor in the element region 21NMOS. A source region 21g and an n + -type drain region 21h are formed outside the sidewall insulating film 23WN. Note the sidewall insulation films 23WB in the step of FIG. 7K includes a silicide blocking region 23wb extending toward the second isolation region portion 21I ₂ from the gate electrode 23G, as a result, the drain region 21D is the gate electrode It is formed at a position about 0.2 μm away from the drain side end of 23G.

Next, a resist pattern _{R 10} of the 10 covering the device regions 21A and 21NMOS on the silicon substrate 21 is formed in the step of FIG. 7L, under the acceleration voltage of the B in this state for example 4keV~10keV, 4 × 10 ¹⁵ Ions are implanted at a dose of cm ^{−2 to} 6 × 10 ¹⁵ cm ⁻² to form p + -type source region 21 i and p + -type drain region 21 j of the p-channel MOS transistor outside the sidewall insulating film 23WP.

  Next, in the step of FIG. 7M, silicide regions 24G, 24S, and 24D are formed on the gate electrode 23G, the source diffusion region 21S, and the drain diffusion region 21D by the salicide method, and at the same time, the gate electrodes 23GN, 23GP, the source region 21g, Silicide layers 24 are also formed on 21i and drain regions 21h and 21j, respectively.

Further, in the step of FIG. 7N, an interlayer insulating film 25 is formed on the structure of the precursor FIG. 7M, in the step of FIG. 7O, a wiring pattern 26 is formed on the interlayer insulating film 25, and via plugs 26 ₁ are formed on the gate electrode 23G. The drain region 21h is connected to the source region 21S by a via plug 26 _{2 and} to the drain region 21D by a via plug 26 ₃ , the gate electrode 23GN by a via plug 26 ₄ , and the source region 21g by a via plug 26 _5. The via plug 26 _{6 is} connected to the gate electrode 23GP by a via plug 26 ₇ , the via plug 26 ₈ to the source region 21i, and the via plug 26 ₉ to the drain region 21j. by forming a _{1-26 9,} the same sheet An n-channel MOS transistor and the p-channel MOS transistor of the high voltage MOS transistor 20 and the CMOS device on the con substrate 21, at the same time, can be integrated in minimizing the additional mask steps.

  In the processes of FIGS. 10A to 10O, the manufacturing process of the high voltage MOS transistor 20 and the manufacturing process of the input / output p-channel MOS transistor and n-channel MOS transistor are shared except the processes of FIGS. 10F and 10G. I can see that Of the processes not shared, the process of FIG. 7G, that is, the process of forming a so-called triple well structure by forming the deep n-type well 21DNW, may be a process for manufacturing other elements depending on the type of the embedded element. May be shared with others.

  The formation of the silicide block structure 23wb in FIG. 7K can be performed without increasing the number of mask processes if it can be combined with another process for forming a resistance element, for example.

[Second Embodiment]
FIG. 8 shows a configuration of a high voltage MOS device 40 according to the second embodiment of the present invention.

Referring to FIG. 8, the high breakdown voltage MOS element 40 has a configuration in which two high breakdown voltage MOS transistors 20 are symmetrically arranged on the silicon substrate 21, and on the right side of the high breakdown voltage MOS transistor 20. the a gate electrode 23G and the source region 21S each gate electrode 23G _1, and the source region 21S ₁ in response to, another high voltage MOS transistors 20 ₁ to share the drain region 21D and the drain extension region 21b is, the high It is formed symmetrically with respect to the breakdown voltage MOS transistor 20.

High voltage MOS transistors 20 ₁ of the right thus includes a channel region 21 CH ₁ corresponding to the channel region 21 CH of the high voltage MOS transistor 20, a source region 21S ₁ corresponding to the source region 21S of the high voltage MOS transistors 20, A source extension region 21a ₁ corresponding to the source extension region 21a of the high breakdown voltage MOS transistor 20, a first shallow well 21PW ₁ corresponding to the p-type first shallow well 21PW, and the n-type second a shallow well 21NW ₁ of the second corresponding to the shallow well 21NW, have, and the gate electrode 23G ₁ of the high voltage MOS transistor 20 ₁ is the similar to the gate electrode 23G of the high voltage MOS transistor 20 A gate insulating film 22 between the silicon substrate 21 and That. Further, sidewall insulating films 23WA ₁ and 23WB ₁ corresponding to the sidewall insulating films 23WA and 23WB of the gate electrode 23 are formed on the gate electrode 23G ₁ , and a silicide layer 24G ₁ is formed corresponding to the silicide layer 24G. ing.

In addition the high voltage MOS transistors 20 _1, the on the source region 21S _1, the high voltage MOS transistor silicide layer 24S similar silicide layer 24S ₁ formed on the source region 21S of 20 is formed.

It said first and second well 21DW and 21NW, more space / 21PW the formation is not a deep well 21DNW of the n-type is shared with the high voltage MOS transistor 20 in the high voltage MOS transistors 20 _1, in the region / 21PW The shared drain extension region 21b is formed, and the shared drain region 21D is formed so as to be surrounded by the drain extension region 21b. The silicide layer 24D is formed on the surface of the drain region 21D.

  FIG. 9 is a plan view of the high voltage MOS device of FIG. 8 cut at a depth position just below the element isolation region portion 21I, similar to FIG.

Referring to FIG. 9, also in this embodiment, the region / 21PW is continuously surrounded, and a pn junction is formed by the first shallow well 21PW and the second shallow well 21NW, and the shallow well since the potentials of 21PW is fixed in a contact region 21SS, the high voltage MOS transistor noise caused by 20 and 20 ₁ are operated is propagated to the side of the middle of the silicon substrate 21, interfere with the operation of the other elements To solve the problem.

Note a high breakdown voltage MOS device according to the present embodiment, the high voltage MOS for transistor 20 and the high voltage MOS transistor 20 ₁ are symmetrically formed, if the gate electrode 23G and 23G ₁ in the silicon substrate 21 pattern - even when shifted to the left and right in the figure with respect to emissions, the gate electrode 23 overlaps the OWL ₁ and overlap length OWL and gate electrode 23 ₁ and the drain extension region 21b of the drain extension region 21b are complementary Preferred features are obtained that vary and maintain the overall output current unchanged.

  FIG. 10 is a plan view showing an element 40A according to a modification of the high voltage semiconductor element 40 of FIG. However, in FIG. 10, the side wall insulating films 23WA and 23WB and the silicide layers 24G, 24S, and 24D are not shown.

Referring to FIG. 10, a gate electrode 23G and 23G ₁ of FIG. 8 in this embodiment, it is formed by a single gate electrode 43G of the symmetrical taking rotational symmetry around the drain region 21D, the gate electrode It can be seen that a single drain extension region 21b is formed between 43G and the drain region 21D so as to surround the drain region 21D. The drain extension region 21b extends below the gate electrode 43G to a position indicated by a broken line 21be corresponding to the cross-sectional view of FIG.

Further, in the modification of FIG. 10, the source regions 21S and 21S _{1 of} FIG. 8 and the source extension regions 21a and 21a _{1 (} not shown) each constitute a single diffusion region, and the gate electrode 43G Surrounds continuously.

  Also in this embodiment, the p-type well 21PW and the n-type well 21NW are formed outside the element region 21A, and voltage fluctuations generated in the element region 21A become noise and the silicon substrate 21 is placed on the substrate surface. Problems that propagate along and interfere with other integrated semiconductor devices are avoided.

  When the impurity concentration of the p-type silicon substrate 21 is even lower than that described above, the high voltage MOS transistor 20 of FIG. 4 is modified to form the element region 21A as shown in FIG. It is also possible to form a well 21P− having a lower p-type impurity concentration than the first shallow well 21PW and a higher p-type impurity concentration than the silicon substrate 21, including the region / 21PW. .

  In the above description, a p-channel high voltage MOS transistor can be configured by inverting the conductivity type of each semiconductor layer and well.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A first substrate region defined by a device isolation region and having a first conductivity type;
In the first element region, formed on the surface of the semiconductor substrate via a gate insulating film, the first side forms a source side end, and the second side opposite to the first side forms a drain side end. A gate electrode,
In the semiconductor substrate, between the source side end of the gate electrode in the first element region and a first element isolation region portion of the element isolation region facing the source side end of the gate electrode. A second conductivity of a conductivity type opposite to the first conductivity type, formed to be separated from the source side end of the gate electrode by a first distance and extending to the first element isolation region portion. The source area of the type;
In the semiconductor substrate, between the drain side end of the gate electrode in the first element region and a second element isolation region portion of the element isolation region facing the drain side end of the gate electrode. The drain of the second conductivity type formed by being separated from the drain side end of the gate electrode by a second distance larger than the first distance and extending to the second element isolation region portion. Area,
In the semiconductor substrate, in the first element region, from the source region tip facing the side of the source region in contact with the first element isolation region portion toward the drain region, the gate electrode A source extension region extending beyond the source side edge by a third distance, having the second conductivity type, and having an impurity concentration lower than that of the source region;
In the semiconductor substrate, the first element region encloses the drain region, and the drain side end of the gate electrode extends from the second element isolation region portion toward the source region. A drain extension region extending beyond a fourth distance greater than the distance, having a second conductivity type and having an impurity concentration lower than that of the drain region,
In the semiconductor substrate, a channel region is formed between the source extension region and the drain extension region,
In the semiconductor substrate, a first well is formed below the source region and the source extension region to form a first pn junction with the first conductivity type and to the source region and the source extension region. And formed at a depth exceeding the lower end of the element isolation region,
A second well is formed below the first well by forming a second pn junction with the first conductivity type and the first well,
The MOS transistor according to claim 1, wherein the first well and the second well are not formed under the drain extension region and the drain region.
(Appendix 2)
Immediately below the element isolation region that defines the first element region, outside the first element region, the first well that wraps around the first well from the outside is continuous with the upper part of the second well. 3. The MOS transistor according to appendix 1, wherein three wells are formed of the second conductivity type.
(Appendix 3)
3. The MOS transistor according to claim 2, wherein the third well extends continuously surrounding the first well when viewed from a direction perpendicular to the surface of the semiconductor substrate.
(Appendix 4)
4. The MOS transistor according to appendix 2 or 3, wherein the lower end of the third well is formed to have substantially the same depth as the lower end of the first well.
(Appendix 5)
5. The MOS transistor according to claim 1, wherein the second well is continuously formed below the first well. 6.
(Appendix 6)
The drain extension region and the drain region are formed in a fourth well having the first conductivity type in the first element region and having an impurity concentration lower than that of the first well. 6. The MOS transistor according to any one of appendices 1 to 5, wherein the drain extension region and the drain region form a third pn junction with the fourth well.
(Appendix 7)
6. The MOS transistor according to any one of appendices 1 to 5, wherein the drain extension region and the drain region form a third pn junction with the semiconductor substrate. .
(Appendix 8)
The MOS transistor according to any one of appendices 1 to 7,
A semiconductor integrated circuit device comprising: a CMOS element formed on the semiconductor substrate;
The CMOS device includes an n-channel MOS transistor and a p-channel MOS transistor formed on the semiconductor substrate in the second and third device regions defined by the device isolation region,
The n-channel MOS transistor includes a fifth well formed in the second element region and having the first conductivity type, and the fifth well substantially contains the same impurity element as the first well. At the same concentration and depth,
The p-channel MOS transistor includes a sixth well formed in the third element region and having the second conductivity type, and the sixth well substantially contains the same impurity element as the third well. A semiconductor integrated circuit device comprising the same concentration and depth.
(Appendix 9)
The n-channel MOS transistor and the p-channel MOS transistor have respective gate insulating films, and the gate insulating film of the n-channel MOS transistor and the gate insulating film of the p-channel MOS transistor are the same as the gate insulating film of the MOS transistor. 9. The semiconductor integrated circuit device according to appendix 8, wherein the semiconductor integrated circuit device has the same composition and the same thickness.
(Appendix 10)
The first and second MOS transistors each comprising the MOS transistor according to any one of appendices 1 to 7 are arranged symmetrically on the semiconductor substrate, sharing the drain region and the drain extension region. A semiconductor device.

20, 20 ₁ high voltage MOS transistor 21 silicon substrate 21A element region 21CH channel region 21S, 21S ₁ , 41S source region 21D drain region 21SS contact region 21I element isolation region 21PW p-type first shallow well 21NW n-type second Shallow well / 21PW region where first shallow well is not formed 21DNW n-type deep well 21a source extension region 21b drain extension region 22 gate insulating film 23G, 23G ₁ , 43G gate electrode 23WA, 23WB, 23WA ₁ , 23WB ₁ gate sidewall insulating films 24G, 24S, 24D silicide layer 25 interlayer insulating film 26 wirings pattern - down 26 _{1-26 9} via plug 40,40A high breakdown voltage semiconductor device

Claims (5)

A first substrate region defined by a device isolation region and having a first conductivity type;
Said first element and the semiconductor substrate on the gate insulating film formed on the region, is formed on the gate insulating film, a second side edge opposite the first side edge and the first side edge A gate electrode having
Wherein in the semiconductor substrate, the said first side edge of the gate electrode in the first element region, a first isolation region portion opposed to said first side edge of said gate electrode of said device isolation region Between the first side of the gate electrode and a first distance from the first side end, and extending to the first element isolation region portion. A source region of a second conductivity type of the mold;
Wherein in the semiconductor substrate, the said second side edge of the gate electrode in the first element region, said second element isolation region portion facing the second side edge of said gate electrode of said device isolation region Between the second side end of the gate electrode and a second distance larger than the first distance, and extending to the second element isolation region portion. A drain region of two conductivity types;
In the semiconductor substrate, in the first element region, from the source region tip facing the side of the source region in contact with the first element isolation region portion toward the drain region, the gate electrode A source extension region extending beyond the first side edge by a third distance, having the second conductivity type, and having an impurity concentration lower than that of the source region;
In the semiconductor substrate, in the first element region, the second side edge of the gate electrode is wrapped around the drain region and from the second element isolation region portion toward the source region, A drain extension region extending beyond a fourth distance greater than a third distance, having a second conductivity type and having a lower impurity concentration than the drain region ;
In said semiconductor substrate, a channel region located between said source extension region and said drain extension region,
Forming a first pn junction with the first conductivity type with respect to the source region and the source extension region, located under the source region and the source extension region in the semiconductor substrate; and A first well formed at a depth exceeding a lower end portion of the isolation region, and being spaced apart from the drain extension region and the drain region in plan view ;
A second pn junction is formed between the first well and the second conductivity type, and is formed below the first well, and in plan view with the drain extension region and the drain region. A second well located at a distance ;
MOS transistor characterized by including .   Immediately below the element isolation region that defines the first element region, outside the first element region, the first well that wraps around the first well from the outside is continuous with the upper part of the second well. 3. The MOS transistor according to claim 1, wherein three wells are formed of the second conductivity type. The drain extension region and said drain region, said in the first element region, having said first conductivity type, formed in the front Symbol lower in the fourth well impurity concentration than the first well, the 3. The MOS transistor according to claim 1, wherein the drain extension region and the drain region form a third pn junction with the fourth well. 4. A MOS transistor according to claim 2 ;
A semiconductor integrated circuit device comprising: a CMOS element formed on the semiconductor substrate;
The CMOS device includes an n-channel MOS transistor and a p-channel MOS transistor formed on the semiconductor substrate in the second and third device regions defined by the device isolation region,
The n-channel MOS transistor includes a fifth well formed in the second element region and having the first conductivity type, and the fifth well contains the same impurity element as the first well. Including at one concentration and depth,
The p-channel MOS transistor includes a sixth well formed in the third element region and having the second conductivity type, and the sixth well contains the same impurity element as the third well. A semiconductor integrated circuit device comprising a single concentration and depth.   The first and second MOS transistors each comprising the MOS transistor according to any one of claims 1 to 3 are symmetrically arranged on the semiconductor substrate, sharing the drain region and the drain extension region. A semiconductor device characterized by that.

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