JP2006253334A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the driving power and breakdown voltage of a high breakdown voltage MOSFET. <P>SOLUTION: The semiconductor device comprises a high breakdown voltage MOSFET having a P type heavily doped source region 20 and a P type heavily doped drain region 18 formed in an N type well region 4 which is formed on a P type semiconductor substrate 2 while spaced apart from each other, a channel region 22 and an N type lightly doped drain region 10 formed in the heavily doped source region 20 between the heavily doped source region 20 and the heavily doped drain region 18, a gate insulation film 14 formed on the channel region 22 and the source side end of the lightly doped drain region 10, a field insulation film 12a formed on the lightly doped drain region 10 between the gate insulation film 14 and the heavily doped drain region 18, and a gate electrode 16 formed from above the gate insulation film 14 to above the field insulation film 12a wherein the lightly doped drain region 10 has such an impurity concentration distribution as it is sparse on the surface side of the semiconductor substrate 2 and dense on the deep side in a region beneath the gate insulation film 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a manufacturing method thereof.

  For example, a semiconductor integrated circuit having a charging control function for a mobile phone is normally driven at a voltage of 5 to 6 V (volt), and the rating is set to about 8 V. However, a voltage exceeding the normal rating, for example, 12V to 18V may be applied to the internal circuit by being connected to a defective charging adapter. As a semiconductor integrated circuit, it is desirable that the internal circuit operates normally without causing defects such as heat generation or failure even when the above problems occur.

  There are various means for raising the rating of the MOSFET, and one of them is a method of forming a thick oxide film under the gate oxide film on the drain side and forming a low concentration drain region under the thick oxide film. ing. A MOSFET in which a thick oxide film is formed by a field oxide film for element isolation is called a LOCOS offset transistor.

  When forming a LOCOS offset transistor, increasing the rating and increasing the driving capability are in a conflicting relationship. The reason for this is that when the concentration of the low concentration drain region is increased, the concentration of the electric field becomes remarkable in the vicinity of the gate insulating film, and the breakdown voltage between the drain and the semiconductor substrate decreases. In addition, since the extension of the depletion layer between the low concentration drain region and the semiconductor substrate is suppressed, the breakdown voltage between the semiconductor substrates is reduced. Conversely, when the concentration of the low-concentration drain region is decreased, the parasitic resistance of the drain is increased and the driving capability is decreased. Therefore, the structure of the low-concentration drain region is the key to realizing both at a higher level.

As a first conventional example, there is a MOSFET having a structure shown in FIG. 11 (see, for example, Patent Document 1). In this MOSFET, a thick field oxide film 82 is formed on the channel region side of the high-concentration first drain region 80, and a high-concentration and shallow second drain region 84 is formed directly below the field oxide film 82. Further, a deep third drain region 86 is formed at a low concentration so as to surround the second drain region 84.
By adopting such a drain structure, a high driving capability can be realized while increasing the breakdown voltage between the drain and the semiconductor substrate.

As a second conventional example, there is a MOSFET having a structure shown in FIG. 12 (see, for example, Patent Document 2). A thick oxide film 90 is formed on the channel region side of the high-concentration drain contact diffusion layer 88, and a P diffusion layer 92 is formed so as to surround the drain contact diffusion layer 88 from directly below the thick oxide film 90. Further, a shallow P-diffusion layer 94 having a low concentration is formed immediately below the thick oxide film 90.
The P − diffusion layer 94 is formed by introducing a N-type impurity having a conductivity type opposite to that of the drain contact diffusion layer 88 and the P diffusion layer 92 into the P diffusion layer 92 at a low concentration before forming the thick oxide film 90. Has been. Thereby, since the extension of the depletion layer at the drain end can be secured, a high breakdown voltage can be realized.

Further, as a third conventional example, there is a MOSFET having the structure shown in FIGS. 13A and 13B (see, for example, Patent Document 3). FIG. 13A is a cross-sectional view, and FIG. 13B is a plan view showing the N-drain offset region of FIG.
An N− drain offset region 98 and an N + source region 100 are formed on the surface of a P-type silicon substrate 96 with a channel region interposed therebetween. A field oxide film 104 thicker than the gate oxide film 102 is formed on the surface of the N-drain offset region 98. The gate oxide film 102 on the channel region extends along the surface of the N-drain offset region 98 and is connected to the field oxide film 104. Gate electrode 106 is formed from gate oxide film 102 to field oxide film 104.

In the region AB of FIG. 13B, the N-drain offset region 98 is formed in a comb shape. Therefore, the impurity concentration per unit area in the source-side protruding portion 108 of the N-drain offset region 98 is lower than the impurity concentration per unit area other than the source-side protruding portion 108 of the N-drain offset region 98. While preventing a decrease in breakdown voltage due to concentration, an increase in on-resistance, that is, a decrease in driving capability can be suppressed.
Japanese Patent No. 2668713 Japanese Patent No. 2730088 Japanese Patent Laid-Open No. 2003-204062

  However, in the structure of FIG. 11 (Patent Document 1), the impurity for the second drain region 84 having a high concentration and shallowness is introduced immediately below the field oxide film 82 before the field oxide film 82 is formed. There is a problem that the driving ability is easily affected by process fluctuations due to the influence of ion absorption into the inside and segregation of ions to the oxide film-semiconductor substrate interface. In addition, since the high-concentration and shallow second drain region 84 is formed near the gate oxide film, there is a problem that the electric field between the gate and the drain becomes strong and the breakdown voltage of the gate insulating film is lowered. Therefore, there is a restriction that the gate insulating film must be formed thicker than usual even in a MOSFET in which a high breakdown voltage is applied only to the drain side.

  In the structure shown in FIG. 12 (Patent Document 2), it is necessary to overlap the P− diffusion layer 94 with the lower region of the gate oxide film in order to suppress the variation in the driving capability of the high voltage MOSFET. However, when they are overlapped, the P- diffusion layer 94 having a relatively high concentration is in direct contact with the channel region. In such a structure, it is necessary to reduce the concentration of the P− diffusion layer 94 itself in order to ensure the extension of the depletion layer and improve the breakdown voltage, resulting in a decrease in the driving capability of the high breakdown voltage MOSFET. There was a problem.

  In the structure shown in FIG. 13 (Patent Document 3), the area AB of the N-drain offset region 98 is controlled by the planar shape of the implantation mask, so that there is a limit to narrowing the AB distance. It was. When the interval A-B is long, there is a problem that the on-resistance is suppressed and the transistor size is reduced. Further, according to the method of changing the impurity concentration depending on the mask shape, there is a limit to the concentration distribution shape finally obtained.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of improving the driving capability and breakdown voltage of a high breakdown voltage MOSFET and a manufacturing method thereof.

A semiconductor device according to the present invention includes a second conductivity type high concentration source region and a high concentration drain region formed in a well region of a first conductivity type formed on a semiconductor substrate, and the high concentration source region. A channel region formed adjacent to the high-concentration source region between the high-concentration drain regions; a second conductivity type low-concentration drain region formed between the channel region and the high-concentration drain region; A gate insulating film formed over the channel region and the source-side end of the lightly doped drain region, and formed on the lightly doped drain region between the gate insulating film and the heavily doped drain region; A field insulating film having a thickness greater than that of the gate insulating film, and a gate electrode formed over the field insulating film from the gate insulating film; With a high voltage MOSFET having the above low-concentration drain region are those having the concentration distribution of the side dark deep thin semiconductor substrate surface side second conductivity type impurity in the region below the gate insulating film.
Here, the first conductivity type means P type or N type, and the second conductivity type means N type or P type opposite to the first conductivity type.

In the semiconductor device of the present invention, the low concentration drain region may cover the high concentration drain region.
Furthermore, the end of the lightly doped drain region on the source side may be formed with a gap from the gate insulating film.

  Further, the concentration distribution of the second conductivity type impurity in the depth direction in the region under the gate insulating film of the low concentration drain region has two peaks, and the impurity concentration at the peak position on the semiconductor substrate surface side is on the deep side. The impurity concentration may be lower than the peak position. Such an impurity concentration distribution can be formed by ion implantation including a first ion implantation step and a second ion implantation step in which the acceleration energy is smaller and the implantation amount is smaller than those in the first ion implantation step.

  Further, the lower end of the lightly doped drain region is formed so that the region under the field insulating film is shallower than other regions, and impurities in the lightly doped drain region near the field insulating film are formed in the field oxide film. It may not be taken in. Such a structure can be formed by performing an ion implantation process for forming a low-concentration drain region after forming a field insulating film.

A first aspect of a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device for forming a semiconductor device according to the present invention, which includes the following steps (A) to (F): A method for manufacturing a semiconductor device.
(A) forming a first conductivity type well region in a semiconductor substrate;
(B) A second conductivity type impurity is implanted into a predetermined region of the well region by an ion implantation method, and a low concentration drain region having a concentration distribution of the second conductivity type impurity is obtained. Forming step,
(C) forming a field insulating film in a predetermined region at least on the surface of the low-concentration drain region;
(D) forming a gate insulating film adjacent to the field oxide film at least on the surface of the well region;
(E) forming a gate electrode from above the gate insulating film to the field insulating film;
(F) Impurities of the second conductivity type are implanted by the ion implantation method using the gate electrode and the field insulating film as a mask to form a high concentration source region in the well region and a high concentration in the low concentration drain region. Forming a concentration drain region;

A second aspect of the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device for forming the semiconductor device of the present invention, comprising the following steps (A) to (F): A method for manufacturing a semiconductor device.
(A) forming a first conductivity type well region in a semiconductor substrate;
(B) forming a field insulating film at least in a predetermined region on the surface of the well region;
(C) Second conductivity type impurities are implanted into a predetermined region of the well region including the field insulating film formation region by ion implantation, so that the semiconductor substrate surface side is thin and the deep side is dark. Forming a low concentration drain region having a concentration distribution;
(D) forming a gate insulating film adjacent to the field oxide film at least on the surface of the well region;
(E) forming a gate electrode from above the gate insulating film to the field insulating film;
(F) Impurities of the second conductivity type are implanted by the ion implantation method using the gate electrode and the field insulating film as a mask to form a high concentration source region in the well region and a high concentration in the low concentration drain region. Forming a concentration drain region;

  In the step (B) of the first aspect of the manufacturing method and the step (C) of the second aspect, the ion implantation for forming the low-concentration drain region is performed by implanting a second conductivity type impurity. In addition, an example including a second ion implantation step of implanting the second conductivity type impurity under the condition that the acceleration energy is smaller and the implantation amount is smaller than that of the first ion implantation step can be given. Here, the order of the first ion implantation step and the second ion implantation step may be first.

  Further, in the step (B) of the first aspect of the manufacturing method and the step (C) of the second aspect, the ion implantation is performed so that the implantation depth of the second conductivity type impurity is 0.2 μm or more. May be.

  In the semiconductor device according to the present invention, the low-concentration drain region of the high breakdown voltage MOSFET has a concentration distribution of the second conductivity type impurity in the region under the gate insulating film where the semiconductor substrate surface side is thin and the deep side is dense. Electric field concentration in the vicinity of the film can be alleviated and the operating breakdown voltage can be improved. Furthermore, since the impurity concentration distribution in the low concentration drain region has a deep concentration distribution on the deep side, the resistance value of the drain region can be lowered, and a large current can flow. Thus, the driving capability and breakdown voltage of the high breakdown voltage MOSFET can be improved.

  In the semiconductor device of the present invention, if the low concentration drain region covers the high concentration drain region, the low concentration drain region is formed between the high concentration drain region and the semiconductor substrate. The junction breakdown voltage between the high concentration drain region and the semiconductor substrate can be improved.

  Further, if the end portion on the source side of the lightly doped drain region is formed with a gap from the gate insulating film, the concentration of the electric field in the vicinity of the gate insulating film can be further reduced, so that the operating breakdown voltage is reduced. Further improvement can be achieved.

  Further, the lower end of the low concentration drain region is formed so that the region under the field insulating film is shallower than other regions, and impurities in the low concentration drain region near the field insulating film are not taken into the field oxide film. That is, after the field insulating film is formed, ion implantation for forming a low-concentration drain region is performed, and impurities are extracted due to the formation of the field insulating film (a phenomenon in which impurities are taken into the field insulating film in the process of forming the field insulating film) If this does not occur, the impurity concentration in the low-concentration drain region can be prevented from decreasing, and the driving capability can be prevented from decreasing.

In the first aspect of the manufacturing method of the present invention, a step of forming a first conductivity type well region in a semiconductor substrate, (A) the concentration distribution of the second conductivity type impurity is thin on the semiconductor substrate surface side and deep on the deep side by ion implantation. Forming a low-concentration drain region in a predetermined region of the well region (B), forming a field insulating film in a predetermined region on the surface of the low-concentration drain region (C), and forming a gate insulating film (D ), Forming a gate electrode (E), and
Since the step (F) of forming the high concentration source region in the well region and forming the high concentration drain region in the low concentration drain region is included, the high breakdown voltage MOSFET constituting the semiconductor device of the present invention can be formed. it can.

  In the step (B) of the first aspect of the manufacturing method, the ion implantation includes a first ion implantation step for implanting a second conductivity type impurity, and a condition in which the acceleration energy is small and the implantation amount is small compared to the first ion implantation step. By including the second ion implantation step of implanting the second conductivity type impurity, it is possible to form a low concentration drain region in which the semiconductor substrate surface side is thin and the deep side has a dense impurity concentration distribution.

  Further, in the step (B) of the first aspect of the manufacturing method, if the ion implantation is performed so that the impurity implantation depth is 0.2 μm or more, the semiconductor substrate surface side is formed by one ion implantation treatment. A low-concentration drain region having a dense impurity concentration distribution on the thin and deep side can be formed.

In the second aspect of the manufacturing method of the present invention, a step (A) of forming a first conductivity type well region on a semiconductor substrate, a step (B) of forming a field insulating film in a predetermined region on the surface of the well region, ion implantation The second conductivity type impurity is implanted into a predetermined region of the well region including the field insulating film formation region by a method, and a low concentration drain region having a second conductivity type impurity concentration distribution in which the semiconductor substrate surface side is thin and the deep side is dense. A step (C) of forming, a step (D) of forming a gate insulating film, a step (E) of forming a gate electrode, a high concentration source region in the well region, and a high concentration drain region in the low concentration drain region. Since the step (F) of forming the semiconductor device is included, the high breakdown voltage MOSFET constituting the semiconductor device of the present invention can be formed.
Further, after the field insulating film is formed (step (B)), the low concentration drain region is formed (step (C)), and the impurity is not sucked out due to the formation of the field insulating film. Therefore, it is possible to prevent the impurity concentration in the low-concentration drain region from being lowered and the driving ability from being lowered.

  In the step (C) of the second aspect of the manufacturing method, the ion implantation includes a first ion implantation step for implanting a second conductivity type impurity, and a condition in which the acceleration energy is small and the implantation amount is small compared to the first ion implantation step. By including the second ion implantation step of implanting the second conductivity type impurity, it is possible to form a low concentration drain region in which the semiconductor substrate surface side is thin and the deep side has a dense impurity concentration distribution.

  Further, in the step (C), if the ion implantation is performed so that the impurity implantation depth is 0.2 μm or more, the concentration of the impurity on the semiconductor substrate surface side is thin and deep on one ion implantation process. A low concentration drain region having a distribution can be formed.

  Examples of the semiconductor substrate of the present invention will be described below together with examples of the manufacturing method of the present invention. In addition, the Example shown below is an example to which this invention is applied, and this invention is not limited to this.

[Example 1]
FIG. 1 is a process cross-sectional view for explaining an embodiment of the first aspect of the manufacturing method, and (E) is a cross-sectional view showing an embodiment of the semiconductor device. FIG. 2A is a cross-sectional view showing a simulation result of the impurity concentration distribution of this example, and FIG. 2B is a diagram showing an impurity concentration profile in the depth direction at the position AA in FIG. First, an embodiment of a semiconductor device will be described with reference to FIGS.

  An N-type well region 4 is formed in the P-type semiconductor substrate 2. A P-type low concentration drain region 10 is formed in the N-type well region 4. The P-type low concentration drain region 10 has a region 10a having a high impurity concentration and a region 10b having a lower impurity concentration than the region 10a.

  A field oxide film (field insulating film) 12 is formed on the surface of the P-type semiconductor substrate 2 near the periphery of the N-type well region 4 formation region and the periphery of the P-type low-concentration drain region 10 formation region. A gate oxide film (gate insulating film) 14 is formed on the surface of the N-type well region 4 in succession to the field oxide film 12 a formed near one end of the P-type low concentration drain region 10. Gate electrode 16 is formed from gate oxide film 14 to field oxide film 12a.

  A P-type high concentration drain region 18 is formed in the vicinity of the surface of the P-type low concentration drain region 10 with a gap from the gate electrode 16. A P-type high concentration source region 20 is formed in the vicinity of the surface of the N-type well region 4 so as to be adjacent to or overlapping with the side surface of the gate electrode 16 opposite to the P-type high concentration drain region 18 side. The P-type high-concentration source region 20 and the P-type low-concentration drain region 10 are arranged with a space therebetween, and the region near the surface of the N-type well region 4 between the regions 10 and 20 constitutes a channel region 22.

  As shown in FIG. 2B, the P-type low concentration drain region 10 has a concentration distribution of impurities in the region below the gate oxide film 14 where the surface side of the P-type semiconductor substrate 2 is thin and the deep side is deep. Thereby, the electric field concentration in the vicinity of the gate oxide film 14 can be relaxed, and the operating breakdown voltage can be improved. Further, since the impurity concentration distribution of the P-type low concentration drain region 10 has a deep concentration distribution on the deep side, the resistance value of the P-type low concentration drain region 10 can be lowered and a large current can flow. Therefore, the driving capability and breakdown voltage of the high breakdown voltage MOSFET can be improved.

Further, the P-type low concentration drain region 10 covers the P-type high concentration drain region 18, and the P-type low concentration drain region 10 is formed between the P-type high concentration drain region 18 and the P-type semiconductor substrate 2. Thus, the junction breakdown voltage between the P-type high concentration drain region 18 and the P-type semiconductor substrate 2 can be improved.
Furthermore, since the end 10c of the P-type low concentration drain region 10 on the P-type high concentration source region 20 side is formed with a gap from the gate oxide film 14, the concentration of the electric field near the gate oxide film 14 is further alleviated. is doing.

An embodiment of the first aspect of the manufacturing method will be described with reference to FIG. Hereinafter, the descriptions of (A) to (E) correspond to (A) to (E) in FIG.
(A): A resist pattern (not shown) is formed on the P-type semiconductor substrate 2 by photolithography to define an N-type well region formation area, and the resist pattern is used as a mask, for example, N-type Phosphorus ions, which are impurities, are implanted under the conditions of an acceleration energy of 160 KeV and an implantation amount of 1 × 10 ¹³ cm ⁻² . After removing the resist pattern, for example, heat treatment is performed for 2 hours under conditions of a temperature of 1150 ° C. and a nitrogen atmosphere, and the implanted phosphorus is diffused and activated to form the N-type well region 4.

(B): In order to demarcate the formation region of the low-concentration drain region, the ion implantation resist pattern 6 is formed on the P-type semiconductor substrate 2 by photolithography, and the first time using the ion implantation resist pattern 6 as a mask. Ion implantation (first ion implantation step). In the first ion implantation, for example, boron 8a which is a P-type impurity is implanted under the conditions of an acceleration energy of 140 KeV and an implantation amount of 5 × 10 ¹³ cm ⁻² .

(C): Second ion implantation (second ion implantation step) is performed with the ion implantation resist pattern 6 left. In the second ion implantation, boron 8b is implanted under the conditions that the acceleration energy is smaller and the implantation amount is smaller than that of the first ion implantation, for example, the acceleration energy is 50 KeV and the implantation amount is 5 × 10 ¹² cm ⁻² .

(D): After removing the resist pattern 6 for ion implantation, a nitride film as an oxidation resistant film is formed on the entire surface of the P-type semiconductor substrate 2, and the nitride film is patterned using a photoengraving technique and an etching technique. A nitride film pattern (not shown) for defining the field oxide film is formed. For example, heat treatment is performed for 1 hour under conditions of a temperature of 1000 ° C. and an oxidizing atmosphere to form the field oxide films 12 and 12a. By this heat treatment, the boron ions 8a and 8b implanted in the steps (B) and (C) are diffused and activated, and the P-type low concentration drain region 10 is formed. Here, the boron ions 8a and 8b are diffused and activated simultaneously with the formation of the field oxide films 12 and 12a. However, the present invention is not limited to this, and the boron ions 8a and 8b are diffused and activated. A dedicated heat treatment process may be provided.
After removing the nitride film pattern and further removing the oxide film on the surface of the P-type semiconductor substrate 2 other than the formation region of the field oxide films 12 and 12a, a heat treatment is performed in an oxygen atmosphere to form the gate oxide film.

(E): A polysilicon film is formed on the entire surface of the P-type semiconductor substrate 2, and the polysilicon film is patterned by using a photoengraving technique and an etching technique, and polysilicon is formed over the gate oxide film 14 and the field oxide film 12a. A gate electrode 16 made of a film is formed.
Ion implantation is performed using field oxide films 12 and 12a and gate electrode 16 as a mask to form P-type high-concentration drain region 18 in P-type low-concentration drain region 10, and P-type high-concentration source in N-type well region 4. Region 20 is formed. In this ion implantation, for example, BF ₂ (boron difluoride) ions are implanted under the conditions of an acceleration energy of 30 KeV and an implantation amount of 5 × 10 ¹⁵ cm ⁻² . Thereafter, a heat treatment for diffusing and activating the injected BF ₂ is performed.

In this embodiment of the manufacturing method, ion implantation is performed twice before the field oxide film 12 is formed, and the second ion implantation is performed so that a smaller amount of ions is implanted in a shallower region than the first ion implantation. Therefore, as shown in FIG. 2A, the P-type low-concentration drain region 10 has an impurity concentration distribution in the region below the gate oxide film 14 where the surface side of the P-type semiconductor substrate 2 is thin and the deep side is dense.
Further, as shown in FIG. 2B, the impurity concentration distribution in the depth direction in the region under the gate oxide film 14 of the P-type low concentration drain region 10 has two peaks, and the peak on the surface side of the semiconductor substrate 2. The impurity concentration at the position is lower than the impurity concentration at the peak position on the deep side.

[Example 2]
FIG. 3 is a process cross-sectional view for explaining another embodiment of the first aspect of the manufacturing method, and FIG. 3E is a cross-sectional view showing another embodiment of the semiconductor device. 4A is a cross-sectional view showing a simulation result of the impurity concentration distribution of this embodiment, and FIGS. 4B and C are diagrams showing an impurity concentration profile in the depth direction at the BB position in FIG. Yes, (B) shows the state immediately after injection, and (C) shows the state after thermal diffusion treatment. In FIGS. 3 and 4, the same reference numerals are given to portions that perform the same functions as those in FIGS. 1 and 2.

  Embodiments of the semiconductor device will be described with reference to FIGS. Description of the same portions as those of the above-described embodiment of the semiconductor device described with reference to FIGS.

In this embodiment, the impurity concentration distribution of the P-type low-concentration drain region 10 is different from the above-described embodiment described with reference to FIGS.
Also in this embodiment, as shown in FIG. 4C, the P-type low-concentration drain region 10 has a concentration distribution of impurities in which the surface side of the P-type semiconductor substrate 2 is thin and the deep side is deep in the region below the gate oxide film 14. . Thereby, the electric field concentration in the vicinity of the gate oxide film 14 can be relaxed, and the operating breakdown voltage can be improved. Further, since the impurity concentration distribution of the P-type low concentration drain region 10 has a deep concentration distribution on the deep side, the resistance value of the P-type low concentration drain region 10 can be lowered and a large current can flow.

Furthermore, also in this embodiment, since the P-type low concentration drain region 10 covers the P-type high concentration drain region 18, the junction breakdown voltage between the P-type high concentration drain region 18 and the P-type semiconductor substrate 2 can be improved. it can.
Furthermore, since the end 10c of the P-type low concentration drain region 10 on the P-type high concentration source region 20 side is formed with a gap from the gate oxide film 14, the concentration of the electric field near the gate oxide film 14 is further alleviated. is doing.

Another embodiment of the first aspect of the manufacturing method will be described with reference to FIG. Hereinafter, the descriptions of (A) to (E) correspond to (A) to (E) in FIG.
(A): The P-type semiconductor substrate 2N-type well region 4 is formed by the same process as the process (A) described with reference to FIG.

(B): A resist pattern 6 for ion implantation is formed on the P-type semiconductor substrate 2 by a photoengraving technique in order to define a formation region of the low concentration drain region. For example, boron 8 which is a P-type impurity is implanted under the conditions of an acceleration energy of 140 KeV and an implantation amount of 1 × 10 ¹⁴ cm ^{−2 using} the ion implantation resist pattern 6 as a mask. The implantation depth of boron 8 implanted here is 0.45 μm, for example.

(C): After removing the resist pattern 6 for ion implantation, for example, heat treatment is performed for 1 hour under conditions of a temperature of 1000 ° C. in a nitrogen atmosphere to diffuse and activate the boron ions 8 to form the P-type low concentration drain region 10. It is formed (see also FIG. 4C).

(D): Field oxide films 12 and 12a are formed in a predetermined region on the surface of the P-type semiconductor substrate 2 by the same process as the process (D) described with reference to FIG. 14 is formed. Even in this heat treatment, the boron ions 8 implanted in the step (B) are diffused and activated. Boron ions 8 may be diffused and activated in this step without performing a dedicated heat treatment step (the above step (C)) for diffusing and activating boron ions 8.

(E): The gate electrode 16, the P-type high-concentration drain region 18 and the P-type high-concentration source region 20 are formed by the same step as the step (E) described with reference to FIG.

  In this embodiment of the manufacturing method, in the step (B), since the ion implantation is performed so that the impurity implantation depth is 0.2 μm or more, here 0.45 μm, the P-type low concentration drain region 10 The P-type semiconductor substrate 2 has a thin impurity concentration distribution on the thin side and a deep side. In this embodiment, since the P-type lightly doped drain region 10 is formed by one ion implantation process, the impurity concentration distribution in the depth direction in the region under the gate oxide film 14 of the P-type lightly doped drain region 10 is It has only one peak (see FIG. 4C).

[Example 3]
FIG. 5 is a process sectional view for explaining one embodiment of the second aspect of the manufacturing method, and FIG. 5E is a sectional view showing still another embodiment of the semiconductor device. 6A is a cross-sectional view showing the simulation result of the impurity concentration distribution of this example, and FIG. 6B is a diagram showing the impurity concentration profile in the depth direction at the CC position in FIG. In FIGS. 5 and 6, the same reference numerals are given to portions that perform the same functions as those in FIGS. 1 and 2.

  An example of a semiconductor device will be described with reference to FIGS. Description of the same portions as those of the above-described embodiment of the semiconductor device described with reference to FIGS.

In this embodiment, the impurity concentration distribution and the shape of the lower end of the P-type low-concentration drain region 10 are different from the above-described embodiment described with reference to FIGS.
Also in this embodiment, as shown in FIG. 6B, the P-type low-concentration drain region 10 has a concentration distribution of impurities in which the surface side of the P-type semiconductor substrate 2 is thin and the deep side is deep in the region below the gate oxide film 14. . Thereby, the electric field concentration in the vicinity of the gate oxide film 14 can be relaxed, and the operating breakdown voltage can be improved. Further, since the impurity concentration distribution of the P-type low concentration drain region 10 has a deep concentration distribution on the deep side, the resistance value of the P-type low concentration drain region 10 can be lowered and a large current can flow.

Furthermore, also in this embodiment, since the P-type low concentration drain region 10 covers the P-type high concentration drain region 18, the junction breakdown voltage between the P-type high concentration drain region 18 and the P-type semiconductor substrate 2 can be improved. it can.
Furthermore, since the end 10c of the P-type low concentration drain region 10 on the P-type high concentration source region 20 side is formed with a gap from the gate oxide film 14, the concentration of the electric field near the gate oxide film 14 is further alleviated. is doing.

  In this embodiment, as shown in FIGS. 5E and 6A, the lower end of the P-type low-concentration drain region 10 is formed shallower in the region under the field oxide film 12a than in other regions. Thus, the impurities in the P-type low concentration drain region 10 near the field insulating film 12a are not taken into the field oxide film 12a. Thereby, a decrease in the impurity concentration of the P-type low concentration drain region 10 can be prevented, and a decrease in driving ability can be prevented.

An embodiment of the second aspect of the manufacturing method will be described with reference to FIG. Hereinafter, the descriptions of (A) to (E) correspond to (A) to (E) in FIG.
(A): The P-type semiconductor substrate 2N-type well region 4 is formed by the same process as the process (A) described with reference to FIG.

(B): Field oxide films 12 and 12a are formed in a predetermined region on the surface of the P-type semiconductor substrate 2 under the same conditions as in the step (D) described with reference to FIG.

(C): In order to demarcate the formation region of the low concentration drain region, the resist pattern 6 for ion implantation is formed on a predetermined region of the P-type semiconductor substrate 2 including the formation region of the field oxide film 12 by photolithography. The first ion implantation (first ion implantation step) is performed using the ion implantation resist pattern 6 as a mask. In the first ion implantation, for example, boron 8a which is a P-type impurity is implanted under the conditions of an acceleration energy of 140 KeV and an implantation amount of 5 × 10 ¹³ cm ⁻² .
A second ion implantation (second ion implantation step) is performed with the ion implantation resist pattern 6 left. In the second ion implantation, boron 8b is implanted under the conditions that the acceleration energy is smaller and the implantation amount is smaller than that of the first ion implantation, for example, the acceleration energy is 50 KeV and the implantation amount is 5 × 10 ¹² cm ⁻² .
Here, in the region where field oxide films 12 and 12a are formed, field oxide films 12 and 12a function as implantation masks for boron ions 8a and 8b. That is, the implantation depth of boron ions 8a and 8b becomes shallow in the formation region of field oxide films 12 and 12a.

(D): After removing the resist pattern 6 for ion implantation, for example, heat treatment is performed for 1 hour under conditions of a temperature of 1000 ° C. in a nitrogen atmosphere to diffuse and activate the boron ions 8a and 8b to form a P-type low-concentration drain region 10 is formed.
Here, at the lower end of the P-type low-concentration drain region 10, the implantation depth of the boron ions 8a and 8b is shallow in the formation region of the field oxide films 12 and 12a in the step (C). At the lower end of the drain region 10, the region under the field oxide film 12a is formed shallower than other regions. Impurities in the P-type low concentration drain region 10 in the vicinity of the field insulating film 12a are not taken into the field oxide film 12a (see FIG. 6A).
Thereafter, a gate oxide film 14 is formed.

(E): The gate electrode 16, the P-type high-concentration drain region 18 and the P-type high-concentration source region 20 are formed by the same step as the step (E) described with reference to FIG.

In this embodiment of the manufacturing method, after the field oxide film 12 is formed, ion implantation is performed twice, and the second ion implantation is performed so that a smaller amount of ions is implanted in a region shallower than the first ion implantation. Therefore, as shown in FIG. 6A, the P-type low-concentration drain region 10 has a concentration distribution of impurities in which the surface side of the P-type semiconductor substrate 2 is thin and the deep side is deep in the region below the gate oxide film 14.
In addition, as shown in FIG. 6B, the impurity concentration distribution in the depth direction in the region under the gate oxide film 14 of the P-type low concentration drain region 10 has two peaks, and the peak on the surface side of the semiconductor substrate 2. The impurity concentration at the position is lower than the impurity concentration at the peak position on the deep side.

[Example 4]
FIG. 7 is a process cross-sectional view for explaining another example of the second aspect of the manufacturing method, and FIG. 7E is a cross-sectional view showing still another example of the semiconductor device. FIG. 8A is a cross-sectional view showing the simulation result of the impurity concentration distribution of this embodiment, and FIG. 8B is a diagram showing the impurity concentration profile in the depth direction at the DD position in FIG. 7 and 8, the same reference numerals are given to the portions that perform the same functions as those in FIGS. 1 and 2.

  An example of a semiconductor device will be described with reference to FIGS. Description of the same portions as those of the above-described embodiment of the semiconductor device described with reference to FIGS.

In this embodiment, the impurity concentration distribution and the shape of the lower end of the P-type low-concentration drain region 10 are different from the above-described embodiment described with reference to FIGS.
Also in this embodiment, as shown in FIG. 8B, the P-type low-concentration drain region 10 has a concentration distribution of impurities in which the surface side of the P-type semiconductor substrate 2 is thin and the deep side is deep in the region below the gate oxide film 14. . Thereby, the electric field concentration in the vicinity of the gate oxide film 14 can be relaxed, and the operating breakdown voltage can be improved. Further, since the impurity concentration distribution of the P-type low concentration drain region 10 has a deep concentration distribution on the deep side, the resistance value of the P-type low concentration drain region 10 can be lowered and a large current can flow.

Furthermore, also in this embodiment, since the P-type low concentration drain region 10 covers the P-type high concentration drain region 18, the junction breakdown voltage between the P-type high concentration drain region 18 and the P-type semiconductor substrate 2 can be improved. it can.
Furthermore, since the end 10c of the P-type low concentration drain region 10 on the P-type high concentration source region 20 side is formed with a gap from the gate oxide film 14, the concentration of the electric field near the gate oxide film 14 is further alleviated. is doing.

  In this embodiment, as shown in FIGS. 7E and 8A, the lower end of the P-type low concentration drain region 10 is formed shallower in the region under the field oxide film 12a than the other regions. Thus, the impurities in the P-type low concentration drain region 10 near the field insulating film 12a are not taken into the field oxide film 12a. Thereby, a decrease in the impurity concentration of the P-type low concentration drain region 10 can be prevented, and a decrease in driving ability can be prevented.

Another embodiment of the second aspect of the manufacturing method will be described with reference to FIG. Hereinafter, descriptions of (A) to (E) correspond to (A) to (E) in FIG.
(A): The P-type semiconductor substrate 2N-type well region 4 is formed by the same process as the process (A) described with reference to FIG.

(B): Field oxide films 12 and 12a are formed in a predetermined region on the surface of the P-type semiconductor substrate 2 under the same conditions as in the step (D) described with reference to FIG.

(C): In order to define the formation region of the low concentration drain region, the resist pattern 6 for ion implantation is formed on a predetermined region of the P-type semiconductor substrate 2 including the formation region of the field oxide film 12 by photolithography. . For example, boron 8 which is a P-type impurity is implanted under the conditions of an acceleration energy of 140 KeV and an implantation amount of 1 × 10 ¹⁴ cm ^{−2 using} the ion implantation resist pattern 6 as a mask. The implantation depth of boron 8 implanted here is 0.35 μm, for example.
Here, in the region where field oxide films 12 and 12a are formed, field oxide films 12 and 12a function as implantation masks for boron ions 8a and 8b. That is, the implantation depth of boron ions 8a and 8b becomes shallow in the formation region of field oxide films 12 and 12a.

(D): After removing the resist pattern 6 for ion implantation, for example, heat treatment is performed for 1 hour under conditions of a temperature of 1000 ° C. in a nitrogen atmosphere to diffuse and activate the boron ions 8 to form the P-type low concentration drain region 10. Form.
Here, at the lower end of the P-type low-concentration drain region 10, the implantation depth of the boron ions 8a and 8b is shallow in the formation region of the field oxide films 12 and 12a in the step (C). At the lower end of the drain region 10, the region under the field oxide film 12a is formed shallower than other regions. Impurities in the P-type low concentration drain region 10 in the vicinity of the field insulating film 12a are not taken into the field oxide film 12a (see FIG. 8A).
Thereafter, a gate oxide film 14 is formed.

(E): The gate electrode 16, the P-type high-concentration drain region 18 and the P-type high-concentration source region 20 are formed by the same step as the step (E) described with reference to FIG.

  In this embodiment of the manufacturing method, in the step (C), the ion implantation is performed so that the impurity implantation depth is 0.2 μm or more, here 0.35 μm. The P-type semiconductor substrate 2 has a thin impurity concentration distribution on the thin side and a deep side. In this embodiment, since the P-type lightly doped drain region 10 is formed by one ion implantation process, the impurity concentration distribution in the depth direction in the region under the gate oxide film 14 of the P-type lightly doped drain region 10 is It has only one peak (see FIG. 8B).

In the above embodiment, the P-type low concentration drain region 10 is formed to cover the P-type high concentration drain region 18, but the semiconductor device of the present invention is not limited to this.
For example, as shown in FIG. 9, a P-type low concentration drain region 10 may be formed between the channel region 22 and the high concentration drain region 18. It can be applied to any of the embodiments of the semiconductor device. Further, this structure can be formed by changing the formation region of the ion implantation resist pattern 6 for defining the formation region of the P-type low concentration drain region 10 in the embodiment of the manufacturing method. Thereby, in the region under the gate oxide film 14 with respect to the P-type low-concentration drain region 10, it is possible to have a concentration distribution of impurities where the surface side of the P-type semiconductor substrate 2 is thin and the deep side is dense.

In the above embodiment, the source side end of the surface portion of the P-type lightly doped drain region 10 is formed near the boundary between the gate oxide film 14 and the field oxide film 12a. However, the present invention is not limited to this. It is not something.
For example, as shown in FIG. 10, the source side end of the surface portion of the P-type lightly doped drain region 10 may be disposed under the gate insulating film 14. This structure can also be applied to any of the embodiments of the semiconductor device. This structure can also be formed by changing the formation region of the ion implantation resist pattern 6 in the embodiment of the manufacturing method. Thereby, in the region under the gate oxide film 14 with respect to the P-type low-concentration drain region 10, it is possible to have a concentration distribution of impurities where the surface side of the P-type semiconductor substrate 2 is thin and the deep side is dense.

Further, the conductivity types of the semiconductor substrate, well region, drain region, and source region shown in the above embodiment are merely examples, and the present invention is not limited to this, and these may be changed to the reverse conductivity type. Good.
Further, the implantation conditions such as the implanted ion species, ion implantation amount, and implantation energy in the ion implantation of the above-described examples are merely examples of preferred embodiments of the present invention, and the present invention is not limited thereto. .

It is process sectional drawing for demonstrating one Example of the 1st aspect of a manufacturing method, (E) is sectional drawing which shows one Example of a semiconductor device. (A) is sectional drawing which shows the simulation result of the impurity concentration distribution of this Example, (B) is a figure which shows the impurity concentration profile of the depth direction in the AA position of (A). It is process sectional drawing for demonstrating the other Example of the 1st aspect of a manufacturing method, (E) is sectional drawing which shows the other Example of a semiconductor device. (A) is sectional drawing which shows the simulation result of the impurity concentration distribution of this Example, (B) And (C) is a figure which shows the impurity concentration profile of the depth direction in the BB position of (A), (B) shows the state immediately after injection, and (C) shows the state after thermal diffusion treatment. It is process sectional drawing for demonstrating one Example of the 2nd aspect of a manufacturing method, (E) is sectional drawing which shows the further another Example of a semiconductor device. (A) is sectional drawing which shows the simulation result of the impurity concentration distribution of this Example, (B) is a figure which shows the impurity concentration profile of the depth direction in CC position of (A). It is process sectional drawing for demonstrating the other Example of the 2nd aspect of a manufacturing method, (E) is sectional drawing which shows the further another Example of a semiconductor device. (A) is sectional drawing which shows the simulation result of the impurity concentration distribution of this Example, (B) is a figure which shows the impurity concentration profile of the depth direction in the DD position of (A). It is sectional drawing which shows other Example of a semiconductor device. It is sectional drawing which shows the simulation result of impurity concentration distribution of the further another Example of a semiconductor device. It is sectional drawing for demonstrating an example of the conventional semiconductor device. It is sectional drawing for demonstrating the other example of the conventional semiconductor device. It is a figure for demonstrating the further another example of the conventional semiconductor device, (A) is sectional drawing, (B) is an enlarged plan view of the drain offset area | region of (A).

Explanation of symbols

2 P-type semiconductor substrate 4 N-type well region 6 Ion implantation resist pattern 8, 8a, 8b Boron ion 10 P-type low-concentration drain region 10c End region 12, 12a on the source region side of P-type low-concentration drain region Field oxide film 14 Gate oxide film 16 Gate electrode 18 High concentration drain region 20 High concentration source region 22 Channel region

Claims (11)

A second conductivity type high concentration source region and a high concentration drain region formed in a well region of the first conductivity type formed on the semiconductor substrate and spaced apart from each other, and between the high concentration source region and the high concentration drain region; A channel region formed adjacent to the high-concentration source region; a low-concentration drain region of a second conductivity type formed between the channel region and the high-concentration drain region; A gate insulating film formed over the source side end of the drain region, and a film thicker than the gate insulating film formed on the low concentration drain region between the gate insulating film and the high concentration drain region A high withstand voltage MOSFET having a field insulating film having a thickness and a gate electrode formed from the gate insulating film to the field insulating film is provided. ,
2. The semiconductor device according to claim 1, wherein the low concentration drain region has a concentration distribution of the second conductivity type impurity in a region under the gate insulating film, wherein the semiconductor substrate surface side is thin and the deep side is dark.   The semiconductor device according to claim 1, wherein the low concentration drain region covers the high concentration drain region.   3. The semiconductor device according to claim 1, wherein an end of the lightly doped drain region on the source side is formed at a distance from the gate insulating film.   The concentration distribution of the second conductivity type impurity in the depth direction in the region under the gate insulating film in the low concentration drain region has two peaks, and the impurity concentration at the peak position on the semiconductor substrate surface side is the peak position on the deep side. 4. The semiconductor device according to claim 1, wherein the semiconductor device has a lower impurity concentration.   At the lower end of the low concentration drain region, a region under the field insulating film is formed shallower than other regions, and impurities in the low concentration drain region near the field insulating film are taken into the field oxide film. The semiconductor device according to claim 1, wherein the semiconductor device is not provided. A method for manufacturing a semiconductor device for forming the semiconductor device according to claim 1, comprising the following steps (A) to (F).
(A) forming a first conductivity type well region in a semiconductor substrate;
(B) A second conductivity type impurity is implanted into a predetermined region of the well region by an ion implantation method, and a low concentration drain region having a second conductivity type impurity concentration distribution in which the semiconductor substrate surface side is thin and the deep side is dense. Forming step,
(C) forming a field insulating film in a predetermined region at least on the surface of the low-concentration drain region;
(D) forming a gate insulating film adjacent to the field oxide film at least on the surface of the well region;
(E) forming a gate electrode over the field insulating film from the gate insulating film;
(F) Impurity implantation is performed by ion implantation using the gate electrode and the field insulating film as a mask to form a high concentration source region in the well region and a high concentration in the low concentration drain region. Forming a concentration drain region;   In the step (B), the ion implantation is performed in the first ion implantation step for implanting the second conductivity type impurity and the second conductivity type under the condition that the acceleration energy is smaller and the implantation amount is smaller than those in the first ion implantation step. The method for manufacturing a semiconductor device according to claim 6, further comprising a second ion implantation step of implanting impurities.   7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step (B), the ion implantation is performed so that the implantation depth of the second conductivity type impurity is 0.2 [mu] m or more. A method of manufacturing a semiconductor device for forming a semiconductor device according to claim 1, comprising the following steps (A) to (F).
(A) forming a first conductivity type well region in a semiconductor substrate;
(B) forming a field insulating film at least in a predetermined region on the surface of the well region;
(C) Second conductivity type impurities are implanted into a predetermined region of the well region including the field insulating film formation region by ion implantation, so that the semiconductor substrate surface side is thin and the deep side is dark. Forming a low concentration drain region having a concentration distribution;
(D) forming a gate insulating film adjacent to the field oxide film at least on the surface of the well region;
(E) forming a gate electrode over the field insulating film from the gate insulating film;
(F) Impurity implantation is performed by ion implantation using the gate electrode and the field insulating film as a mask to form a high concentration source region in the well region and a high concentration in the low concentration drain region. Forming a concentration drain region;   In the step (C), the ion implantation is performed in the first ion implantation step for implanting a second conductivity type impurity and the second conductivity type under the condition that the acceleration energy is smaller and the implantation amount is smaller than those in the first ion implantation step. The method for manufacturing a semiconductor device according to claim 9, further comprising a second ion implantation step of implanting impurities.   10. The method of manufacturing a semiconductor device according to claim 9, wherein in the step (C), the ion implantation is performed so that the implantation depth of the second conductivity type impurity is 0.2 [mu] m or more.