JP2000068385A - Manufacture of mos transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of photo masks necessary for manufacturing a MOS transistor by forming an oxide film having an uneven thickness in an upper layer of a semiconductor substrate to form regions of different impurity densities with only one-time ion implantation by a difference in the thickness of the oxide film. SOLUTION: An oxide film INS having an uneven thickness is formed on the surface of a semiconductor substrate SUB. Ions are implanted into the substrate through the oxide film INS to form an ion implanted region of a high density on the surface of the semiconductor substrate SUB in a field region where the oxide film INS is thick, Meanwhile, in an active region where the oxide film INS is thin, the ion implanted region of a high density is formed deep in the semiconductor substrate SUB. As a result, the impurity density on the surface of the substrate in the active region is lower than that in the field region, thereby forming two types of ion implanted layers of different concentrations. Accordingly, the number of photo masks necessary for manufacturing a MOS transistor can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor, and more particularly to a high withstand voltage MOS transistor and a low withstand voltage M transistor.
The present invention relates to a method for manufacturing a MOS transistor suitable for a driver of a liquid crystal display device in which OS transistors are mixed or a flash memory.

[0002]

2. Description of the Related Art A MOS transistor for a driver or a flash memory of a liquid crystal display device is formed by mixing a high withstand voltage MOS transistor and a low withstand voltage MOS transistor. Conventionally, to form an impurity region by ion implantation in the manufacture of this type of MOS transistor, a resist is applied to a semiconductor substrate, an opening is formed by removing the resist only in a region where ions are to be implanted, and a resist is formed in other regions. Ion implantation is being performed.

FIG. 37 is a process chart for explaining an example of a conventional impurity region forming process. First, (a) an oxide film INS is formed on the semiconductor substrate SUB, (b) a photoresist REG is applied thereon, and a photomask PMSK is applied. Remove. (C) An ion ION is implanted through the oxide film INS through the opening from which the resist has been removed to form an ion-implanted layer having a low impurity concentration or an ion-implanted layer IONL / R having a high impurity concentration. Finally, (d) the remaining resist is removed.

As described above, conventionally, one impurity region is used for each impurity region.
One photomask is required, and two photomasks are required to form two regions having different impurity regions.

FIG. 38 is a process chart for explaining another example of a conventional process for forming an impurity region. In this process, first, (a) an oxide film INS is formed on the semiconductor substrate SUB.
Is formed, and ions are implanted into the entire surface to form (b) an ion-implanted layer IONL having a low impurity concentration.
(C) A resist REG is applied on the oxide film, and the resist in a region where ions are to be implanted is removed by exposure and development through a photomask PMSK having an opening in a region with a high impurity concentration. (D) ion ION is implanted through the oxide film INS through the opening from which the resist has been removed,
(E) A region IONR having a high impurity concentration is formed.

In this process, two types of impurity regions having different ion concentrations can be formed with one photomask. However, two ion implantation steps are required, and the first ion implantation requires the semiconductor substrate SUB. Ions are implanted over the entire surface.

FIGS. 34 and 35 are schematic process diagrams illustrating a manufacturing process of a driver of an active matrix type liquid crystal panel having a high breakdown voltage MOS transistor.
B is a semiconductor substrate, HNW is a well of a high breakdown voltage PMOS transistor, HPW is a well of a high breakdown voltage NMOS transistor, NW is a well of a low breakdown voltage PMOS transistor, and PW is a well of a low breakdown voltage NMOS transistor.
F is a channel stopper in a field region of the well HNW of the high breakdown voltage PMOS transistor and the well NW of the low breakdown voltage PMOS transistor, and NP is a high breakdown voltage NMO.
Well HPW of S transistor and low breakdown voltage NMOS
A channel stopper in a field region of a transistor well PW, FR is a field region covered with a thick oxide film, HPM is an electric field relaxation layer in a drain / source portion of a high breakdown voltage PMOS transistor, and HNM is a drain / source of a high breakdown voltage NMOS transistor. Part of electric field relaxation layer, PP
G and PNG indicate the gate electrodes of the high voltage MOS transistors, and LPG and LNG indicate the gate electrodes of the low voltage MOS transistors.

This process will be described with reference to FIGS. 39 and 40. First, (a) wells HNW and HPW of high-voltage MOS transistors are formed on a semiconductor substrate SUB with one photomask. Then, (b) low withstand voltage system M
Wells NW and PW of the OS transistor are formed using respective photomasks. In this step, the photomask is 2
Use one.

Next, (c) a field region and channel stoppers NF and PF are formed. In this step, 3
One photomask is used.

(D) After forming the electric field relaxation layers HNM and HPM of the high breakdown voltage type MOS transistor using respective photomasks, (e) forming the gate electrodes PPG and PN.
G, LPG, and LNG are formed to form a high breakdown voltage PMOS transistor, a high breakdown voltage NMOS transistor, and a low breakdown voltage P
A MOS transistor and a low breakdown voltage NMOS transistor are obtained.

The photomasks used in all of the above processes require three photomasks only for forming wells, two photomasks for forming a channel stopper, and two photomasks for forming an electric field relaxation layer at the drain and source portions of a high breakdown voltage MOS transistor. A total of eight photomasks are required including those for forming the field region.

In the conventional process described with reference to FIG. 38, ion implantation is required for each different impurity concentration.

[0013]

As described above, when impurity regions having different ion concentrations are formed, a photomask is required for each of the conventional impurity region formation processes, and ion implantation is performed at different impurity concentrations. The number of times corresponding to the number of regions was required.

That is, when a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor coexist, the well of the high-breakdown-voltage MOS transistor has an impurity concentration due to a short channel effect between the drain and the source of the high-breakdown-voltage MOS transistor. It is necessary to increase the impurity concentration of the well of the low-voltage withstand voltage MOS transistor. For this reason, in the above-mentioned conventional manufacturing process, ion implantation is performed a plurality of times using a large number of expensive photomasks.

An object of the present invention is to solve the above-mentioned problems of the prior art, reduce the number of photomasks required for manufacturing a MOS transistor, and reduce the number of ion implantations to reduce the number of manufacturing steps, thereby reducing cost. An object of the present invention is to provide a method for manufacturing a MOS transistor.

[0016]

In order to achieve the above object, the present invention controls the ion implantation depth by utilizing the difference in the thickness of an oxide film to form a plurality of types of ion implantation layers having different concentrations. It is characterized in that it is made as described above.

FIG. 1 is a schematic diagram for explaining the principle of ion implantation in the method of manufacturing a MOS transistor according to the present invention. In the present invention, oxide films having different thicknesses are formed on the surface of the semiconductor substrate SUB. The thickness of the oxide film INS is increased in the field region and is reduced in the active region.

When ion implantation is performed so as to pass through the oxide film INS, a high-concentration ion implantation layer is formed on the surface of the semiconductor substrate SUB in the field region where the oxide film is thick, and in the active region where the oxide film INS is thin. An ion-implanted layer is formed in a deep portion of the substrate SUB.

As a result, the impurity concentration on the surface is lower than that in the field region, and two types of ion-implanted layers having different concentrations can be formed.

Examples of typical constitutions of the present invention are described in the following (1) and (2).

(1) M including a step of forming well regions having different impurity concentrations in a semiconductor substrate by ion implantation.
In the method for manufacturing an OS transistor, an oxide film having a different thickness is coated on the upper layer of the semiconductor substrate, and regions having different impurity concentrations are formed by a single ion implantation due to the difference in the thickness of the oxide film.

(2) A high-voltage MOS transistor used at a high voltage and a low-voltage MOS transistor used at a low voltage are mixed on the same semiconductor substrate due to a difference in operating voltage.
In a method of manufacturing a MOS transistor in which well regions having different impurity concentrations are formed due to a difference in operating voltage, a field oxide for forming a well of a high breakdown voltage MOS transistor having a low impurity concentration first and then electrically isolating the MOS transistors from each other is formed. By forming a film and then forming a well of a low breakdown voltage MOS transistor having a high impurity concentration, an electric field relaxation layer and a parasitic MOS transistor of a drain / source portion of the high breakdown voltage MOS transistor are formed in the well ion implantation step of the low breakdown voltage MOS transistor. And a channel stopper for the same is formed at the same time.

It should be noted that the present invention is not limited to the above configuration, and does not depart from the technical idea of the present invention.
Various changes can be made without being limited to the following embodiments.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the illustrated embodiments.

FIGS. 2 and 3 are process diagrams schematically showing one embodiment of the method for manufacturing a MOS transistor according to the present invention. In FIG. 2, the same reference numerals as those in FIGS. 34 and 35 correspond to the same parts.

First, (a) a well HN of a high breakdown voltage MOS transistor is formed on a semiconductor substrate SUB using one photomask.
W, HPW are formed. (B) The field region FR is formed of a thick oxide film on the boundary between the wells HNW and HPW of the high breakdown voltage MOS transistor. One photomask is used to form this field region.

Next, (c) the well NW of the low-breakdown-voltage MOS transistor is set (channel stopper and electric field relaxation layer).
Is formed with two photomasks ((c-1), (c-
2)). The following goes to the gate electrode forming step.

As described above, in the present invention, the field region is formed after the well of the high breakdown voltage MOS transistor is formed by changing the order of the conventional manufacturing process, and then the low breakdown voltage well is formed. In this ion implantation for forming a well, ions are implanted by utilizing a difference in thickness of an oxide film between a field region and an active region. Therefore, a photomask for a low breakdown voltage well is used as a substitute for a channel stopper and a photomask for an electric field relaxation layer. Therefore, the same structure as that of the related art can be formed by using four photomasks, and the number of photomasks (channel stoppers and electric field relaxation layers in the N region and the P region, respectively) can be eliminated.

FIGS. 4, 5, 6, and 7 are process diagrams for explaining an embodiment in which the present invention is applied to a manufacturing process of a liquid crystal panel driver. This step includes a well formation process (a) of a high breakdown voltage MOS transistor, a field region formation process (b), a well formation process (c) of a low breakdown voltage MOS transistor, and a gate electrode formation process (d). .

First, in (a) the well forming process of the high breakdown voltage MOS transistor, (a-1) the semiconductor substrate SU
On the surface of B, a through oxide film INS and a nitride film SIN for ion implantation are formed. By applying and patterning the resist film REG, an opening is formed by removing SIN in a region to be the well HNW of the PMOS transistor, and ions are implanted into the region through the opening. And (a-
2) After ion implantation, the resist film REG is removed and thermal oxidation is performed. Since the region where the nitride film SIN is present is not oxidized during this thermal oxidation, if the nitride film SIN is removed after the thermal oxidation, the oxide film in the region where the nitride film SIN was present remains thin, and thus the well of the PMOS transistor is removed. H
Thick oxide film INS (TINS) in the NW region and thin oxide film INS (S) in the well HPW region of the NMOS transistor
INS). Using this thick oxide film INS (thermal oxide film TINS) as a substitute for a resist film, ion implantation is performed in the well HPW region of the NMOS transistor.

Next, in the (b) field region forming process, (b-1) the well region is extended by thermal diffusion for a long time, and the thermal oxide film TINS and the nitride film are again formed on the surface of the semiconductor substrate SUB. After forming the film SIN and forming a resist film (not shown), the nitride film is etched using a photomask for forming a field region. (B-2) When thermal oxidation is performed after the nitride film is etched, a thick field oxide film FINS is formed in a region where the nitride film SIN does not exist.

(C) In the formation of the well of the low-breakdown-voltage MOS transistor, (c-1) In the formation of the well NW of the low-breakdown-voltage PMOS transistor, a resist film is applied and patterned using a photomask to form the low-breakdown-voltage PMOS transistor. An opening is formed in the well region. By performing ion implantation through the opening of the resist film, the low withstand voltage P
High breakdown voltage P together with well region NW of MOS transistor
It is formed as a channel stopper NW (CS) in a well HNW region of a MOS transistor and an electric field relaxation region NW (FD) of a high breakdown voltage NMOS transistor.

Since the ion implantation utilizes the difference in the thickness of the oxide film, ions are implanted with the channel stopper NW (CS) having a high concentration and the well region NW and the electric field relaxation region FD having a low concentration.

Similarly, (c-2) low breakdown voltage NMOS
In the formation of the well PW of the transistor, an opening is formed in the well PW region of the low-breakdown-voltage NMOS transistor by patterning the resist film in the same manner as described above, and then ion implantation is performed to form the well PW of the low-breakdown-voltage NMOS transistor together with the high breakdown voltage. A channel stopper PW (FD) of the well region HPW of the system NMOS transistor is formed. After that, (c-3) the low-voltage MOS by thermal diffusion
The well of the transistor and the electric field relaxation layer of the high breakdown voltage MOS transistor are extended.

Thereafter, the process proceeds to (d) the gate electrode forming process, and the gate electrode PP of the high-voltage MOS transistor is formed.
A driver (IC) suitable for a liquid crystal panel is obtained by forming G, PNG, and gate electrodes LPG, LNG of a low breakdown voltage MOS transistor.

In the application of the present invention, in the above process flow, a well of a high voltage MOS transistor is formed first, and then a field oxide film for electrically isolating MOS transistors is formed. As shown in FIG. 9, first, a field oxide film is formed using one mask, and then high-voltage well ion implantation is performed at a high energy such as to pass through a thick oxide film for a long time. The present invention can also be applied to a process flow in which an electric field relaxation layer and a channel stopper of a high breakdown voltage MOS transistor are simultaneously formed by ion implantation for forming a low breakdown voltage well after the well is extended by thermal diffusion.

The high voltage MOS transistor is not limited to the planar type MOS transistor shown in FIG.
The present invention can also be applied to the manufacture of the LOCOS offset type MOS transistor shown in FIG. 11, and the MOS transistor structure in this case is as shown in FIG.

As described in the above embodiment, according to the manufacturing method employing the process according to the present invention, four photomasks can be reduced and the number of times of ion implantation can be reduced as compared with the conventional process.

Next, an active matrix type color liquid crystal display device to which a driver employing a MOS transistor manufactured according to the present invention is applied will be described.

FIG. 13 is a plan view illustrating a configuration of one pixel of an active matrix type liquid crystal display device to which the present invention is applied and the periphery thereof, FIG. 14 is a cross-sectional view taken along line 3-3 in FIG. FIG. 15 is a cross-sectional view taken along line 4-4 in FIG. 13, and FIG. 16 is a plan view showing a state where a plurality of pixels shown in FIG. 13 are arranged.

As shown in FIG. 13, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) G
L and two adjacent video signal lines (drain signal lines or vertical signal lines) DL are arranged in an intersecting region (in a region surrounded by four signal lines).

Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1, and a storage capacitor Cadd. The scanning signal lines GL extend in the column direction, and a plurality of the scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction and are arranged in a plurality in the column direction.

As shown in FIG. 14, a thin film transistor T is provided on the lower transparent glass substrate SUB1 side with respect to the liquid crystal LC.
An FT and a transparent pixel electrode ITO1 are formed, and a color filter FIL and a light blocking black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side. The upper and lower transparent glass substrates SUB2,1 are, for example, 1.
It has a thickness of about 1 mm, and a silicon oxide film SIO is formed on each of both surfaces thereof by dipping or the like. For this reason, even if the surface of the transparent glass substrates SUB1 and SUB2 has fine scratches, the surface is flattened by the coating of the silicon oxide film SIO and the scanning signal lines G formed thereon are formed.
L, the film quality of the light shielding film (black matrix) BM and the like can be kept uniform.

A light shielding film BM and a color filter FI are provided on the inner surface (the liquid crystal LC side) of the upper transparent glass substrate SUB2.
L and an upper alignment film ORI2 are sequentially laminated.

<< Outline of Matrix Peripheral >> FIG. 17 shows a liquid crystal panel P including upper and lower transparent glass substrates SUB2 and SUB1.
FIG. 18 is a plan view of a main portion around the matrix AR of the NL, and FIG.
7 is a plan view showing the periphery of the matrix AR shown in FIG. 7 in a more exaggerated manner, and FIG. 19 is an enlarged plan view showing the vicinity of the seal portion SL corresponding to the upper left corner of the liquid crystal panel shown in FIGS. 20 is a cross-sectional view taken along line 19a-19a in FIG. 19 on the left side with the cross-section in FIG. 14 as the center, and a cross-sectional view near the external connection terminal DTM to which the video signal line driving circuit is to be connected on the right side. FIG. 21 is a cross-sectional view near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross-sectional view near the seal portion where there is no external connection terminal on the right side.

In the manufacture of this liquid crystal panel, if the size is small, a plurality of pieces are simultaneously processed on one glass substrate and then separated to improve the throughput. A glass substrate of a standardized size is processed even in a variety to reduce the size to a size suitable for each type, and in any case, the glass substrate is cut after passing through one process.

FIGS. 17 to 19 show examples of the latter.
Both FIGS. 17 and 18 show the upper and lower glass substrates SUB.
2, after cutting SUB1, FIG. 19 shows the state before cutting, and LN indicates the edges of the cutting line of the glass substrate by CT1 and CT2.
Indicates the positions of the glass substrates SUB1 and SUB2 to be cut, respectively.

In any case, in the completed state, the portions (the upper and lower sides and the left side in the figure) where the external connection terminal groups Tg and Td (subscripts are omitted) have a size of the upper glass substrate SUB2 such that they are exposed. It is limited inside the lower glass substrate SUB1.

The external connection terminal groups Tg and Td respectively include a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM and their lead-out wiring portions which are described later.
Tape carrier package TCP on which is mounted (Fig. 2
2, see FIG. 23). The lead wiring from the matrix part of each group to the external connection terminal part is inclined as approaching both ends. This is because the terminals DTM and GTM of the liquid crystal panel PNL correspond to the arrangement pitch of the tape carrier package TCP and the connection terminal pitch of each tape carrier package TCP.
It is in order to match.

A liquid crystal LC is provided between the transparent glass substrates SUB1 and SUB2 except for the liquid crystal filling opening INJ along the edge thereof.
Is formed so as to seal the sealing pattern SL (hereinafter, also referred to as a sealing material). The material of this seal pattern is made of, for example, epoxy resin. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the lead-out wiring INT formed on the lower transparent glass substrate SUB1 side by a silver paste material AGP at four corners of the liquid crystal panel at this point. This lead-out wiring INT has a gate terminal GTM and a drain terminal D which will be described later.
It is formed in the same manufacturing process as TM.

The layers of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO1, and the common transparent pixel electrode ITO2 are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are each a lower transparent glass substrate SUB
1. Formed on the outer surface of the upper transparent glass substrate SUB2.

The liquid crystal LC is sealed in a region partitioned by the seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 for setting the direction of the liquid crystal molecules. The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the upper transparent glass substrate SUB2 side.
1 and the upper transparent glass substrate SUB2 are superimposed, and liquid crystal is injected from the opening INJ (injection port) of the sealing material SL.
The inlet INJ is sealed with an epoxy resin or the like, and is assembled by cutting the upper and lower transparent glass substrates.

<< Thin Film Transistor TFT >> The thin film transistor TFT operates so that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is made zero, the channel resistance increases.

The thin film transistor TFT of each pixel is divided into two (a plurality) in the pixel, and is constituted by thin film transistors (divided thin film transistors) TFT1 and TFT2. Thin film transistor TFT1 and TFT
Each of the two has substantially the same size (channel length and channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 is
Gate electrode GT, gate insulating film GI, i-type (intrinsic, in
(Trinsic, not doped with conductivity type determining impurities) i-type semiconductor layer A made of amorphous silicon (Si)
S, a pair of a source electrode SD1 and a drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, and therefore, it should be understood that the source and the drain are switched during the operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.

<< Gate Electrode GT >> The gate electrode GT is shown in FIG.
5 is a shape projecting in the vertical direction (upward in FIGS. 13 and 24) from the scanning signal line GL, as shown in FIG. 14 (a plan view depicting only the second conductive film g2 and the i-type semiconductor layer AS). (Branched into a T-shape).

The gate electrode GT is a thin film transistor TFT
1, and project beyond the respective active areas of the TFT2. The respective gate electrodes GT of the thin film transistors TFT1 and TFT2 are formed continuously. Here, the gate electrode GT is formed of a single-layer second conductive film g2. As the second conductive film g2, for example, an aluminum (Al) film formed by sputtering is used, and 1000 to 55 is used.
It is formed with a thickness of about 00 °. Further, an anodic oxide film AOF of aluminum is provided on the gate electrode GT.

As shown in FIGS. 13, 14 and 26, the gate electrode GT is formed larger than that so as to completely cover the i-type semiconductor layer AS (as viewed from below). Therefore, when a backlight BL such as a fluorescent tube is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of this opaque aluminum film becomes a shadow, and light from the backlight is applied to the i-type semiconductor layer AS. Therefore, the conductive phenomenon due to the light irradiation, that is, the deterioration of the off characteristic of the thin film transistor TFT is less likely to occur. Note that the original size of the gate electrode GT is the minimum necessary for straddling between the source electrode SD1 and the drain electrode SD2 (the alignment margin between the gate electrode GT, the source electrode SD1, and the drain electrode SD2). And a depth W that determines the channel width W is the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, a factor W / L that determines the transconductance gm. Is determined by how many. The size of the gate electrode GT in this liquid crystal display device is, of course, made larger than the original size described above.

<< Scanning Signal Line GL >> The scanning signal line GL is
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is formed integrally. Further, an anodic oxide film AOF of aluminum Al is provided also on the scanning signal line GL.

<< Insulating Film GI >> The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 and TFT2. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. The insulating film GI is formed using a silicon nitride film formed by, for example, plasma CVD and having a thickness of 1200 to 2700 ° (about 2000 ° in this liquid crystal display device). As shown in FIG. 19, the gate insulating film GI is formed so as to surround the entire matrix part AR, and the peripheral part is formed with external connection terminals DTM,
It has been removed to expose the GTM.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
Are used as channel forming regions of the thin-film transistors TFT1 and TFT2 divided into a plurality of portions as shown in FIG. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film.
It is formed with a thickness of 0 ° (about 200 ° in this liquid crystal display device).

The i-type semiconductor layer AS is formed by changing the composition of the supply gas and forming the insulating film GI used as the gate insulating film made of Si ₂ N ₄ by the same plasma CVD.
It is formed by an apparatus and without being exposed to the outside from the plasma CVD apparatus.

An N (+) type semiconductor layer d0 doped with 2.5% of phosphorus (P) for ohmic contact is used.
14 (FIG. 14) is similarly formed continuously with a film thickness of 200 to 500 ° (about 300 ° in this liquid crystal display device). Then, the lower transparent glass substrate SUB1 is CVD
It is taken out of the device and N
The (+) type semiconductor layer d0 and the i type semiconductor layer AS are shown in FIG.
3, and patterned into independent islands as shown in FIGS.

FIGS. 13 and 24 show the i-type semiconductor layer AS.
As shown in (1), it is also provided between both intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Transparent Pixel Electrode ITO1 >> Transparent Pixel Electrode I
TO1 forms one of the pixel electrodes of the liquid crystal panel. The transparent pixel electrode ITO1 is connected to both the source electrode SD1 of the thin film transistor TFT2 and the source electrode SD1 of the thin film transistor TFT2. For this reason, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by a laser beam or the like, and if not, the other thin film transistor operates normally. You can leave it. The two thin film transistors TFT1, TFT1
It is seldom that defects occur simultaneously in the image data 2 and the probability of occurrence of point defects and line defects can be extremely reduced by such a redundant system.

The transparent pixel electrode ITO1 is composed of the first conductive film d1. This first conductive film d1 is a transparent conductive film (Indium-Tin) formed by sputtering.
-Oxide ITO: Nesa film)
2000 膜厚 film thickness (1400 で は in this liquid crystal display device)
).

<< Source electrode SD1, Drain electrode SD
2 >> Thin-film transistors TFT1, TF divided into a plurality
Source electrode SD1 and drain electrode SD of T2
13 is the same as FIG. 13, FIG. 14 and FIG.
As shown in a plan view depicting only the third conductive films d1 to d3), they are separately provided on the i-type semiconductor layer AS.

Each of the source electrode SD1 and the drain electrode SD2 is formed by sequentially stacking a second conductive film d2 and a third conductive film d3 from the lower side in contact with the N (+) type semiconductor layer d0. Second conductive film d of source electrode SD1
The second and third conductive films d3 are the second conductive films d3.
The conductive film d2 and the third conductive film d3 are formed in the same manufacturing process.

The second conductive film d2 is formed using a chromium (Cr) film formed by sputtering and having a thickness of 500 to 1000 Å (about 600 膜厚 in this liquid crystal display device). The Cr film is aluminum A of a third conductive film d3 described later.
A so-called barrier layer for preventing l from diffusing into the N (+) type semiconductor layer d0 is formed. Cr as the second conductive film d2
In addition to the film, a film of a high melting point metal (Mo, Ti, Ta, W, etc.), a high melting point metal silicide (MoSi ₂ , TiSi ₂ ,
TaSi ₂ , WSi _2, etc.) can also be used.

The third conductive film d3 is formed by sputtering aluminum Al to a thickness of 3000 to 5000 ° (about 4000 ° in this liquid crystal display). The aluminum Al film has a smaller stress than the chromium Cr film and can be formed in a thick film.
It is configured to reduce the resistance values of D1, the drain electrode SD2, and the video signal line DL. As the third conductive film d3, an aluminum film containing silicon or copper (Cu) as an additive in addition to normal aluminum can be used.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, using the same mask or using the second conductive film d2 and the third conductive film d3 as a mask, an N (+) type The semiconductor layer d0 is removed. That is, in the N (+)-type semiconductor layer d0 remaining on the i-type semiconductor layer AS, portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, since the N (+)-type semiconductor layer d0 is etched so as to remove all of its thickness, the i-type semiconductor layer AS is also slightly etched at its surface. What is necessary is just to control by processing time.

The source electrode SD1 is a transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 is formed by a step of the i-type semiconductor layer AS (the thickness of the second conductive film d2, the anodic oxide film AOF).
, The thickness of the i-type semiconductor layer AS, and the thickness of the N (+)-type semiconductor layer d0). Specifically, the source electrode SD1 is i
Conductive film d formed along the step of the semiconductor layer AS
2 and a third conductive film d3 formed on the second conductive film d2. Since the third conductive film d3 of the source electrode SD1 cannot increase the thickness of the Cr film of the second conductive film d2 due to an increase in stress and cannot climb over the step of the i-type semiconductor layer AS, the third conductive film d3 needs to get over the i-type semiconductor layer AS. It is configured. That is, the step coverage is improved by increasing the thickness of the third conductive film d3. Third conductive film d3
Can be formed thick, which greatly contributes to a reduction in the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).

<< Protective Film PSV1 >> Thin Film Transistor TF
A protective film PSV1 is provided on T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture, and a film having high transparency and good moisture resistance is used. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD device, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

As shown in FIG. 19, the protective film PSV1 is formed so as to surround the entire matrix portion AR, the peripheral portion is removed so as to expose the external connection terminals DTM and GTM, and the upper transparent glass substrate Common electrode C of SUB2
The portion connecting the OM to the external connection terminal connection lead-out wiring INT of the lower transparent glass substrate SUB1 with the silver paste AGP is also removed. Regarding the thickness relationship between the protective film PSV1 and the gate insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner in consideration of the transconductance gm of the transistor. Therefore, as shown in FIG. 14, the protection film PSV1 having a high protection effect is formed larger than the gate insulating film GI so as to protect the peripheral portion as much as possible.

<< Light-shielding film BM >> Upper transparent glass substrate SUB
On the second side, a light-shielding film BM is provided so that external light (light from above in FIG. 14) does not enter the i-type semiconductor layer AS used as a channel formation region. The light-shielding film BM has a pattern shown by hatching in FIG. FIG. 26 shows the first conductive film d1, the color filter FIL, and the light shielding film BM shown in FIG.
It is the top view which drew only.

The light-shielding film BM has a high light-shielding property against light,
For example, it is formed of an aluminum film, a chromium film, or the like. In this liquid crystal display device, the chromium film is formed by sputtering at 130
It is formed to a thickness of about 0 °.

Therefore, the thin film transistors TFT1, TFT1
The i-type semiconductor layer AS of the TFT 2 is sandwiched by the upper and lower light shielding films BM and the large gate electrode GT, and the portion is not exposed to external natural light or backlight light. As shown by hatching in FIG. 21, the light-shielding film BM is formed around the pixels, that is, the light-shielding film BM is formed in a lattice shape (a so-called black matrix), and the effective display area of one pixel is partitioned by the lattice. ing. With the light-shielding film BM, the outline of each pixel is clear, and the contrast is improved. That is, the light shielding film BM is formed of the i-type semiconductor layer AS.
And a black matrix.

Further, the portion (lower right portion in FIG. 13) of the transparent pixel electrode ITO1 facing the edge on the root side in the rubbing direction is shielded from light by the light shielding film BM. Since the domain is not visible, the display characteristics do not deteriorate.

The backlight can be attached to the upper transparent glass substrate SUB2, and the lower transparent glass substrate SUB1 can be used as the observation side (exposed side).

The light-shielding film BM is also formed in a peripheral portion in a frame-shaped pattern as shown in FIG. 19, and the pattern is continuous with the pattern of the matrix portion shown in FIG. It is formed. The light-shielding film BM in the peripheral portion is extended outside the seal portion SL as shown in FIGS. 18 to 21 to prevent leakage light such as reflected light due to a mounting device such as a personal computer from entering the matrix portion. I have. On the other hand, the light shielding film BM is formed on the upper transparent glass substrate SUB.
About 0.3-1.0mm inside from the edge of 2,
It is formed avoiding the cutting area of the upper transparent glass substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed by coloring a dye on a dyed base material formed of a resin material such as an acrylic resin. Color filter F
IL is formed in a stripe shape at a position facing the pixel (FIG. 27) and is dyed separately (FIG. 27 shows the first conductive film d1, the light shielding film BM, and the color filter FIL in FIG. 16).
Only R, G, B color filters F
ILs are hatched at 45 ° and 135 ° crosses, respectively. As shown in FIGS. 26 and 27, the color filter FIL is formed to be large so as to cover the entirety of the transparent pixel electrode ITO1, and the light shielding film BM is formed of the color filter FI.
It is formed inside the periphery of the transparent pixel electrode ITO1 so as to overlap with the edge portion of the transparent pixel electrode ITO1.

The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, by performing similar steps, a green filter G and a blue filter B are sequentially formed.

<< Protective Film PSV2 >> The protective film PSV2 is composed of a liquid crystal L made of a dye obtained by dyeing the color filter FIL into different colors.
It is provided to prevent leakage to C. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin.

<< Common Transparent Pixel Electrode ITO2 >> The common transparent pixel electrode ITO2 is opposed to the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is determined by each pixel electrode ITO1. In response to a potential difference (electric field) between the pixel electrode and the common transparent pixel electrode ITO2. A common voltage V is applied to the common transparent pixel electrode ITO2.
com is applied. In this,
The common voltage Vcom includes a low-level driving voltage Vdmin and a high-level driving voltage Vd applied to the video signal line DL.
Although it is set to an intermediate potential with respect to dmax, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal driving circuit to about half, an AC voltage may be applied. The plan shape of the common transparent pixel electrode ITO2 should be referred to FIGS.

<< Gate Terminal >> FIG. 28 shows a state in which the scanning signal lines GL of the liquid crystal pattern display matrix are connected to the external connection terminals G.
It is explanatory drawing of the connection structure to TM, (A) is a top view,
(B) is a sectional view taken along line BB of (A). This figure corresponds to the vicinity of the lower part of FIG. 19, and the portion of the oblique wiring is represented by a straight line for convenience.

AO is a mask pattern for photo processing, in other words, a photoresist pattern of selective anodic oxidation. Therefore, this photoresist is removed after anodic oxidation, and the pattern AO shown in the figure does not remain as a finished product, but an oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view of FIG. So that the trajectory remains. In the plan view of (A), the boundary line A of the photoresist is shown.
With reference to O, the left side is a region covered with the resist and not subjected to anodization, and the right side is a region exposed from the resist and anodized. The oxide AAl ₂ O ₃ film AOF is formed on the surface of the anodized aluminum Al layer g2, and the volume of the lower conductive portion is reduced. Of course, anodic oxidation is performed by setting an appropriate time, voltage and the like so that the conductive portion remains. The mask pattern AO does not intersect the scanning signal line GL with a single straight line, but intersects by bending in a crank shape.

In the figure, the aluminum Al layer g2 is hatched for easy understanding, but the region that is not anodized is patterned in a comb shape. this is,
If the width of the aluminum Al layer is large, whiskers are generated on the surface. Therefore, the width of each one is narrowed, and by arranging a plurality of them in parallel, the occurrence of whiskers is prevented while preventing the occurrence of disconnections. The goal is to minimize sacrifices in probability and conductivity. Therefore, here, the portion corresponding to the root of the comb is also shifted along the mask AO.

The gate terminal GTM has good adhesion to the silicon oxide SIO layer, and has a chromium Cr layer g1 having higher corrosion resistance than aluminum Al.
Transparent conductive layer d1 at the same level (same layer, simultaneous formation) as TO1
It is composed of The conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof are formed so that the conductive layers g2 and g1 are not etched together due to a pinhole or the like at the time of etching the conductive layers d2 and d3. This remains as a result of covering the area with photoresist. In addition, the ITO layer d1 extending rightward beyond the gate insulating film GI is a thorough countermeasure.

In the plan view of FIG. 28A, the gate insulating film GI has a protective film PSV1 on the right side of the boundary line.
Are formed on the right side of the boundary line, and the terminal portion GTM located on the left side is exposed therefrom so as to be able to make electrical contact with an external circuit. Although only one pair of the gate line GL and the gate terminal is shown in FIG. 12, a plurality of such pairs are actually arranged vertically as shown in FIG. 14) is constituted,
The left side of the gate terminal is a cutting area CT of the substrate during the manufacturing process.
1 and is short-circuited by the wiring SHg.
Such a short-circuit line SHg in the manufacturing process has an effect of supplying power during anodization (at the time of anodizing treatment) and preventing electrostatic breakdown generated at the time of rubbing of the alignment film ORI1 or the like.

<< Drain Terminal DTM >> FIGS. 29A and 29B are explanatory diagrams of the connection from the video signal line DL to its external connection terminal DTM, where FIG. 29A is a plan view and FIG. 29B is a BB line of FIG. FIG. 29 corresponds to the vicinity of the upper right of FIG. 19, and the direction of the drawing is changed for convenience, but the right end direction is the upper end (or lower end) of the lower transparent glass substrate SUB1.
Corresponds to.

TSTd is an inspection terminal to which no external circuit is connected, but is wider than the wiring portion so that a probe needle or the like can be contacted. Similarly, the width of the drain terminal DTM is wider than that of the wiring portion so as to enable connection with an external circuit. A plurality of test terminals TSTd and external connection terminals DTM are alternately arranged in a staggered manner in the vertical direction, and the test terminals TSTd are connected to the lower transparent glass substrate S as shown in the figure.
Although the terminal ends without reaching the end of UB1, the drain terminal DTM forms a terminal group Td (subscript omitted) as shown in FIG. 14 and crosses the cutting line CT1 of the lower transparent glass substrate SUB1. All of them are further extended, and all of them are short-circuited to each other by the wiring SHd in order to prevent electrostatic destruction during the manufacturing process. The drain connection terminal is connected to the opposite side of the matrix of the video signal line DL where the inspection terminal TSTd exists, and the video signal line DL where the drain terminal DTM exists
An inspection terminal is connected to the opposite side of the matrix.

The drain terminal DTM is formed of two layers of the chromium Cr layer g1 and the ITO layer d1 for the same reason as the gate terminal GTM described above, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. ing. The semiconductor layer AS formed on the edge of the gate insulating film GI is for etching the edge of the gate insulating film GI into a video signal in a tapered shape. On the drain terminal DTM, of course, the protective film PSV1 is removed for connection with an external circuit. AO is the anodic oxidation mask described above, and the left side from the boundary line is covered with the mask. However, since the layer g2 does not exist in the portion not covered in this figure, this pattern is not directly related.

As shown in FIG. 20C, the lead-out wiring from the matrix portion to the drain terminal DTM portion has the video signal line DL immediately above the layers d1 and g1 at the same level as the drain terminal DTM portion. Although the layers d2 and d3 of the same level are stacked halfway through the seal pattern SL, this is to minimize the probability of disconnection and to replace the aluminum Al layer d3 which is easily corroded with the protective film PSV1 and the seal pattern SL. The aim is to protect as much as possible with SL.

<< Structure of Storage Capacitor Cadd >> The transparent pixel electrode ITO1 is formed so as to overlap with the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. This superposition is shown in FIG.
3. As is clear from FIG. 17, the transparent pixel electrode ITO
1 is one electrode PL2, and the adjacent scanning signal line GL is the other electrode PL1.
Configure add. The dielectric film of the storage capacitor Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As is apparent from FIG. 24, the storage capacitance element Cadd is formed in a portion of the scanning signal line GL where the width of the second conductive film g2 is increased. The portion of the second conductive film g2 that intersects with the video signal line DL is thinned to reduce the probability of the video signal line DL and its short circuit.

In the step portion of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d3 are formed so as to straddle the step even if the transparent pixel electrode ITO1 is disconnected. The fault is compensated by the island region.

<< Equivalent Circuit of Entire Display Device >> FIG. 30 is a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
This figure is a circuit diagram, but is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X represents a video signal line DL, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively. Y means the scanning signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The video signal line X (subscript omitted) is connected to the upper video signal drive circuit He. That is, similarly to the scanning signal line Y, the video signal line X is connected to the video signal panel PNL.
The terminal is drawn out only on one side. Scan signal line Y
(The suffix is omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device which divides information for a CRT (cathode ray tube) from a power supply circuit for obtaining a stabilized voltage source by dividing a voltage source into a plurality of voltage sources and a host (upper processing unit). This is a circuit that includes a circuit that exchanges information for use.

<< Equivalent Circuit of Storage Capacitor Cadd and Its Operation >> FIG. 31 is an equivalent circuit diagram of the pixel shown in FIG. In FIG. 31, Cgs is a thin film transistor TFT
Is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1. The dielectric film of the parasitic capacitance element Cgs is the insulating film GI and the anodic oxide film AOF. Cpix is the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode IT
This is a liquid crystal capacitance formed between O2 (COM). The dielectric film of the liquid crystal capacitor Cpix is a liquid crystal LC, a protective film PSV1.
And the orientation films ORI1 and ORI2. V1c is a midpoint potential.

The capacitance of the storage capacitor Cadd (the storage capacitor Cadd)
add) works to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) V1c when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔV1c = ｛Cgs / (Cgs + Cadd)
+ Cpix)｝ × ΔVg Here, ΔV1c represents a change in the midpoint potential due to ΔVg. The change ΔV1c causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance Cadd is increased. In addition, the storage capacitance element Cadd also has a function of prolonging the discharge time, and stores video information after the thin film transistor TFT is turned off for a long time. The reduction of the DC component applied to the liquid crystal LC
, The so-called image sticking, in which the previous image remains when the liquid crystal display screen is switched, can be reduced.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the area of overlap with the source electrode SD1 and the drain electrode SD2 increases, so that the parasitic capacitance Cgs increases. , The midpoint potential V1c is easily affected by the gate (scanning) signal Vg. However, the storage capacitor Ca
By providing dd, this disadvantage can be eliminated.

The storage capacitor Cadd of the storage capacitor Cadd
Is 4 to the liquid crystal capacitance Cpix from the writing characteristics of the pixel.
８8 times (4 · Cpix <Cadd <8 · Cpix), and 8 to 32 times (8 · Cgs <Cad) with respect to the parasitic capacitance Cgs.
d <32 · Cgs).

<< Connection Method of Storage Capacitor Cadd Electrode Line >> The first-stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is, as shown in FIG. 30, a common transparent pixel electrode ITO2 (Vcom). ) To the same potential. FIG.
In the example shown in FIG. 9, the first-stage scanning signal line is short-circuited to the common electrode COM through the terminal GTO, the lead line INT, the terminal DT0, and the external wiring. Alternatively, the first-stage storage capacitor electrode line Y ₀ is connected to the last-stage scanning signal line Yend, connected to a DC potential point (AC ground point) other than Vcom, or one extra scanning pulse Y from the vertical scanning circuit V. _It may be connected to receive ₀ .

<< Connection Structure with External Circuit >> As shown in FIG. 22, in the tape carrier package TCP, the integrated circuit chip CHI constituting the scanning signal driving circuit V and the video signal driving circuits He and Ho is connected to a flexible wiring board ( Commonly known as TA
B; Tape, Automated Bonding)
FIG. 20 shows a state where this is connected to the video signal circuit terminal DTM of the video signal panel PNL. An integrated circuit for driving a liquid crystal panel (liquid crystal driver) constituting the video signal driving circuit He and the vertical scanning circuit V is an MO manufactured by the manufacturing method of the present invention described above.
An S transistor is used.

TB is an input terminal / wiring portion of the integrated circuit CHI, and TM is an output terminal / wiring portion of the integrated circuit CHI.
A bonding pad PAD of the integrated circuit CHI is connected to each inner end portion (commonly referred to as an inner lead) by a so-called face-down bonding method. Terminal T
B, the outer end portions (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively, and the liquid crystal is formed by the anisotropic conductive film ACF on the CRT / TFT conversion circuit / power supply circuit SUP by soldering or the like. Panel PN
It is connected to the liquid crystal panel so as to cover the protective film PSV1 exposing the connection terminal DTM on the L side. Therefore, the external connection terminal DTM (GTM) is covered with at least one of the protective film PSV1 and the tape carrier package TCP.
It becomes strong against electric corrosion.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that the solder does not adhere to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX or the like after cleaning, and the tape carrier package TCP and the upper transparent glass substrate S
Between UB2, silicone resin SIL is further filled to multiplex protection.

<< Manufacturing Method >> Next, a method of manufacturing the above-described lower transparent glass substrate SUB1 of the liquid crystal display device will be described with reference to FIGS. In each figure, the middle letters are abbreviations of the process names, the left side shows the pixel portion shown in FIG. 14, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal shown in FIG. Except for the process D, the processes A to I are classified according to the respective photographic processes, and all the cross-sectional views of the respective processes show the stage where the processing after the photographic process is completed and the photoresist is removed. I have.
Note that photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description thereof will be omitted. Less than,
A description will be given according to the divided steps.

[0111]Step A (FIG. 32) Lower transparent glass substrate made of 7059 glass (trade name)
Dip processing of silicon oxide film SIO on both sides of SUB1
Baking at 500 ° C for 60 minutes.
U. The film thickness is 1100 on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium (Cr) is sputtered.
After photo processing, nitric acid
Selectively select first conductive film g1 with 2 cerium ammonium solution
And the gate terminal GTM and the drain terminal DT
M, anodizing bus line S connecting gate terminal GTM
Hg, bus line SH for shorting drain terminal DTM
d, the anodizing pattern connected to the anodizing bus line SHg
A pad (not shown) is formed. Step B (FIG. 32) Al-Pd, Al-Si, Al-S with a thickness of 2800 °
Second conductive film g2 made of i-Ta, Al-Si-Cu, or the like
Is provided by sputtering. After photographic processing,
Etch the second conductive film g2 with a mixed acid solution of nitric acid and glacial acetic acid
To

Step C (FIG. 32) After photographic processing (after the formation of the anodic oxidation mask AO described above), 3
% Tartaric acid was adjusted to pH 6.25 ± 0.05 with ammonia, and the lower transparent glass substrate SUB was placed in an anodic oxidation solution consisting of a solution diluted 1: 9 with an ethylene glycol solution.
1 is immersed and adjusted (constant current formation) so that the formation current density becomes 0.5 mA / cm ² . Next, a predetermined Al ₂ O
₃ Anodizing is performed until the formation voltage 125 V necessary for obtaining the film thickness is reached. Thereafter, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is because the uniform Al
_This is important for obtaining a ₂ O ₃ film. Thereby,
The conductive film g2 is anodized to form an anodic oxide film AOF having a thickness of 1800 ° on the scanning signal line GL, the gate electrode GT, and the electrode PL1.

Step D (FIG. 33) Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 2000-nm-thick Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form a film. After providing an i-type amorphous Si film having a thickness of 2000 °, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus to form an N (+)-type amorphous Si film having a thickness of 300 °.

Step E (FIG. 33) After photographic processing, SF ₆ and CC are used as dry etching gases.
Using l ₄ , an N (+)-type amorphous Si film and an i-type amorphous S
By selectively etching the i-film, islands of the i-type semiconductor layer AS are formed.

Step F (FIG. 33) After the photographic processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Step G (FIG. 34) A first conductive film d1 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form

Step H (FIG. 34) A second conductive film d2 made of chromium Cr having a thickness of 600 ° is provided by sputtering, and further a Al-Pd, Al-Si, Al-Si-Ti, Al- S
A third conductive film d3 made of i-Cu or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as in the step B, the second conductive film d2 is etched with the same liquid as in the step A, and the video signal line DL and the source electrode SD are etched.
1. The drain electrode SD2 is formed. Next, by introducing CCl ₄ and SF ₆ into a dry etching apparatus and etching the N (+)-type amorphous Si film, the N (+)-type semiconductor layer d0 between the source and the drain is selectively formed. Remove.

Step I (FIG. 34) Ammonia gas, silane gas and nitrogen gas are introduced into a plasma CVD apparatus to form a 1 μm-thick Si nitride film. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo etching technique (photolithography technique) using SF ₆ as a dry etching gas.

An alignment film is formed on the innermost surface of the lower transparent glass substrate SUB1 manufactured in this way, and the upper transparent glass substrate SUB2 manufactured in a separate manufacturing process is bonded. The liquid crystal panel PNL is obtained by sandwiching and sealing with a sealing material, and attaching polarizing plates (POL1, POL2) on both sides.

The liquid crystal panel PNL is connected to a backlight,
Liquid crystal display device (liquid crystal display module) laminated with other optical films, etc., and incorporating various drive circuit boards
To be integrated.

FIG. 35 is a plan view showing a state where the liquid crystal panel and the drive circuit board are connected. CHI is liquid crystal panel P
An integrated circuit (IC) chip for driving the NL (the lower five ICs on the vertical scanning circuit side and the left ten ICs on the video signal driving circuit side. The number of these integrated circuits is liquid crystal Depending on the resolution of the panel, the higher the definition, the larger the number is required.

The TCP is, as shown in FIGS. 22 and 23,
A tape carrier package (TCP) in which an IC chip CHI of a drive circuit is mounted by a tape automated bonding (TAB) method, and a PCB1 is a drive circuit board on which the above-described TCP and capacitors are mounted. It is divided into two for the drive circuit.

FGP is a frame ground pad.
A spring-shaped fragment provided by cutting into the shield case SHD is soldered. FC is the lower drive circuit board PC
This is a flat cable for electrically connecting B1 to the left drive circuit board PCB1.

As shown in the figure, as the flat cable FC, a plurality of lead wires (phosphor bronze material plated with Sn) were sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer. Use things.

<< TCP Connection Structure >> FIG. 22 is a sectional view of a tape carrier package in which an integrated circuit chip CHI constituting the scanning signal driving circuit V and the video signal driving circuit H is mounted on a flexible wiring board. FIG. 4 is a sectional view of a main part of the liquid crystal panel, here showing a state connected to a scanning signal circuit terminal GTM.

TTB is an input terminal / wiring portion of the integrated circuit chip CHI, and TTM is an output terminal / wiring portion of the integrated circuit chip CHI. The TTM is made of, for example, Cu. As described above, the bonding pads PAD of the integrated circuit chip CHI are connected by a so-called face-down bonding method.

The outer ends (outer leads) of the terminals TTB and TTM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
As described above, the RT / TFT conversion circuit / power supply circuit SUP is connected to the liquid crystal panel PNL by the anisotropic conductive film ACF.

The package TCP has a protective film PSV whose leading end exposes the connection terminal GTM on the liquid crystal panel PNL side.
1 is connected to the liquid crystal panel PNL so as to cover the liquid crystal panel PNL. Therefore, the outer connection terminal GTM (DTM) is connected to the protective film PSV1.
Is covered with at least one of the package TCPs, and thus is resistant to electrolytic corrosion.

As described above, BF1 is a base film made of a resin such as polyimide, and SRS is a solder resist film for masking so that solder does not adhere to unnecessary portions during soldering. Seal pattern SL
The gap between the upper and lower transparent glass substrates on the outside is protected by an epoxy resin EPX or the like after cleaning, and a silicon resin SI is further provided between the package TCP and the upper transparent glass substrate SUB2.
L is filled and protection is multiplexed.

<< Drive Circuit Board PCB2 >> Drive Circuit Board P
Electronic components such as an IC, a capacitor, and a resistor are mounted on the CB2. As described above, this drive circuit board PC
B2 is equipped with a power supply circuit for dividing the voltage from one voltage source to obtain a plurality of stabilized voltage sources, and a circuit SUP including a circuit for converting CRT information from the host into information for the liquid crystal display device. Have been. CJ is a connector connecting portion for a connector (not shown) connected to the outside.

Drive circuit board PCB1 and drive circuit board PC
B2 is electrically connected by a joiner JN such as a flat cable FC.

FIG. 36 is an external view of a notebook personal computer as an example of an electronic apparatus on which the liquid crystal display device according to the present invention is mounted.

In this notebook computer, a keyboard unit and a display unit are connected by a hinge, and the keyboard unit has a CP.
A host computer made of a U or the like is mounted, and the liquid crystal display device according to the present invention is mounted on a display unit as a liquid crystal display module (MDL).

Drive circuit boards PCB1, PCB1 are provided around a liquid crystal panel PNL constituting the liquid crystal display module.
2, a PCB 3, an inverter power supply IV for backlight, and the like. Note that CT is a connector connected to the host, and TCON is a control circuit that generates signal processing for displaying an image on the liquid crystal panel PNL and a timing signal based on a display signal input from the host.

The liquid crystal display device according to the present invention can be used not only for a portable personal computer such as a notebook type as shown in FIG. 36 but also for a stationary personal computer such as a desktop monitor and a display device of other equipment. Needless to say.

The present invention can be applied not only to the above-described type in which the driver is mounted on the TCP but also to a method in which a transistor is formed directly around an insulating substrate (glass substrate) constituting a liquid crystal panel. The present invention is not limited to the vertical electric field type active matrix type liquid crystal display device, but is similarly applied to the horizontal electric field type active matrix type liquid crystal display device or the simple matrix type liquid crystal display device. it can.

[0137]

As described above, according to the present invention,
Conventionally, a separate photomask was easily used for each ion-implanted layer, but by changing the thickness of the through oxide film for ion-implantation and changing the order of the MOS transistor manufacturing process, a single ion-implantation was performed. Thus, impurity regions having different concentrations can be formed, the number of photomasks can be reduced, and the number of steps can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating the principle of ion implantation in a method for manufacturing a MOS transistor according to the present invention.

FIG. 2 is a process chart schematically showing one embodiment of a method for manufacturing a MOS transistor according to the present invention.

FIG. 3 is a process diagram subsequent to FIG. 2, schematically showing one embodiment of the method for manufacturing a MOS transistor according to the present invention;

FIG. 4 is a process diagram illustrating an embodiment in which the present invention is applied to a manufacturing process of a liquid crystal panel driver.

FIG. 5 is a process drawing following FIG. 4 for explaining an embodiment in which the present invention is applied to a manufacturing process of a liquid crystal panel driver.

FIG. 6 is a process drawing following FIG. 5 for explaining an embodiment in which the present invention is applied to a manufacturing process of a liquid crystal panel driver.

FIG. 7 is a process drawing following FIG. 6 for explaining an embodiment in which the present invention is applied to a manufacturing process of a liquid crystal panel driver.

FIG. 8 is a process chart schematically showing another embodiment of the method for manufacturing a MOS transistor according to the present invention.

FIG. 9 is a process diagram subsequent to FIG. 8, schematically showing another embodiment of the method for manufacturing a MOS transistor according to the present invention.

FIG. 10 is a schematic structural diagram of a planar MOS transistor to which the present invention can be applied.

FIG. 11 is a schematic structural view of a LOCOS offset type MOS transistor to which the present invention can be applied.

FIG. 12 shows a LOCOS offset type M to which the present invention is applied.
FIG. 3 is a schematic structural diagram of an OS transistor.

FIG. 13 is a plan view showing one pixel and a light-shielding region of a black matrix BM and its periphery constituting a vertical electric field type active matrix type color liquid crystal display device according to the present invention.

FIG. 14 is a cross-sectional view showing one pixel and its periphery taken along section line 3-3 in FIG. 8;

FIG. 15 shows an additional capacitance element C taken along section line 4-4 in FIG. 8;
It is sectional drawing of add.

16 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels of FIG. 8 are arranged.

FIG. 17 is a plan view for explaining a configuration of a matrix peripheral portion of a display panel.

FIG. 18 is a plan view for slightly more specifically explaining the peripheral portion of FIG. 12;

FIG. 19 is an enlarged plan view of a corner portion of a liquid crystal panel including electrical connection portions of upper and lower transparent glass substrates.

FIG. 20 is a cross-sectional view showing the vicinity of a corner of a liquid crystal panel and the vicinity of a video signal terminal on both sides with a pixel portion of a matrix at the center.

FIG. 21 is a cross-sectional view showing a scanning signal terminal on the left side and a liquid crystal panel edge portion without an external connection terminal on the right side.

FIG. 22 is a cross-sectional view showing a structure of a tape carrier package in which an integrated circuit chip constituting a driving circuit is mounted on a flexible wiring board.

FIG. 23 is an essential part cross sectional view showing a state where a tape carrier package is connected to a video signal circuit terminal of a liquid crystal panel.

24 is a plan view illustrating only a conductive layer g2 and an i-type semiconductor layer AS of the pixel illustrated in FIG.

FIG. 25 is a diagram showing conductive layers d1, d2, and d3 of the pixel shown in FIG.
It is the top view which drew only.

26 is a plan view illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel illustrated in FIG.

FIG. 27 is a plan view of a principal part in which only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel array shown in FIG. 11 are drawn.

FIG. 28 is an explanatory diagram near a connection portion between a gate terminal and a gate wiring.

FIG. 29 is an explanatory diagram near a connection portion between a drain terminal and a video signal line.

FIG. 30 is an equivalent circuit diagram showing a liquid crystal display portion of an active matrix type color liquid crystal display device.

FIG. 31 is an equivalent circuit diagram of the pixel shown in FIG. 8;

FIG. 32 is an explanatory diagram of a manufacturing process for the lower transparent glass substrate side.

FIG. 33 is an explanatory view following FIG. 32 of the manufacturing process for the lower transparent glass substrate side;

FIG. 34 is an explanatory view following FIG. 33 of the manufacturing process for the lower transparent glass substrate.

FIG. 35 is a plan view showing a state where a liquid crystal panel and a drive circuit board are connected.

FIG. 36 is an external view of a notebook computer illustrating an example of an electronic device on which the liquid crystal display device of the present invention is mounted.

FIG. 37 is a process chart illustrating an example of a conventional impurity region forming process.

FIG. 38 is a process chart illustrating another example of the conventional impurity region forming process.

FIG. 39 is a schematic process diagram for explaining the manufacturing process of the driver of the active matrix type liquid crystal panel having the high breakdown voltage type MOS transistor;

FIG. 40 is a schematic process diagram following FIG. 39 for explaining the manufacturing process of the driver of the active matrix liquid crystal panel having the high-breakdown-voltage MOS transistor;

[Explanation of symbols]

HNW Well of high-breakdown-voltage PMOS transistor HPW Well of high-breakdown-voltage NMOS transistor NW Well of low-breakdown-voltage PMOS transistor PW Well of low-breakdown-voltage NMOS transistor HNM Electric field relaxation layer of drain / source portion of high-breakdown-voltage NMOS transistor HPM High breakdown voltage Electric field relaxation layer at drain / source portion of system PMOS transistor NF Channel stopper in field region of well of high breakdown voltage NMOS transistor and well of low breakdown voltage NMOS transistor PF Well of high breakdown voltage PMOS transistor and well of low breakdown voltage PMOS transistor Channel stopper in the field area.

Continued on the front page (72) Inventor Masami Koketsu 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in the Semiconductor Division, Hitachi, Ltd. (Reference) 2H092 JA22 JA28 KA07 KA10 MA06 MA14 MA27 MA27 MA37 NA27 PA01 5F048 AA09 AB07 AC04 BA01 BC06 BE01 BE05 BE06 BG12 BH07 DA10

Claims (2)

[Claims] 1. A method of manufacturing a MOS transistor, comprising the step of forming well regions having different impurity concentrations in a semiconductor substrate by ion implantation, wherein an oxide film having a different thickness is coated on an upper layer of the semiconductor substrate.
A region having a different impurity concentration due to a difference in the thickness of the oxide film formed by one ion implantation;
A method for manufacturing an OS transistor. 2. A high breakdown voltage MOS transistor used at a high voltage and a low breakdown voltage MO used at a low voltage according to a difference in working voltage.
In a method of manufacturing a MOS transistor in which an S transistor is mixed on the same semiconductor substrate to form a well region having a different impurity concentration due to a difference in operating voltage, a well of a high withstand voltage MOS transistor having a low impurity concentration is formed first, By forming a field oxide film for electrically separating the MOS transistors from each other and then forming a well of the low breakdown voltage MOS transistor having a high impurity concentration, the drain of the high breakdown voltage MOS transistor is formed in the well ion implantation step of the low breakdown voltage MOS transistor. A method of manufacturing a MOS transistor, wherein an electric field relaxation layer in a source portion and a channel stopper for a parasitic MOS transistor are simultaneously formed.