JPH06258666A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the generation of unequal brightness and malfunction by positioning the ends in the channel width direction of the source electrode and drain electrode of a thin film transistor(TFT) on the side more outside than the end in the channel width direction of a semiconductor layer. CONSTITUTION:A transparent pixel electrode is connected to both of the source electrode SD1 of the TFT1 and the source electrode SD2 of the TFT2. The source electrode SD1 and drain electrode SD2 are respectively constituted of a second conductive film in contact with the n (+) type semiconductor layer and a third conductive film formed thereon. The ends in the channel width direction of the source electrode SD1 and the drain electrode SD2 are positioned on the side more outside than the end in the channel width direction of the i type semiconductor layer AS. The arrival of the light at the end in the channel width direction of the i type semiconductor layer AS is prevented by the source electrode SD1 and the drain electrode SD2, by this constitution and, therefore, the unequal brightness and the malfunction do not arise any more.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device using thin film transistors, and more particularly to an OHP having a high brightness lamp and a liquid crystal display device used for a projector.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active system has better contrast than the so-called simple matrix system, which employs the time-division driving system, and especially the color liquid crystal display device. Then it is becoming an indispensable technology. A typical example of the switching element is a thin film transistor (TFT).

FIG. 25 is a plan view showing a thin film transistor portion of a conventional active matrix type liquid crystal display device,
FIG. 26 is a sectional view showing the thin film transistor portion shown in FIG. As shown in the figure, the thin film transistors TFT1 and TFT are provided at the intersections of the scanning signal lines GL and the video signal lines DL.
Two are provided. Thin film transistor TFT1, TF
T2 is on the gate electrode GT connected to the scanning signal line GL, the source electrode SD1 connected to the transparent pixel electrode ITO1, the drain electrode SD2 connected to the video signal line DL, the i-type semiconductor layer AS, and the i-type semiconductor layer AS. Is formed of an N (+) type semiconductor layer d0, an anodized film AOF provided between the gate electrode GT and the i type semiconductor layer AS, and an insulating film GI. Further, a silicon oxide film SIO is provided on the surface of the lower transparent glass substrate SUB1, a protective film PSV1 for protecting the thin film transistor TFT is provided, and an alignment film ORI1 is provided on the protective film PSV1. The ends of the source electrode SD1 and the drain electrode SD2 in the channel width direction are located inside the ends of the i-type semiconductor layer AS in the channel width direction.

FIG. 27 is a plan view showing a thin film transistor portion of another conventional active matrix type liquid crystal display device, and FIG. 28 is a sectional view showing the thin film transistor portion shown in FIG. As shown in the figure, the thin film transistor TF
The light shielding film LSF is provided between the protective film PSV1 and the alignment film ORI1 in the T portion.

An active matrix type liquid crystal display device using thin film transistors is disclosed in, for example, Japanese Unexamined Patent Publication No. 63-309921, "1.
2.5-inch active matrix color LCD ", Nikkei Electronics, pages 193-210, 1986 12
Known on the 15th of March, published by Nikkei McGraw-Hill, Inc.

[0006]

In the liquid crystal display device shown in FIGS. 25 and 26, the light incident from the opening of the light shielding film (black matrix) provided on the upper transparent glass substrate is interfered or irregularly reflected. Since it reaches the i-type semiconductor layer AS, holes and electrons are generated in the i-type semiconductor layer AS, and luminance unevenness malfunctions and the like occur, so that the display quality deteriorates.

Further, in the liquid crystal display device shown in FIGS. 27 and 28, the light incident from the opening of the light-shielding film (black matrix) provided on the upper transparent glass substrate by the light-shielding film LSF is transmitted to the i-type semiconductor layer AS. Can be reached. However, since capacitance is formed between the source electrode SD1 and drain electrode SD2 and the light shielding film LSF, the coupling capacitance Cds between the source electrode SD1 and drain electrode SD2 as shown in FIG. The ratio of the signal of the signal line DL directly entering the transparent pixel electrode ITO1 without passing through the thin film transistor TFT increases. Therefore, a malfunction called smear occurs and the display quality deteriorates.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device having good display quality.

[0009]

In order to achieve this object, in a first aspect of the invention, in a liquid crystal display device having a thin film transistor, the ends of the source electrode and the drain electrode of the thin film transistor in the channel width direction are formed of a semiconductor layer. It is located outside the end in the channel width direction.

In a second aspect of the present invention, in a liquid crystal display device having a thin film transistor, a first light shielding film located above the source electrode of the thin film transistor and below the alignment film, and above the drain electrode of the thin film transistor. Further, at least one of the second light shielding films located below the alignment film is provided.

[0011]

In the liquid crystal display device according to the first aspect of the present invention, since the source electrode and the drain electrode can prevent light from reaching the end portion of the semiconductor layer in the channel width direction, a malfunction such as uneven brightness occurs. And there is no light-shielding film above the semiconductor layer and below the alignment film,
Since the coupling capacitance between the source electrode and the drain electrode does not increase, a malfunction called smear does not occur, and the display quality is good.

Further, in the liquid crystal display device according to the second invention, light can be prevented from reaching the semiconductor layer by the first and second light-shielding films, so that there is no occurrence of uneven brightness operation. Also, since there is no light-shielding film located above the source electrode and the drain electrode and below the alignment film, the coupling capacitance between the source electrode and the drain electrode does not increase, so a malfunction called smear does not occur. Therefore, the display quality is good.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS The invention, further objects of the invention and further features of the invention will become apparent from the following description with reference to the drawings.

<< Active Matrix Liquid Crystal Display Device >>
An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

<< Outline of Matrix Section >> FIG. 2 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device to which the present invention is applied, and FIG.
3 is a cross-sectional view taken along the line -3, and FIG. 4 is a cross-sectional view taken along the line 4-4 in FIG.

As shown in FIG. 2, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL.
And an adjacent two video signal lines (drain signal line or vertical signal line) DL are intersected with each other (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the vertical direction. Video signal line DL
Extend in the up-down direction and are arranged in the left-right direction.

As shown in FIG. 3, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal LC layer, and a color filter FIL and a black matrix are formed on the upper transparent glass substrate SUB2 side. A pattern light-shielding film BM is formed. Silicon oxide films SIO formed by dipping or the like are provided on both surfaces of the transparent glass substrates SUB1 and SUB2.

A light-shielding film BM and a color filter FI are formed on the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

<< Outline of Matrix Periphery >> FIG. 5 is a diagram showing a plane of a main part around a matrix AR of a display panel PNL including transparent glass substrates SUB1 and SUB2, and FIG. 6 is a diagram showing a further exaggerated plane of the periphery. FIG. 7 is a diagram showing an enlarged plane near the seal pattern SL corresponding to the upper left corner of the panel of FIGS. 5 and 6. 8 is a cross section taken along the line 8a-8a in FIG. 7 with the cross section of FIG. 3 at the center, and the cross section near the drain terminal DTM, which is an external connection terminal to which the video signal drive circuit is to be connected, on the right side. FIG. Similarly, FIG. 9 is a diagram showing a cross section near the gate terminal GTM, which is an external connection terminal to which the vertical scanning circuit is to be connected, on the left side and a cross section near the seal portion where there is no external connection terminal on the right side.

In the manufacture of this display panel, if the size is small, a plurality of devices are simultaneously processed on one glass substrate for the purpose of improving throughput, and if the size is large, the manufacturing equipment is shared. In any product, a glass substrate having a standardized size is processed, and then the size is reduced to a size suitable for each product. In any case, the glass substrate is cut after one step. 5 to 7 show an example of the latter, both of which are shown in FIG. 5 and FIG.
7 shows the state after cutting UB1 and SUB2, and FIG. 7 shows the state before cutting. LN indicates the edges of the transparent glass substrates SUB1 and SUB2 before cutting, and CT1 and CT2 indicate the transparent glass substrates SU, respectively.
The cutting line which should cut | disconnect B1 and SUB2 is shown. In any case, the size of the upper transparent glass substrate SUB2 is lower transparent so that the external connection terminal groups Tg and Td (subscripts omitted) (upper side and left side in the figure) are exposed in the completed state. It is limited to the inside of the glass substrate SUB1. Each of the terminal groups Tg and Td is a tape carrier package TC in which a gate terminal GTM for connecting a vertical scanning circuit, a drain terminal DTM for connecting a video signal driving circuit, and lead-out wiring portions thereof, which are to be described later, are mounted on an integrated circuit chip CHI.
A plurality of Ps (FIGS. 18 and 19) are collectively named. The lead wiring from the matrix AR portion of each group to the external connection terminal portion is inclined toward both ends. This is because the arrangement pitch of the tape carrier package TCP and the connection terminal pitch of each tape carrier package TCP are set to the terminals DTM of the display panel PNL,
This is to match the GTM.

A liquid crystal LC is provided between the transparent glass substrates SUB1 and SUB2 along the edge thereof except for the liquid crystal inlet INJ.
A seal pattern SL is formed so as to seal the. The seal pattern SL is made of, for example, epoxy resin. Common transparent pixel electrode ITO on the upper transparent glass substrate SUB2 side
In at least one place, 2 is connected to the lead wiring INT formed on the lower transparent glass substrate SUB1 side by the silver paste material AGP at the four corners of the display panel PNL in this display device. The lead wiring INT is formed in the same manufacturing process as a gate terminal GTM and a drain terminal DTM described later.

The respective layers of the orientation films ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2 are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are lower transparent glass substrates SUB, respectively.
1. Formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is enclosed in a region partitioned by a seal pattern SL between a lower alignment film ORI1 and an upper alignment film ORI2 that set the orientation of liquid crystal molecules. The lower alignment film ORI1 is a protective film P on the lower transparent glass substrate SUB1 side.
It is formed on top of SV1.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, the seal pattern SL is formed on the upper transparent glass substrate SUB2 side, and the upper transparent glass substrate SUB is formed.
1 and the lower transparent glass substrate SUB2 are overlapped, the liquid crystal LC is injected from the liquid crystal sealing port INJ of the seal pattern SL, the liquid crystal sealing port INJ is sealed with epoxy resin or the like, and the transparent glass substrates SUB1 and SUB2 are cut. Assembled by

<< Thin Film Transistor TFT >> Next, referring to FIG.
Returning to FIG. 3, the configuration on the lower transparent glass TFT substrate SUB1 side on which the thin film transistor TFT is formed will be described in detail.

The thin film transistor TFT has a gate electrode G
When a positive bias is applied to T, the channel resistance between the source and the drain decreases, and when the bias is zero, the channel resistance increases.

A plurality of (two) thin film transistors TFT1 and TFT2 are redundantly provided in each pixel. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same), and has a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic,
intrinsic, conductivity type determination impurities are not doped)
It has an i-type semiconductor layer AS made of amorphous Si, a pair of source electrodes SD1 and a drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

<< Gate Electrode GT >> The gate electrode GT has a shape protruding vertically from the scanning signal line GL (branched into a T shape). The gate electrode GT projects so as to extend beyond the respective active regions of the thin film transistors TFT1 and TFT2. Thin film transistor TFT
The gate electrodes GT of the TFT 1 and the TFT 2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of the single-layer second conductive film g2. As the second conductive film g2, for example, A formed by sputtering is used.
1 film is used, and an Al anodic oxide film AOF is provided thereon.

The gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below), and is devised so that the i-type semiconductor layer AS is not exposed to external light or backlight light. .

<< Scanning Signal Line GL >> The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. Also, an Al anodic oxide film AOF is provided on the scanning signal line GL.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the i-type semiconductor layer AS together with the gate electrode GT in the thin film transistors TFT1 and TFT2. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. Insulation film GI
For example, Si nitride formed by plasma CVD
A film is selected and formed to a thickness of 1200 to 2700Å (about 2000Å in this display device). As shown in FIG. 7, the gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion has a terminal DTM for external connection,
Removed to expose GTM. The insulating film GI also contributes to electrical insulation between the scanning signal line GL and the video signal line DL.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
In this example, is amorphous Si formed as islands independent of each of the thin film transistors TFT1 and TFT2.
Then, in the thickness of 200-2200Å (in this display device,
The film thickness is about 2000Å). d0 is an N (+) type semiconductor layer made of N (+) type amorphous Si doped with phosphorus (P) for ohmic contact, the i type semiconductor layer AS exists on the lower side, and the conductive film on the upper side. It is left only where d2 (d3) exists.

The i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Transparent Pixel Electrode ITO1 >> Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by laser light or the like, and if not, the other thin film transistor operates normally. You can leave it alone. The transparent pixel electrode ITO1 is composed of the first conductive film d1.
Is a transparent conductive film (Indium-Tin) formed by sputtering.
-Oxide ITO: Nesa film), 1000-200
It is formed to a thickness of 0Å (a film thickness of about 1400Å in this display device).

<< Source Electrode SD1, Drain Electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is composed of a second conductive film d2 in contact with the N (+) type semiconductor layer d0 and a third conductive film d3 formed thereon.

The second conductive film d2 is Cr formed by sputtering.
The film is formed to have a thickness of 500 to 1000Å (about 600Å in this display device). Since the stress increases when the Cr film is formed thicker, the Cr film is formed within the range of about 2000 Å. The Cr film improves adhesion to the N (+) type semiconductor layer d0 and prevents Al of the third conductive film d3 from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). used. As the second conductive film d2, in addition to the Cr film, refractory metals (Mo, Ti, T
a, W) film, refractory metal silicide (MoSi ₂ , Ti)
A Si ₂ , TaSi ₂ , WSi ₂ ) film may be used.

The third conductive film d3 is formed by sputtering Al to a thickness of 3000 to 5000 Å (4 in this display device).
000Å) formed. The Al film has less stress than the Cr film and can be formed to have a thick film thickness, which reduces the resistance values of the source electrode SD1, the drain electrode SD2 and the video signal line DL, and the gate electrode GT and the i-type semiconductor. It has a function of ensuring that a step difference caused by the layer AS is overcome (improving the step coverage).

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, an N (+) type film is formed by using the same mask or by using the second conductive film d2 and the third conductive film d3 as a mask. The semiconductor layer d0 is removed. That is,
The N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so that the entire thickness thereof is removed, the surface portion of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

As shown in FIG. 1, the source electrode SD
1. Since the ends of the drain electrode SD2 in the channel width direction are located outside the ends of the i-type semiconductor layer AS in the channel width direction, the source electrode SD1 and the drain electrode SD2
As a result, it is possible to prevent light from reaching the end portion of the i-type semiconductor layer AS in the channel width direction, so that the uneven brightness operation does not occur, and the alignment film ORI1 is formed above the i-type semiconductor layer AS. Since there is no light-shielding film below,
Since the coupling capacitance Csd between the source electrode SD1 and the drain electrode SD2 does not increase, a malfunction called smear does not occur, and the display quality is good.

<Video Signal Line DL> The video signal line DL is composed of a second conductive film d2 and a third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2.

<< Protective Film PSV1 >> Thin Film Transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a film thickness of about 1 μm.

As shown in FIG. 7, the protective film PSV1 is formed so as to surround the entire matrix portion AR, the peripheral portion is removed so as to expose the external connection terminals DTM and GTM, and the upper substrate side SUB2 is commonly transparent. Pixel electrode ITO2 (CO
The portion for connecting M) to the lead wire INT for connecting the external connection terminal of the lower transparent glass substrate SUB1 with the silver paste material AGP is also removed. Regarding the thickness relationship between the protective film PSV1 and the insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner considering the mutual conductance gm of the transistor. Therefore, as shown in FIG. 7, the protective film PSV1 having a high protective effect is formed to be larger than the insulating film GI so as to protect the peripheral portion over as wide a range as possible.

<< Light-shielding film BM >> Upper transparent glass substrate SUB
On the second side, a light shielding film BM is provided so that external light or backlight light does not enter the i-type semiconductor layer AS. The closed polygonal contour line of the light-shielding film BM shown in FIG. 2 indicates an opening inside which the light-shielding film BM is not formed. The light-shielding film BM has a high light-shielding property, such as an Al film or Cr.
It is formed of a film or the like, and in this display device, a Cr film is formed by sputtering to a thickness of about 1300Å.

Therefore, the thin film transistors TFT1,
The i-type semiconductor layer AS of the TFT 2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT, and external natural light or backlight light is not exposed.
The light-shielding film BM is formed in a lattice shape around each pixel (so-called black matrix), and the effective display area of one pixel is partitioned by this lattice. Therefore, the contour of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

Since the edge portion of the transparent pixel electrode ITO1 on the base side in the rubbing direction (lower right portion in FIG. 2) is also shielded by the light shielding film BM, even if a domain occurs in the above portion, the domain cannot be seen. The display characteristics do not deteriorate.

As shown in FIG. 6, the light-shielding film BM is also formed in a frame shape in the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. There is. As shown in FIGS. 6 to 9, the peripheral light shielding film BM is extended to the outside of the seal pattern SL to prevent leaked light such as reflected light caused by a mounting machine such as a personal computer from entering the matrix portion. . On the other hand, this light-shielding film B
M is about 0.3 to more than the edge of the upper transparent glass substrate SUB2.
The upper transparent glass substrate SU which is clamped inside by about 1.0 mm
It is formed so as to avoid the cutting region of B2.

<< Color Filter FIL >> The color filter FIL is formed in a stripe shape by repeating red, green and blue at positions facing the pixels. The color filter FIL is formed to have a large size so as to cover all of the transparent pixel electrode ITO1, and the light shielding film BM overlaps with the edge portions of the color filter FIL and the transparent pixel electrode ITO1.
It is formed inside the peripheral portion of TO1.

The color filter FIL can be formed as follows. First, a dyeing base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

<< Protective Film PSV2 >> The protective film PSV2 is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal LC. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

<< Common Transparent Pixel Electrode ITO2 >> The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. In this display device, the common voltage Vcom is set to an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL, but it is used in the video signal drive circuit. If it is desired to reduce the power supply voltage of the circuit to about half, an AC voltage may be applied. For the planar shape of the common transparent pixel electrode ITO2, see FIGS. 6 and 7.

<< Structure of Storage Capacitance Element Cadd >> The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. In this superposition, as is clear from FIG. 4, the transparent pixel electrode ITO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used as the other electrode PL.
A holding capacitance element (electrostatic capacitance element) Cadd which is 1 is configured. The dielectric film of the storage capacitor Cadd is an insulating film G used as a gate insulating film of the thin film transistor TFT.
I and the anodic oxide film AOF.

The storage capacitor element Cadd is formed in the portion where the width of the second conductive film g2 of the scanning signal line GL is widened. The second conductive film g2 at the portion intersecting the video signal line DL is thinned in order to reduce the probability of short circuit with the video signal line DL.

Even if the transparent pixel electrode ITO1 is broken at the step portion of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d2 formed so as to cross the step.
The defect is compensated by the island region formed of the conductive film d3.

<< Gate Terminal GTM >> FIG. 10 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to the gate terminal GTM which is an external connection terminal thereof. FIG. 10A is a plan view and FIG. It is sectional drawing in the BB cutting line of A). It should be noted that the figure corresponds to the lower part of FIG. 7, and the diagonal wiring portions are shown in a straight line for convenience.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodic oxidation, and the pattern AO shown in the figure does not remain as a finished product, but the oxide film AO is formed on the scanning signal line GL as shown in the sectional view.
Since F is selectively formed, its locus remains. In the plan view, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized. The anodized second conductive film (Al layer) g2 has an anodized film (Al ₂ O ₃ film) AOF, which is an oxide thereof, formed on the surface thereof, so that the volume of the lower conductive portion is reduced. Of course, anodic oxidation is performed by setting an appropriate time, voltage, etc. so that the conductive portion remains. The mask pattern AO does not intersect the scanning signal line GL by a single straight line, but is bent in a crank shape and intersects.

In the figure, the second conductive film g2 is hatched for easy understanding, but the region which is not anodized is patterned in a comb shape. This is because whiskers are generated on the surface when the width of the second conductive film g2 is wide. Therefore, by narrowing the width of each one and by bundling them in parallel, the generation of whiskers can be prevented. At the same time, the aim is to minimize the probability of wire breakage and the sacrifice of conductivity. Therefore,
In this example, the portion corresponding to the root of the comb is also the mask pattern AO.
Are staggered along.

The gate terminal GTM is a silicon oxide film SIO.
And a first conductive film (Cr layer) g1 having good adhesiveness and higher electric contact resistance than Al and the like, and protecting the surface of the first conductive film g1 at the same level as the transparent pixel electrode ITO1 (same layer, simultaneous formation)
And the first (transparent) conductive film d1. In addition,
Conductive film d formed on insulating film GI and on its side surface
2 and d3 remain as a result of covering the regions with photoresist so that the conductive films g2 and g1 are not etched together due to pinholes or the like during the etching of the conductive films d3 and d2. In addition, the first conductive film (ITO layer) d1 which extends over the insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the gate terminal GTM portion located at the left end is exposed from them and the external circuit is formed. It is possible to make electrical contact with. In the figure, only one pair of the scanning signal line GL and the gate terminal GTM is shown, but in reality, a plurality of such pairs are arranged vertically as shown in FIG. 7 and the terminal group Tg (FIGS. 6 and 7). In the manufacturing process, the left end of the gate terminal GTM is extended beyond the cutting line CT1 of the lower transparent glass substrate SUB1 and short-circuited by the wiring SHg. Such short-circuit wiring SHg in the manufacturing process is useful for supplying power during anodic oxidation and preventing electrostatic breakdown during rubbing of the alignment film ORI1.

<< Drain Terminal DTM >> FIG. 11 shows a drain terminal DTM which is an external connection terminal of the video signal line DL.
2A is a plan view, and FIG. 4B is a cross-sectional view taken along the line BB of FIG. 7 corresponds to the vicinity of the upper right of FIG. 7, and the orientation of the drawing is changed for convenience, but the right end direction corresponds to the upper end portion (or lower end portion) of the lower transparent glass substrate SUB1.

TSTd is an inspection terminal, and inspection terminal TS
Although an external circuit is not connected to Td, the width is wider than that of the wiring portion so that a probe needle or the like can come into contact therewith. Similarly,
The drain terminal DTM is also wider than the wiring portion so that it can be connected to an external circuit. The inspection terminals TSTd and the drain terminals DTM for external connection are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the lower transparent glass substrate SUB1 as shown in the figure. , The drain terminal DTM constitutes a terminal group Td (subscripts omitted) as shown in FIG. 7, and is further extended beyond the cutting line CT1 of the lower transparent glass substrate SUB1. Wires to each other SHd
Shorted by. The drain terminal DTM is connected to the opposite side of the matrix of the video signal lines DL including the inspection terminals TSTd, and conversely, the inspection terminal TSTd is provided on the opposite side of the matrix of the video signal lines DL including the drain terminals DTM. Are connected.

The drain terminal DTM is formed of two layers of the first conductive film (Cr layer) g1 and the first conductive film (ITO layer) d1 for the same reason as the gate terminal GTM described above.
The part where the insulating film GI is removed is connected to the video signal line DL. Semiconductor layer AS formed on the end of the insulating film GI
Is for etching the edge of the insulating film GI into a tapered shape. The protective film PSV1 is, of course, removed on the drain terminal DTM to connect to an external circuit. AO is the anodizing mask pattern described above,
The boundary is formed so as to largely surround the entire matrix, and the left side of the boundary is covered with a mask in the figure, but since the second conductive film g2 does not exist in the part not covered in this figure, this pattern Is not directly related.

The lead-out wiring from the matrix portion to the drain terminal DTM portion is, as shown in FIG. 8C, the video signal line DL immediately above the conductive films d1 and g1 at the same level as the drain terminal DTM portion. Conductive films d2 and d of the same level as
3 has a structure in which the seal pattern SL is laminated halfway, but this minimizes the probability of disconnection, and the third conductive film (Al layer) d3, which is easy to contact with electricity, is provided with the protective film PSV1 and the seal pattern SL. The aim is to protect as much as possible.

<< Equivalent Circuit of Entire Display Device >> FIG. 12 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device which displays information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a plurality of divided and stabilized voltage sources from one voltage source. It is a circuit including a circuit for exchanging information for use.

<< Function of Storage Capacitance Element Cadd >> The storage capacity element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg where Cgs is the gate electrode G of the thin film transistor TFT
Parasitic capacitance formed between T and source electrode SD1, C
pix is a liquid crystal capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM),
ΔVlc represents the amount of change in the pixel electrode potential due to ΔVg.
This variation ΔVlc causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the holding capacitance Cadd is increased. In addition, the storage capacitor Cadd
Has the effect of prolonging the discharge time, the thin film transistor T
The image information after the FT is turned off is stored for a long time. Liquid crystal LC
The reduction of the DC component applied to the liquid crystal can improve the life of the liquid crystal LC and reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large enough to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and thus the parasitic capacitance Cgs is increased. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, the storage capacitor Cadd
By providing the above, this demerit can be eliminated.

The storage capacitance of the storage capacitance element Cadd is 4 to 8 times (4.C
pix <Cadd <8 · Cpix), 8 to 3 for parasitic capacitance Cgs
Set to a value about twice (8 · Cgs <Cadd <32 · Cgs).

The scanning signal line GL (Y ₀ ) in the first stage, which is used only as the storage capacitor electrode line, is the common transparent pixel electrode ITO2.
Set to the same potential as (Vcom). In the example of FIG. 7, the scanning signal line at the first stage is the common transparent pixel electrode ITO2 (CO2) through the terminal GT0, the lead wiring INT, the terminal DT0 and the external wiring.
Shorted to M). Alternatively, the first-stage storage capacitor electrode line Y
₀ may be connected to the scanning signal line Yend at the final stage, may be connected to a DC potential point (AC grounding point) other than Vcom, or may be connected to receive one extra scanning pulse Y ₀ from the vertical scanning circuit V. .

<< Manufacturing Method >> Next, a manufacturing method of the lower transparent glass substrate SUB1 side of the above-described liquid crystal display device will be described with reference to FIGS. In the figure, the letters in the center are abbreviations of process names, the left side shows the pixel portion shown in FIG. 3, and the right side shows the processing flow as seen in the sectional shape near the gate terminal shown in FIG. Except for the step D, steps A to I are divided corresponding to each photographic process, and all the cross-sectional views of each process show the stage after the photo process is finished and the photoresist is removed. In this description, the photographic processing means a series of operations from the application of the photoresist to the selective exposure using the mask to the development thereof, and the repetitive description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 13 After forming a silicon oxide film SIO on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of Cr is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a cerium ammonium nitrate solution as an etching solution. As a result, the gate terminal GTM, the drain terminal DTM, the wiring (anodic oxidation bus line) SHg connecting the gate terminal GTM, the wiring (bus line) SHd shorting the drain terminal DTM, and the wiring (anodization bus line) SHg are connected. An anodized pad (not shown) is formed.

Step B, FIG. 13 Al-Pd, Al-Si, Al-S having a film thickness of 2800Å
The second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Are provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step C, FIG. 13 After photographic processing (after forming the above-mentioned anodic oxidation mask AO), 3
Lower transparent glass substrate SUB1 in an anodic oxidation solution consisting of a solution of% tartaric acid adjusted to pH 6.25 ± 0.05 with ammonia diluted with ethylene glycol solution 1: 9
Is soaked and adjusted so that the formation current density is 0.5 mA / cm ² (constant current formation). Next, anodic oxidation is performed until the formation voltage 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is uniform Al ₂
This is important in obtaining an O ₃ film. As a result, the second conductive film g2 is anodized, and the anodic oxide film AOF having a film thickness of 1800Å is formed on the scanning signal line GL, the gate electrode GT and the electrode PL1.

Step D, FIG. 14 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a nitrided Si film having a film thickness of 2000 Å, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus. After forming an i-type amorphous Si film having a thickness of 2000Å, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N (+)-type amorphous Si film having a film thickness of 300Å.

Step E, FIG. 14 After photo processing, SF ₆ and CC are used as dry etching gas.
Use l ₄ N (+) type amorphous Si film, i-type amorphous Si
The island of the i-type semiconductor layer AS is formed by selectively etching the film.

Step F, FIG. 14 After the photographic process, SF ₆ is used as a dry etching gas to selectively etch the Si nitride film.

Step G, FIG. 15 A first conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layers of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form.

Step H, FIG. 15: A second conductive film d2 made of Cr and having a film thickness of 600 Å is provided by sputtering.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as the process B, and the second conductive film d2 is etched with the same liquid as the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do. Next, by introducing CCl ₄ and SF ₆ into the dry etching apparatus, N (+) type amorphous S
By etching the i film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG. 15 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a Si nitride film having a thickness of 1 μm. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo-etching technique using SF ₆ as a dry etching gas.

<< Overall Structure of Liquid Crystal Display Module >> FIG.
[Fig. 3] is an exploded perspective view showing each component of the liquid crystal display module MDL.

SHD is a frame-shaped shield case (metal frame) made of a metal plate, and LCW is a shield case SH.
D display window, PNL liquid crystal display panel, SPB light diffusion plate, MFR intermediate frame, BL backlight, BL
S is the backlight support, LCA is the lower case,
The modules MDL are assembled by stacking the respective members in a vertical arrangement relationship as shown in the figure.

The module MDL is a shield case SH.
The whole is fixed by the claw CL and the hook FK provided on D.

The intermediate frame MFR is formed in a frame shape so that an opening corresponding to the display window LCW is provided, and the frame portion has a diffusion plate SPB, a backlight support BLS, and various circuit components in accordance with their shapes and thicknesses. There are irregularities and openings for heat dissipation.

The lower case LCA also serves as a reflector of backlight light, and a reflection mountain RM is formed corresponding to the backlight (fluorescent tube) BL so as to efficiently reflect light.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 17 is a top view showing a state in which the video signal drive circuits He and Ho and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.

CHI is a driving integrated circuit chip for driving the display panel PNL (three lower chips are driving integrated circuit chips on the vertical scanning circuit V side, and six left and right devices are driving integrated circuits for the video signal driving circuits He and Ho). Circuit chip). TCP is a drive integrated circuit chip C as will be described later with reference to FIGS.
HI uses tape automated bonding method (T
Tape carrier package mounted by AB), P
CB1 is a drive circuit board on which a tape carrier package TCP, a capacitor CDS, etc. are mounted.
CB1 is divided into three. FGP is a frame ground pad, and the frame ground pad FGP is soldered with a spring-like fragment FG provided by cutting into the shield case SHD. FC is the lower drive circuit board P
It is a flat cable that electrically connects CB1 and the left drive circuit board PCB1 and electrically connects the lower drive circuit board PCB1 and the right drive circuit board PCB1. As the flat cable FC, as shown in the figure, a plurality of lead wires (phosphor bronze material plated with Sn) sandwiched between a striped polyethylene layer and a polyvinyl alcohol layer are used.

<< Connection Structure of Tape Carrier Package TCP >> FIG. 18 is a cross section of a tape carrier package TCP in which an integrated circuit chip CHI, which constitutes the scanning signal drive circuit V and the video signal drive circuits He and Ho, is mounted on a flexible wiring board. FIG. 19 is a diagram showing the structure, and FIG. 19 is a cross-sectional view of essential parts showing a state where it is connected to a drain terminal DTM of a liquid crystal display panel, in this example, a video signal circuit.

In the figure, TTB is an integrated circuit chip C.
HI is an input terminal / wiring portion, and TTM is an output terminal / wiring portion of the integrated circuit chip CHI, which is made of, for example, Cu and has inner end portions (commonly called inner leads).
Is the bonding pad PAD of the integrated circuit chip CHI
Are connected by a so-called face-down bonding method. Outer end portions (commonly called outer leads) of the terminals TTB and TTM respectively correspond to the input and output of the semiconductor integrated circuit chip CHI, and are soldered or the like to the CRT / TF.
The T conversion circuit / power supply circuit SUP is connected to the liquid crystal display panel PNL by an anisotropic conductive film ACF. The tape carrier package TCP is connected to the panel so that its tip portion covers the protective film PSV1 exposing the drain terminal DTM on the panel PNL side. Therefore, the external connection terminal DTM (GTM) is the protective film PSV1 or the tape carrier package. Since it is covered on at least one side of TCP, it is strong against electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it will not stick to unnecessary places during soldering. Transparent glass substrate SU outside the seal pattern SL
The gap between B1 and SUB2 is protected by an epoxy resin EPX or the like after cleaning, and a silicone resin SIL is further filled between the tape carrier package TCP and the upper transparent glass substrate SUB2 for multiple protection.

<< Drive Circuit Board PCB2 >> Intermediate Frame M
As shown in FIG. 20, the drive circuit board PCB2 of the liquid crystal display unit LCD which is held / stored in the FR has an L shape, and has electronic components such as ICs, capacitors, and resistors mounted thereon. This drive circuit board PCB2 is provided with a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (upper processing unit). A circuit SUP including a circuit for converting into information for a TFT liquid crystal display device is mounted. CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected. The drive circuit board PCB2 and the inverter circuit board PCB3 are electrically connected by a backlight cable through a connector hole provided in the intermediate frame MFR.

Drive circuit board PCB1 and drive circuit board PC
B2 is electrically connected by a foldable flat cable FC. When assembled, drive circuit board PCB
2 is overlapped on the back side of the drive circuit board PCB1 by bending the flat cable FC by 180 ° and fitted into a predetermined recess of the intermediate frame MFR.

FIG. 21 shows another active circuit according to the present invention.
22 is a plan view showing a thin film transistor portion of a matrix type liquid crystal display device, and FIG. 22 is a sectional view showing the thin film transistor portion shown in FIG. As shown in the figure, the source electrode S
First located above D1 and below orientation film ORI1
Is provided, and the second light shielding film LSF2 located above the drain electrode SD2 and below the alignment film ORI1 is provided.

In this liquid crystal display device, the light shielding film LS
Since light can be prevented from reaching the i-type semiconductor layer AS by the F1 and LSF2, uneven brightness or the like will not occur, and the light will be above the source electrode SD1 and the drain electrode SD2 and below the alignment film ORI1. Since there is no light-shielding film located, the coupling capacitance Csd between the source electrode SD1 and the drain electrode SD2 does not increase, and a malfunction called smear does not occur.
The display quality is good.

FIG. 23 shows another active circuit according to the present invention.
FIG. 6 is a plan view showing a thin film transistor portion of a matrix type liquid crystal display device. In this liquid crystal display device, since the light-shielding film LSF1 is provided, there is no malfunction such as uneven brightness, and no malfunction called smear occurs, so that the display quality is good.

FIG. 24 shows another active circuit according to the present invention.
FIG. 6 is a plan view showing a thin film transistor portion of a matrix type liquid crystal display device. In this liquid crystal display device, the end portions in the channel width direction of the source electrode SD1 and the drain electrode SD2 are located outside the end portions in the channel width direction of the i-type semiconductor layer AS, and moreover, the light shielding films LSF1 and LSF2.
Since there is no malfunction such as brightness unevenness and no malfunction called smear, the display quality is good.

[0099]

As described above, in the liquid crystal display device according to the present invention, there are no malfunctions such as uneven brightness and no malfunctions called smear.
The display quality is good. As described above, the effect of the present invention is remarkable.

[Brief description of drawings]

FIG. 1 is a plan view showing a thin film transistor portion of the liquid crystal display device shown in FIG.

FIG. 2 is a main-portion plan view showing one pixel and its periphery of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied.

FIG. 3 is a cross-sectional view showing one pixel and its periphery taken along the section line 3-3 in FIG.

FIG. 4 is a retention capacitance element Cad taken along section line 4-4 of FIG.
It is a sectional view of d.

FIG. 5 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel.

FIG. 6 is a panel plan view for exaggerating the peripheral portion of FIG. 5 and explaining it more specifically.

FIG. 7 is an enlarged plan view of a corner portion of a display panel including electrical connection portions of upper and lower substrates.

FIG. 8 is a cross-sectional view showing the vicinity of a panel angle and the vicinity of a video signal terminal portion on both sides, with the pixel portion of the matrix at the center.

FIG. 9 shows a panel edge portion having a gate terminal on the left side,
It is sectional drawing which shows the panel edge part without an external connection terminal on the right side.

FIG. 10 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a scanning signal line GL.

FIG. 11 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 12 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device.

FIG. 13: Processes A to C on the lower transparent glass substrate SUB1 side
6 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing the manufacturing process of FIG.

FIG. 14: Processes D to F on the lower transparent glass substrate SUB1 side
6 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing the manufacturing process of FIG.

FIG. 15: Processes G to I on the lower transparent glass substrate SUB1 side
6 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing the manufacturing process of FIG.

FIG. 16 is an exploded perspective view of a liquid crystal display module.

FIG. 17 is a top view showing a state in which a peripheral drive circuit is mounted on a liquid crystal display panel.

FIG. 18 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI forming a drive circuit is mounted on a flexible wiring board.

FIG. 19 is a cross-sectional view of essential parts showing a state in which the tape carrier package TCP is connected to the video signal circuit terminal DTM of the liquid crystal display panel PNL.

FIG. 20: Peripheral drive circuit board PCB1 (top surface visible)
It is a top view which shows the connection state of power supply circuit circuit board PCB2 (a lower surface is visible).

FIG. 21 is a plan view showing a thin film transistor portion of another active matrix type liquid crystal display device according to the present invention.

22 is a cross-sectional view showing a thin film transistor part shown in FIG.

FIG. 23 is a plan view showing a thin film transistor portion of another active matrix type liquid crystal display device according to the present invention.

FIG. 24 is a plan view showing a thin film transistor portion of another active matrix type liquid crystal display device according to the present invention.

FIG. 25 is a plan view showing a thin film transistor portion of a conventional active matrix type liquid crystal display device.

FIG. 26 is a cross-sectional view showing a thin film transistor portion shown in FIG.

FIG. 27 is a plan view showing a thin film transistor portion of another conventional active matrix type liquid crystal display device.

28 is a cross-sectional view showing the thin film transistor portion shown in FIG. 27.

29 is an equivalent circuit diagram of the pixel shown in FIGS. 27 and 28. FIG.

[Explanation of symbols]

SUB ... Transparent glass substrate, GL ... Scan signal line, DL ... Video signal line GI ... Insulating film, GT ... Gate electrode, AS ... i-type semiconductor layer SD ... Source electrode or drain electrode, PSV ... Protective film, BM ... Light-shielding film LC ... Liquid crystal, TFT ... Thin film transistor, ITO ... Transparent pixel electrode g, d ... Conductive film, Cadd ... Storage capacitor element, AOF ... Anodized film AO ... Anodized mask pattern, GTM ... Gate terminal,
DTM ... drain terminal SHD ... shield case, PNL ... liquid crystal display panel, S
PB ... Light diffusion plate MFR ... Intermediate frame, BL ... Backlight, BLS ...
Backlight support LCA ... Lower case, RM ... Backlight light reflection mountain, L
SF ... Shading film (subscripts omitted above).

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hironori Kondo 3300 Hayano, Mobara, Chiba Prefecture Electronic Device Division, Hitachi, Ltd. (72) Inventor Katsuhiko Yuchida 3300 Hayano, Mobara, Chiba Hitachi Electronic Devices Co., Ltd. (72) Inventor Kuniyuki Matsunaga 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Devices Division

Claims (2)

[Claims] 1. A liquid crystal display device having a thin film transistor, characterized in that the source electrode and the drain electrode of the thin film transistor are located at the outer ends of the semiconductor layer in the channel width direction. Liquid crystal display device. 2. A liquid crystal display device having a thin film transistor, wherein a first light shielding film is located above the source electrode of the thin film transistor and below the alignment film, above the drain electrode of the thin film transistor and below the alignment film. A liquid crystal display device, wherein at least one of the second light-shielding films located is provided.