JPH05232494A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To suppress the generation of electric corrosion by covering an external connecting terminals with at least either of a protective film or base film. CONSTITUTION:The Al pattern position of a terminal leading-out part is confined within a sealing pattern SL and the protective film PSV 1 is extended up to TCPF to cover the terminal leading-out part. Namely, the front ends on the outer side of the terminals TTM respectively correspond to the input and output of a semiconductor integrated circuit chip and are connected by soldering, etc., to a CRT/TFT conversion circuit and power source circuit and by an anisotropic conductive film ACF to a liquid crystal display panel. A package TCP is so connected to the panel that the front end thereof covers the protective film PSV 1 exposing the connecting terminals DTM on the panel side. Then, the external connecting terminal DTM (GTM) is coated with at least either of the protective film PSV 1 or the package TCP and is, therefore, strong to the electric corrosion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device using thin film transistors.

[0002]

2. Description of the Related Art An active matrix liquid crystal display device using a thin film transistor is disclosed in, for example, Japanese Patent Laid-Open No. 63-30.
It is known from Japanese Patent Publication No. 9921.

An active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. The liquid crystal is sealed and sealed in the gap between the upper and lower substrates to form an integrated cell. In the module assembling process, the anisotropic conductive film ACF is used to connect the cell side terminal and the tape carrier package TCP side terminal. Conventionally, the aluminum pattern is used for ultrasonic cleaning after assembling into an integrated cell and terminal cleaning work before TCP crimping in the module assembly process.
There was a problem that the protective film (PSV1) on the screen peeled off. It was found that this peeling of the protective film causes electrolytic corrosion between terminals after the high temperature and high humidity test. Further, if there is a portion where the conductor pattern is exposed between the protective film and the TAB, the epoxy resin E
It was found that the application of PX or the silicone resin SIL was not sufficient in terms of reliability, and caused electrolytic corrosion between terminals. Therefore, it is necessary to specify the Al pattern position and the protective film position of the terminal lead portion.

Further, since the video signal or the digital signal is constantly input to the signal line side and the duty is high,
Better reliability design is needed. Even in the high-temperature and high-humidity test results, the signal line side was often electrolyzed first, and the scanning line side was not abnormal in many cases. Therefore, the present invention is particularly effective on the signal line side.

[0005]

SUMMARY OF THE INVENTION One object of the present invention is to provide a highly reliable liquid crystal display device.

Another object of the present invention is to provide a liquid crystal display device capable of preventing the electrical corrosion between terminals after the high-temperature and high-humidity test, which becomes more conspicuous, because the terminal pitch becomes smaller as the definition becomes higher. It is to be.

[0007]

According to one embodiment of the present invention, in a liquid crystal display device in which a terminal is connected to a video signal line through an oblique wiring, the Al pattern position of the terminal lead-out portion is a see-through position. A liquid crystal display device is provided in which the protective film PSV1 is extended to the bottom of the TCP and is covered in the pattern SL, and the terminal lead portion is covered.

[0008]

According to such a liquid crystal display device, even if mechanical stress is applied in the liquid crystal assembling process or the module process, peeling is prevented because the Al material and the protective film, which have weak adhesion, are present in the seal. In addition, since all the lead-out wiring is covered with the protective film, there is no exposed conductor pattern, it is difficult to directly contact the outside air, and the high temperature and high humidity test reliability is good.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS The invention, further objects of the invention and further features of the invention will become apparent from the following description with reference to the drawings.

(Active matrix liquid crystal display device)
An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

(Outline of Matrix Section) FIG. 1 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device to which the present invention is applied, and FIG.
2 is a view showing a cross section taken along the line -2, and FIG. 3 is 3-3 in FIG.
It is sectional drawing in a cutting line. Further, FIG. 4 shows a plan view when a plurality of pixels shown in FIG. 1 are arranged.

As shown in FIG. 1, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL.
And an adjacent two video signal lines (drain signal lines or vertical signal lines) DL intersect with each other (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction and a plurality of video signal lines DL are arranged in the column direction.

As shown in FIG. 2, a thin film transistor TFT is provided on the lower transparent glass substrate SUB1 side based on the liquid crystal LC.
The transparent pixel electrode ITO1 is formed, and the color filter FIL and the light-shielding black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 mm. In addition, the transparent glass substrates SUB1 and S
A silicon oxide film SIO formed by dipping or the like is provided on both surfaces of the UB2. Therefore, even if there are sharp scratches on the surfaces of the transparent glass substrates SUB1 and SUB2, the sharp scratches can be covered with the silicon oxide film SIO, and the scanning signal line G deposited on the scratches can be covered.
The film quality of L, the light shielding film BM, etc. can be kept uniform.

On the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2, a light shielding film BM and a color filter FI are provided.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

(Outline of Matrix Periphery) FIG. 16 shows a display panel PNL including upper and lower glass substrates SUB1 and SUB2.
17 is a plane in which a peripheral portion of the matrix (AR) is exaggerated, FIG.
7 is a diagram showing an enlarged plane near the seal portion SL corresponding to the upper left corner of the panel of FIG. Further, FIG. 19 is a diagram showing a cross section taken along a cutting line 19a-19a in FIG. 18 on the left side and a cross section near the external connection terminal DTM to which the video signal driving circuit is to be connected, on the right side, with the cross section of FIG. 2 as the center. is there. Similarly, FIG.
0 is an external connection terminal G to which the scanning circuit should be connected on the left side
It is a figure which shows the cross section near TM, and the cross section near the seal part where there is no external connection terminal on the right side.

[0016] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared In each product type, a glass substrate of standardized size is processed and then reduced to a size suitable for each product type. In each case, the glass is cut after one step. 16 to 18 show an example of the latter case. In both of FIGS. 16 and 17, the upper and lower substrates SUB are shown.
18 shows the state after the cutting of the substrates 1 and SUB2, and FIG. 18 shows the state before the cutting, LN indicates the edges of the both substrates before the cutting, and CT1 and CT2 indicate the positions of the substrates SUB1 and SUB2 to be cut, respectively. In either case, in the completed state, the external connection terminal group T
g and Td (subscripts omitted) exist (upper and lower sides in the figure)
The upper substrate SUB2 is limited in size to the inside of the lower substrate SUB1 so as to expose them. The terminal groups Tg and Td are respectively a scanning circuit connecting terminal GTM, a video signal circuit connecting terminal DTM, which will be described later, and lead-out wiring parts thereof of a tape carrier package TCP (FIG. 20, FIG. 21) on which an integrated circuit chip CHI is mounted. It is named after a plurality of units. The lead wiring from the matrix portion of each group to the external connection terminal portion is inclined toward both ends. This is to match the terminals DTM and GTM of the display panel PNL with the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP.

A liquid crystal LC is provided between the transparent glass substrates SUB1 and SUB2 along the edge thereof except for the liquid crystal inlet INJ.
A seal pattern SL is formed so as to seal the. The sealing material is made of epoxy resin, for example. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to at least one of the lead wirings INT formed on the lower transparent glass substrate SUB1 side by the silver paste material AGP at four corners of the panel in this embodiment. ing. The lead wiring INT is formed in the same manufacturing process as a gate terminal GTM and a drain terminal DTM described later.

The alignment layers ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2, and the respective layers are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are lower transparent glass substrates SUB, respectively.
1. Formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is enclosed in a region partitioned by a seal pattern SL between a lower alignment film ORI1 and an upper alignment film ORI2 that set the orientation of liquid crystal molecules. The lower alignment film ORI1 is a protective film P on the lower transparent glass substrate SUB1 side.
It is formed on top of SV1.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and the seal pattern SL is provided on the substrate SUB2.
Formed on the side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, the liquid crystal LC is injected from the opening INJ of the sealing material SL, and the injection port INJ is sealed with epoxy resin or the like to form the upper and lower substrates. It is assembled by cutting.

(Thin Film Transistor TFT) The thin film transistor TFT operates so that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain becomes small, and when the bias is zero, the channel resistance becomes large.

The thin film transistor TFT of each pixel is divided into two (plural) within the pixel, and is composed of thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 is an i-type semiconductor made of a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic, intrinsic, conductivity type determination impurity-free) amorphous silicon (Si). It has a layer AS, a pair of source electrodes SD1 and a pair of drain electrodes SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

(Gate Electrode GT) The gate electrode GT is shown in FIG.
As shown in (plan view in which only the second conductive film g2 and the i-type semiconductor layer AS in FIG. 1 are drawn), it is formed in a shape projecting in the vertical direction (upward in FIGS. 1 and 5) from the scanning signal line GL. (T-shaped branch). The gate electrode GT projects so as to extend beyond the active regions of the thin film transistors TFT1 and TFT2. Gate electrodes G of the thin film transistors TFT1 and TFT2
T is formed integrally (as a common gate electrode) and is formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of the single-layer second conductive film g2. The second conductive film g2 is, for example, an aluminum (Al) film formed by sputtering, and is 1000 to 550.
It is formed with a film thickness of about 0Å. An Al anodic oxide film AOF is provided on the gate electrode GT.

As shown in FIGS. 1, 2 and 5, the gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below).
Therefore, when a backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque Al becomes a shadow and the i-type semiconductor layer AS is not exposed to the backlight light. The conduction phenomenon due to the light irradiation, that is, the deterioration of the off-characteristics of the thin film transistor TFT is less likely to occur. The original size of the gate electrode GT is the minimum required to extend between the source electrode SD1 and the drain electrode SD2 (including the alignment margin between the gate electrode GT, the source electrode SD1 and the drain electrode SD2). ) Has a width and its depth length that determines the channel width W is the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W / L that determines the mutual conductance gm. It depends on what you do. Gate electrode G in this liquid crystal display device
The size of T is, of course, larger than the original size described above.

(Scanning Signal Line GL) The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. Further, an Al anodic oxide film AOF is also provided on the scanning signal line GL.

(Insulating Film GI) The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 and TFT2. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. The insulating film GI is, for example, a silicon nitride film formed by plasma CVD, and is formed with a film thickness of 1200 to 2700Å (in this liquid crystal display device, a film thickness of about 2000Å). As shown in FIG. 18, the gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion has external connection terminals DTM and G.
Removed to expose TM.

(I-type semiconductor layer AS) i-type semiconductor layer AS
Is used as a channel forming region of each of the thin film transistors TFT1 and TFT2 divided into a plurality of parts, as shown in FIG. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of 200-2200.
It is formed with a film thickness of Å (a film thickness of about 2000 Å in this liquid crystal display device).

The i-type semiconductor layer AS is continuously formed by the same plasma CVD apparatus and plasma in the same manner as the formation of the insulating film GI used as a gate insulating film made of Si ₃ N ₄ by changing the composition of the supply gas. It is formed without being exposed to the outside from the CVD device. Further, phosphorus (P) for ohmic contact is doped with 2.5% of N (+) type semiconductor layer d.
0 (FIG. 2) is similarly continuously formed with a film thickness of 200 to 500 Å (in this liquid crystal display device, a film thickness of about 300 Å). After that, the lower transparent glass substrate SUB1 is CV
It is taken out from the D device and is N (+) by the photo processing technology.
The type semiconductor layer d0 and the i-type semiconductor layer AS are patterned into independent islands as shown in FIGS. 1, 2 and 5.

As shown in FIGS. 1 and 5, the i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

(Transparent Pixel Electrode ITO1) Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T1.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by laser light or the like, and if not, the other thin film transistor operates normally. You can leave it as it is. It is rare that defects occur simultaneously in the two thin film transistors TFT1 and TFT2, and the probability of point defects and line defects can be extremely reduced by such a redundancy system. Transparent pixel electrode ITO
1 is composed of a first conductive film d1.
The conductive film d1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering.
A film thickness of 00 to 2000Å (in this liquid crystal display device, 14
It is formed with a film thickness of about 00Å).

(Source electrode SD1, drain electrode SD
2) Thin film transistors TFT1, TF divided into a plurality of parts
Source electrode SD1 and drain electrode SD of T2
2 is provided separately from each other on the i-type semiconductor layer AS as shown in FIGS. 1, 2 and 6 (a plan view showing only the first to third conductive films d1 to d3 of FIG. 1). Has been.

Each of the source electrode SD1 and the drain electrode SD2 is formed by sequentially superposing a second conductive film d2 and a third conductive film d3 from the lower layer side in contact with the N (+) type semiconductor layer d0. Second conductive film d2 of the source electrode SD1
The third conductive film d3 is formed in the same manufacturing process as the second conductive film d2 and the third conductive film d3 of the drain electrode SD2.

The second conductive film d2 is a chromium (Cr) film formed by sputtering and is formed to have a film thickness of 500 to 1000 Å (in this liquid crystal display device, a film thickness of about 600 Å).
Since the stress increases when the Cr film is formed thicker, the Cr film is formed within a range of about 2000Å or less.
The Cr film has good contact with the N (+) type semiconductor layer d0.
The Cr film constitutes a so-called barrier layer that prevents Al of the third conductive film d3 described later from diffusing into the N (+) type semiconductor layer d0. As the second conductive film d2, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used instead of the Cr film.

The third conductive film d3 is formed by sputtering Al and has a thickness of 3000 to 5000 Å (in this liquid crystal display device,
The film thickness is about 4000 Å). The Al film has less stress than the Cr film, can be formed to have a thick film thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. As the third conductive film d3, an Al film containing silicon or copper (Cu) as an additive may be used instead of the pure Al film.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, an N (+) type film is formed by using the same mask or by using the second conductive film d2 and the third conductive film d3 as a mask. The semiconductor layer d0 is removed. That is,
The N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so that the entire thickness thereof is removed, the surface portion of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

The source electrode SD1 is a transparent pixel electrode ITO1
It is connected to the. The source electrode SD1 has the i-type semiconductor layer AS step (thickness of the second conductive film g2, thickness of the anodic oxide film AOF, thickness of the i-type semiconductor layer AS, and thickness of the N (+)-type semiconductor layer d0. It is configured along a step corresponding to the added film thickness). Specifically, the source electrode SD1 is the second conductive film d2 formed along the step of the i-type semiconductor layer AS.
And the third conductive film d formed on the second conductive film d2.
3 and 3. The third conductive film d3 of the source electrode SD1 cannot be formed thick due to the increased stress of the Cr film of the second conductive film d2, and cannot overcome the step shape of the i-type semiconductor layer AS. Is configured for. That is, the step coverage is improved by forming the third conductive film d3 thick. Since the third conductive film d3 can be formed thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).

(Protective film PSV1) Thin film transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

As shown in FIG. 18, the protective film PSV1 is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM.
In addition, the common electrode COM of the upper substrate SUB2 is connected to the lower substrate SU.
The portion connected to the lead wire INT for connecting the external connection terminal of B1 with the silver paste AGP is also removed. Protective film PSV
Regarding the thickness relationship between 1 and the gate insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thin in the transconductance gm of the transistor. Therefore, as shown in FIG. 18, the protective film PSV1 having a high protective effect is formed to be larger than the gate insulating film GI so as to protect the peripheral portion over as wide a range as possible.

(Light-shielding film BM) Upper transparent glass substrate SUB
A light-shielding film BM is provided on the second side so that external light (light from above in FIG. 2) does not enter the i-type semiconductor layer AS used as a channel formation region.
The pattern is as shown by the hatching. Note that FIG. 7 shows the first conductive film d made of the ITO film in FIG.
FIG. 1 is a plan view illustrating only a color filter FIL and a light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chrome film having a high light-shielding property, and in this liquid crystal display device, the chrome film is formed by sputtering to a film thickness of about 1300 Å.

Therefore, the thin film transistors TFT1 and TF
The i-type semiconductor layer AS of T2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT,
That part is not exposed to external natural light or backlight. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. 7, that is, the light-shielding film BM is formed in a grid shape (black matrix), and the effective display area of one pixel is partitioned by this grid. .. Therefore, the contour of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

A portion facing the edge portion of the transparent pixel electrode ITO1 on the base side in the rubbing direction (lower right portion in FIG. 1).
Since the light is shielded by the light shielding film BM, even if a domain is generated in the above portion, the domain cannot be seen, so that the display characteristics are not deteriorated.

The backlight may be attached to the upper transparent glass substrate SUB2 side and the lower transparent glass substrate SUB1 may be the observation side (externally exposed side).

The light-shielding film BM is also formed on the peripheral portion in a frame-shaped pattern as shown in FIG. 17, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. Has been done. As shown in FIGS. 17 to 20, the light shielding film BM in the peripheral portion is extended to the outside of the seal portion SL to prevent leaked light such as reflected light caused by a mounting machine such as a personal computer from entering the matrix portion. .. On the other hand, this light-shielding film BM is about 0.3-1.
It is held inside by about 0 mm and formed so as to avoid the cutting region of the substrate SUB2.

(Color Filter FIL) The color filter FIL is constructed by coloring a dye base material made of a resin material such as acrylic resin with a dye. Color filter F
ILs are formed in stripes at positions facing the pixels (FIG. 8) and are dyed separately (FIG. 8 shows only the first conductive film d1, the light shielding film BM and the color filter FIL in FIG. B, R, G color filters FI
L is 45 °, 135 °, and has a cross hatch). As shown in FIGS. 7 and 9, the color filter FIL is formed to have a large size so as to cover the entire transparent pixel electrode ITO1, and the light-shielding film BM of the transparent pixel electrode ITO1 overlaps the edge portions of the color filter FIL and the transparent pixel electrode ITO1. It is formed inside the peripheral portion.

The color filter FIL can be formed as follows. First, a dyeing base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

(Protective Film PSV2) In the protective film PSV2, the liquid crystal L is a dye in which the color filter FIL is dyed in different colors.
It is provided to prevent leakage to C. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

(Common Transparent Pixel Electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. In this embodiment, the common voltage Vcom is the low level drive voltage Vdmin and the high level drive voltage V applied to the video signal line DL.
Although it is set to an intermediate potential with respect to dmax, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal drive circuit to about half, an AC voltage may be applied. For the planar shape of the common transparent pixel electrode ITO2, see FIGS. 17 and 18.

(Gate Terminal) FIG. 9 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM. (A) is a plane and (B) is B of (A). -B shows a cross section taken along the line B. Note that the same drawing corresponds to the lower part of FIG. 18, and the diagonal wiring portions are shown in a straight line for convenience.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but since the oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view, its locus remains. In the plan view, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized. Anodized A
The oxide Al ₂ O ₃ film AOF is formed on the surface of the L layer g2, and the volume of the lower conductive portion is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. The mask pattern AO does not intersect with the scanning line GL by a single straight line, but is bent in a crank shape and intersects.

In the figure, the AL layer g2 is hatched for easy understanding, but the region which is not anodized is patterned in a comb shape. This is because whiskers are generated on the surface when the width of the Al layer is wide. Therefore, by narrowing the width of each one and arranging a plurality of them in parallel, whiskers can be prevented from occurring and wire breakage can be prevented. The aim is to minimize the probability of and the sacrifice of conductivity. Therefore, in this example, the portion corresponding to the base of the comb is also displaced along the mask AO.

The gate terminal GTM has a Cr layer g1 having a good adhesiveness to the silicon oxide SIO layer and a higher electric contact resistance than Al or the like,
Further, the surface thereof is protected and is composed of the pixel electrode ITO1 and the transparent conductive layer d1 of the same level (same layer, simultaneously formed).
In addition, the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof have their regions so that the conductive layers g2 and g1 are not etched together due to pinholes or the like during the etching of the conductive layers d3 and d2. It remains as a result of being covered with photoresist. Further, the ITO layer d1 which extends over the gate insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located at the left end is formed.
Are exposed from them to allow electrical contact with external circuitry. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, a plurality of such pairs are arranged vertically as shown in FIG.
(FIGS. 17 and 18), and the left end of the gate terminal is
In the manufacturing process, it extends beyond the cutting region CT1 of the substrate and is short-circuited by the wiring SHg. Such a short-circuit line SHg in the manufacturing process is used for power supply during anodization and for the orientation film OR.
Useful for preventing electrostatic damage during I1 rubbing.

(Drain Terminal DTM) FIG. 10 is a diagram showing the connection from the video signal line DL to the external connection terminal DTM, (A) shows the plane, and (B) shows B of (A).
-B shows a cross section taken along the line B. The drawing corresponds to the vicinity of the upper right of FIG. 18, and although the orientation of the drawing is changed for convenience, the right end direction corresponds to the upper end portion (or the lower end portion) of the substrate SUB1.

TSTd is an inspection terminal, which is not connected to an external circuit, but is wider than the wiring portion so that a probe needle or the like can come into contact therewith. Similarly, the drain terminal D
The width of the TM is also wider than that of the wiring portion so that the TM can be connected to an external circuit. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the substrate SUB1 as shown in the figure, but the drain terminal DTM.
Is a terminal group Td (subscript omitted) as shown in FIG. 18, and is further extended beyond the cutting line CT1 of the substrate SUB1.
During the manufacturing process, all of them are short-circuited to each other by the wiring SHd to prevent electrostatic breakdown. The drain connection terminal is connected to the opposite side of the matrix of the video signal lines DL in which the inspection terminal TSTd exists, and conversely, the drain connection terminal DTM.
The inspection terminal is connected to the opposite side of the matrix of the video signal lines DL in which there is a line.

The drain connection terminal DTM has the Cr layer g1 and the ITO layer d1 for the same reason as the above-mentioned gate terminal GTM.
And is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. The protective film PSV1 is, of course, removed on the terminal DTM to connect to the external circuit. AO is the anodizing mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side of the boundary line is covered with the mask. This pattern is not directly relevant as it does not exist.

The lead-out wiring from the matrix portion to the drain terminal portion DTM is as shown in FIG.
The layers d2 and d3 having the same level as the video signal line DL are laminated just above the layers d1 and g1 having the same level as the drain terminal portion DTM to the middle of the seal pattern SL, but this is the probability of disconnection. Is to be minimized, and the Al layer d3, which is easily touched with electricity, is protected as much as possible by the protective film PSV1 and the seal pattern SL.

(Structure of Storage Capacitance Element Cadd) The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. This overlay is shown in Figure 1.
As is clear from FIG. 3, a holding capacitance element (electrostatic capacitance element) Cadd having the transparent pixel electrode ITO1 as one electrode PL2 and the adjacent scanning signal line GL as the other electrode PL1 is formed. The dielectric film of the storage capacitor element Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodized film AOF.

As is apparent from FIG. 5, the storage capacitor element Cadd is formed in a portion where the width of the second conductive film g2 of the scanning signal line GL is widened. The second conductive film g2 at the portion intersecting the video signal line DL is thinned in order to reduce the probability of short circuit with the video signal line DL.

Even if the transparent pixel electrode ITO1 is broken at the step portion of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d2 formed so as to cross the step.
The defect is compensated by the island region formed of the conductive film d3.

(Equivalent Circuit of Entire Display Device) FIG. 11 shows a wiring diagram of the equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device that displays information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) to obtain a plurality of divided and stabilized voltage sources from one voltage source. It is a circuit including a circuit for exchanging information for use.

(Equivalent circuit of holding capacitance element Cadd and its operation) FIG. 12 shows an equivalent circuit of the pixel shown in FIG. In FIG. 12, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film having the parasitic capacitance Cgs is the insulating film GI and the anodic oxide film AOF. Cpix is a transparent pixel electrode ITO
A liquid crystal capacitor formed between 1 (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitance Cpix is the liquid crystal LC, the protective film PSV1 and the alignment film ORI.
1 and ORI2. Vlc is the midpoint potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This can be expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔVlc represents a change amount of the midpoint potential due to ΔVg. This variation ΔVlc causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the holding capacitance Cadd is increased. In addition, the storage capacitor element C
The add also has the effect of lengthening the discharge time, and accumulates image information for a long time after the thin film transistor TFT is turned off. The reduction of the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large enough to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and thus the parasitic capacitance Cgs is increased. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, this demerit can be eliminated by providing the storage capacitor element Cadd.

The holding capacitance of the holding capacitance element Cadd is 4 to 8 times (4.C
pix <Cadd <8 · Cpix), 8 to 3 for parasitic capacitance Cgs
Set to a value about twice (8 · Cgs <Cadd <32 · Cgs).

(Method of connecting the storage capacitor element Cadd electrode wire)
As shown in FIG. 11, the scanning signal line GL (Y ₀ ) in the first stage, which is used only as the storage capacitor electrode line, has the same potential as the common transparent pixel electrode ITO2 (Vcom). In the example of FIG. 18, the scanning signal line at the first stage is short-circuited to the common electrode COM through the terminal GT0, the lead wire INT, the terminal DT0 and the external wiring. Alternatively, the first-stage storage capacitor electrode line Y ₀ is connected to the final-stage scanning signal line Yend, is connected to a DC potential point (AC ground point) other than Vcom, or one extra scanning pulse Y ₀ from the vertical scanning circuit V. You may connect to receive.

(Connection Structure with External Circuit) FIG. 21 shows an integrated circuit chip CHI, which constitutes the scanning signal drive circuit V and the video signal drive circuits He and Ho, mounted on a flexible wiring board (commonly called TAB, Tape Automated Bonding). FIG. 23 is a view showing a cross-sectional structure of the tape carrier package TCP, and FIG. 22 is a main-portion cross-sectional view showing a state where the tape carrier package TCP is connected to the liquid crystal display panel, in this example, the video signal circuit terminal DTM.

In the figure, TTB is an input terminal / wiring part of the integrated circuit CHI, and TTM is an output terminal / wiring part of the integrated circuit CHI, which is made of, for example, Cu and has inner ends (commonly called inner leads). ) Is the integrated circuit C
The HI bonding pad PAD is connected by a so-called face-down bonding method. Terminals TTB, T
Outer end portions (commonly called outer leads) of TM correspond to the input and output of the semiconductor integrated circuit chip CHI,
CRT / TFT conversion circuit / power supply circuit S by soldering, etc.
A liquid crystal display panel P is formed on the UP by an anisotropic conductive film ACF.
Connected to NL. The package TCP has a protective film PS whose front end exposes the connection terminal DTM on the panel PNL side.
Since it is connected to the panel so as to cover V1, and therefore the external connection terminal DTM (GTM) is covered with at least one of the protective film PSV1 and the package TCP, it is strong against electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it will not stick to unnecessary places during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by epoxy resin EPX or the like after cleaning, and a silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to provide multiple protection.

(Manufacturing Method) Next, a manufacturing method of the substrate SUB1 side of the above-described liquid crystal display device will be described with reference to FIGS.
Will be described. In the figure, the letters in the center are abbreviations of process names, the left side shows the pixel portion shown in FIG. 2, and the right side shows the processing flow as seen in the sectional shape near the gate terminal shown in FIG. Except for the step D, steps A to I are divided corresponding to each photographic process, and all the cross-sectional views of each process show the stage where the processing after the photographic process is completed and the photoresist is removed. In this description, the photographic processing means a series of operations from the application of the photoresist to the selective exposure using the mask to the development thereof, and the repetitive description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 13 A silicon oxide film SIO is formed on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dip processing, and then baked at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a cerium ammonium nitrate solution as an etching solution. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line SHg connecting the gate terminal GTM, the bus line SHd shorting the drain terminal DTM, and the anodized pad connected to the anodized bus line SHg (not shown). To form.

Step B, FIG. 13 Al-Pd, Al-Si, Al-S having a film thickness of 2800Å
The second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Are provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step C, FIG. 13 After photographic processing (after forming the above-described anodic oxidation mask AO), 3
Substrate SUB1 is immersed in an anodizing solution consisting of a solution of% tartaric acid adjusted to pH 6.25 ± 0.05 with ammonia and diluted 1: 9 with ethylene glycol solution, and the formation current density is 0.5 mA / cm 2. ² so as to adjust (constant current Kasei). Next, anodic oxidation is performed until the formation voltage 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g2 is anodized to form an anodic oxide film AOF having a thickness of 1800Å on the scanning signal line GL, the gate electrode GT and the electrode PL1. Process D, FIG. 14 Ammonia gas, silane gas in plasma CVD apparatus , Nitrogen gas is introduced to form a 2000 Å-thickness Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form a 2000 Å-thick i-type amorphous Si film. Hydrogen gas and phosphine gas are introduced into the CVD apparatus to form an N (+) type amorphous Si film having a film thickness of 300Å.

Step E, FIG. 14 After photo processing, SF ₆ and CC are used as dry etching gas.
Use l ₄ N (+) type amorphous Si film, i-type amorphous Si
The island of the i-type semiconductor layer AS is formed by selectively etching the film.

Step F, FIG. 14 After the photographic process, SF ₆ is used as a dry etching gas to selectively etch the Si nitride film.

Step G, FIG. 15 A first conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layers of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form.

Step H, FIG. 15: A second conductive film d2 made of Cr having a film thickness of 600 Å is provided by sputtering, and an Al- film having a film thickness of 4000 Å is formed.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as the process B, and the second conductive film d2 is etched with the same liquid as the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do. Next, by introducing CCl ₄ and SF ₆ into the dry etching apparatus, N (+) type amorphous S
By etching the i film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG. 15 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a thickness of 1 μm. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo-etching technique using SF ₆ as a dry etching gas.

(Modification) In the above-mentioned embodiment, the protective film PS is used.
V1 is formed over the entire matrix AR, but in the matrix, the protective film PSV1 is formed in a dot shape so as to cover only the transistor portion, or only the pixel electrode ITO1 portion is removed in order to increase the voltage utilization rate. BM
It may be formed in a grid pattern similar to.

[0084]

According to the above-described embodiment of the present invention, since the conductive layer d3 of the lead wiring to the external connection terminal portion DTM containing Al is retained inside the seal portion SL, the external connection terminal DTM, Since GTM is covered with at least one of the protective film PSV1 and the base film BF1, electric contact is less likely to occur.

[Brief description of drawings]

FIG. 1 is a plan view of relevant parts showing one pixel and its periphery of a liquid crystal display section of an active matrix type color liquid crystal display device to which the present invention is applied.

FIG. 2 is a cross-sectional view showing one pixel and its periphery taken along the line 2-2 in FIG.

3 is a cross-sectional view of the additional capacitance Cadd taken along the line 3-3 in FIG.

4 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 1 are arranged.

5 is a plan view illustrating only layers g2 and AS of the pixel shown in FIG.

6 is a plan view illustrating only layers d1, d2 and d3 of the pixel shown in FIG.

7 is a plan view showing only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel shown in FIG.

FIG. 8 is a plan view of a principal part showing only a pixel electrode layer, a light shielding film and a color filter layer of the pixel array shown in FIG.

FIG. 9 is a plan view and a cross-sectional view showing the vicinity of a connecting portion between a gate terminal GTM and a gate wiring GL.

FIG. 10 is a plan view and a cross-sectional view showing the vicinity of a connection between a drain terminal DTM and a video signal line DL.

FIG. 11 is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device.

FIG. 12 is an equivalent circuit diagram of the pixel shown in FIG.

FIG. 13 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side.

FIG. 14 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes D to F on the substrate SUB1 side.

FIG. 15 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps GI on the side of the substrate SUB1.

FIG. 16 is a plan view for explaining a configuration of a matrix peripheral portion of a display panel.

FIG. 17 is a panel plan view for exaggerating the peripheral portion of FIG. 16 and explaining it more specifically.

FIG. 18 is an enlarged plan view of a corner portion of a display panel including electrical connection portions of upper and lower substrates.

FIG. 19 is a cross-sectional view showing the vicinity of a panel angle and the vicinity of a video signal terminal portion on both sides with the pixel portion of the matrix at the center.

FIG. 20 is a cross-sectional view showing a scan signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 21 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI which constitutes a drive circuit is mounted on a flexible wiring board.

FIG. 22 is a cross-sectional view of essential parts showing a state in which the tape carrier package TCP is connected to the video signal circuit terminal DTM of the liquid crystal display panel PNL.

[Explanation of symbols]

SUB ... Transparent glass substrate, GL ... Scan signal line, DL ... Video signal line GI ... Insulating film, GT ... Gate electrode, AS ... i-type semiconductor layer SD ... Source electrode or drain electrode, PSV ... Protective film, BM ... Light-shielding film LC ... Liquid crystal, TFT ... Thin film transistor, ITO ... Transparent pixel electrode g, d ... Conductive film, Cadd ... Storage capacitor element, AOF ... Anodized film AO ... Anodized mask, GTM ... Gate terminal, DTM ...
Drain terminal

Claims (4)

[Claims] 1. A first substrate having a matrix portion formed with a plurality of pixels each having a pixel electrode and a thin film transistor transmitting a drive signal to the pixel electrode, and a counter electrode layer facing the pixel electrode. A second substrate, a liquid crystal layer, a seal pattern for confining the liquid crystal layer between the first and second substrates, a plurality of external connection terminals including the first conductor layer, and a second conductor including Al. A plurality of matrix wirings including a layer and connecting a plurality of the transistors, and a plurality of lead-out wirings connected to the external connection terminals and the matrix wirings and formed across the seal pattern. The lead-out wiring has the first conductor layer from the electrical contact portion with the matrix wiring to the external connection terminal, and the seal pattern of the seal pattern is provided from the contact portion to the external connection terminal. The second conductor layer is further provided in a range not exceeding the side, and in the range, the second conductor layer is in electrical contact with the first conductor layer without an insulating layer interposed therebetween. A liquid crystal display device characterized by the above. 2. The first conductor layer is a transparent body, and in the above range, the second conductor layer is formed by adding Cr to the first conductor layer.
2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is in electrical contact with another conductor layer including the. 3. The liquid crystal display device according to claim 1, wherein each of the matrix wirings is formed by electrically connecting the source and drain of a plurality of the transistors. 4. A first substrate having a matrix portion formed with a plurality of pixels each having a pixel electrode and a thin film transistor transmitting a drive signal to the pixel electrode, and a counter electrode layer facing the pixel electrode. A second substrate, a liquid crystal layer, a seal pattern for confining the liquid crystal layer between the first and second substrates, a plurality of external connection terminals formed outside the seal pattern, and protection for covering the transistor. An insulating layer; and a flexible wiring board having a plurality of output terminals electrically connected to the external connection terminals, and having an integrated circuit for supplying a drive signal to the output terminals.
A layer at the same level as the protective layer is formed so as to straddle the seal pattern, cover part of the external connection terminal and expose the other part, and the end portion of the wiring board is the same as the outside of the seal pattern. A liquid crystal display device characterized by being stacked on a level layer.