JP3311838B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device ,
In particular, the present invention relates to a liquid crystal display device including a semiconductor device manufactured by a so-called tape carrier method.

[0002]

2. Description of the Related Art Tape Carrie
The semiconductor device manufactured by the r) method is suitable for mass production, and has a feature that its structure is smaller than other types of semiconductor devices.

That is, a semiconductor chip is mounted on a flexible insulating substrate which is used in a tape shape during manufacturing, in a so-called face-down manner.

On the surface of the flexible insulating substrate, there is formed a wiring layer which is bonded to each electrode pad of the semiconductor chip and which is drawn out to the peripheral portion as an external extraction terminal.

[0005] The semiconductor chip mounted on the flexible insulating substrate is covered with, for example, a potted resin.

[0006]

However, the semiconductor device having such a configuration is required to be further miniaturized (smaller in area as viewed in plan), and the realization thereof has been expected.

[0007] Therefore, the present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal display device having a further miniaturized semiconductor device.

[0008]

In order to achieve such an object, the present invention basically relates to a liquid crystal display panel.
A liquid crystal display device comprising: a driving circuit;
Includes a flexible insulating substrate and a semiconductor chip mounted on the flexible insulating substrate, and an electrode pad group including a plurality of electrode pads arranged in one direction on a main surface of the semiconductor chip. the said semiconductor chip wiring layer group drawn as external extraction terminals on the periphery is bonded to the electrode pads of the group electrode pad is formed on the flexible insulating plate surface, the electrode pad group of the semiconductor chip is the semiconductor It is characterized in that it is positioned substantially at the center of the main surface of the chip.

[0009]

In the semiconductor device thus constructed, the wiring layer group formed on the surface of the flexible insulating substrate is called a so-called inner lead on the side bonded to the electrode pad of the semiconductor chip. Of the external terminals positioned in the vicinity of are referred to as so-called outer leads.

Since the interval between the outer leads is considerably larger than that of the inner leads, the wiring layer corresponding to the space between the outer leads and the inner leads is formed, for example, in the extending direction of the outer leads. Therefore, they are arranged obliquely.

Then, the minimum width between the outer leads and the inner leads is set by setting the minimum processing width between the wiring layers arranged diagonally (smaller than the width between the inner leads). , The width cannot be made smaller.

This means that the minimum width of the flexible insulating substrate that positions the outer leads at the periphery is also set, and the width cannot be made smaller.

However, according to the present invention, the electrode pads of the semiconductor chip are positioned substantially at the center of the main surface of the semiconductor chip.

This means that, despite the above-mentioned restrictions on the layout of the wiring layers, the position of the electrode pad group is shifted (the overlapping portion of the semiconductor chip and the flexible insulating substrate occurs). (3) The width of the flexible insulating substrate can be reduced.

Therefore, a semiconductor device with a reduced size is required.
A liquid crystal display device having the same can be obtained.

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS The invention, further objects of the invention and further features of the invention will become apparent from the following description with reference to the drawings, in which: FIG.

<< Active matrix liquid crystal display device >>
Hereinafter, an embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

<< Outline of Matrix Unit >> FIG. 2 is a plan view showing one pixel of an active matrix type color liquid crystal display device to which the present invention is applied and its periphery, and FIG.
FIG. 4 is a cross-sectional view taken along line -3 of FIG. 2, and FIG.
It is sectional drawing in a cutting line.

As shown in FIG. 2, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL.
And two adjacent video signal lines (drain signal lines or vertical signal lines) DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1, and a storage capacitor Cadd. The scanning signal lines GL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the up-down direction. Video signal line DL
Extend in the up-down direction and are arranged in a plurality in the left-right direction.

As shown in FIG. 3, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and a color filter FIL and a light-shielding element are formed on the upper transparent glass substrate SUB2 side. A black matrix pattern BM is formed. A silicon oxide film SIO formed by dipping or the like is provided on both surfaces of the transparent glass substrates SUB1 and SUB2.

A light shielding film BM and a color filter FI are provided on the inner surface (the liquid crystal LC side) of the upper transparent glass substrate SUB2.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and an upper alignment film ORI2 are sequentially laminated.

<< Outline of Matrix Peripheral >> FIG. 5 is a plan view of a main part around a matrix (AR) of a display panel PNL including upper and lower glass substrates SUB1 and SUB2, and FIG. FIG. 7 is an enlarged plan view of the vicinity of the seal portion SL corresponding to the upper left corner of the panel in FIGS. 5 and 6. 8 shows a cross section taken along the line 8a-8a in FIG. 7 with the cross section of FIG. 3 at the center and a cross section near the external connection terminal DTM to which the video signal drive circuit is to be connected on the right. is there. Similarly, FIG. 9 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

[0023] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared A glass substrate of a standardized size is processed even in a variety, and the size is reduced to a size suitable for each type. In each case, the glass is cut after passing through one process. FIGS. 5 to 7 show the latter example. Both FIGS. 5 and 6 show the upper and lower substrates SUB1 and SUB.
7 shows a state before cutting, FIG. 7 shows a state before cutting, LN denotes an edge of both substrates before cutting, and CT1 and CT2 denote substrates SU, respectively.
B1 and SUB2 indicate positions to be cut. In any case, in the completed state, the external connection terminal groups Tg and Td (subscripts omitted)
Are present (the upper and lower sides and the left side in the figure) so that the size of the upper substrate SUB2 is reduced so that they are exposed.
Restricted to inside of 1. The terminal groups Tg and Td respectively include a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, and their lead-out wiring portions, which are tape carrier packages TC on which the integrated circuit chip CHI is mounted.
P (FIGS. 18 and 19) are collectively named for each unit. The lead wiring from the matrix section of each group to the external connection terminal section is inclined as approaching both ends. This is because the display panel PN is included in the arrangement pitch of the package TCP and the connection terminal pitch in each package TCP.
This is for matching the L terminals DTM and GTM.

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal sealing opening INJ, the liquid crystal LC
Is formed to seal the sealing pattern SL. The sealing material is made of, for example, an epoxy resin. In at least one place, the common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the lead wiring INT formed on the lower transparent glass substrate SUB1 side by the silver paste material AGP at the four corners of the panel in this embodiment. ing. The lead wiring INT is formed in the same manufacturing process as the later-described gate terminal GTM and drain terminal DTM.

The layers of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2 are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are each a lower transparent glass substrate SUB
1. Formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is sealed in a region partitioned by the seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 for setting the direction of the liquid crystal molecules. The lower alignment film ORI1 is a protective film P on the lower transparent glass substrate SUB1 side.
It is formed above the SV1.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are sealed. Assembled by cutting.

<< Thin Film Transistor TFT >> Next, FIG.
Returning to FIG. 3, the configuration on the TFT substrate SUB1 side will be described in detail.

The thin film transistor TFT has a gate electrode G
When a positive bias is applied to T, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases.

Each pixel is provided with a plurality (two) of thin film transistors TFT1 and TFT2 redundantly. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same), and includes a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic,
intrinsic, not doped with conductivity determining impurities)
It has an i-type semiconductor layer AS made of amorphous silicon (Si), a pair of source electrode SD1, and a drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are interchanged during the operation. However, in the following description, one is fixed and the other is fixed as a drain for convenience.

<< Gate Electrode GT >> The gate electrode GT is configured to protrude vertically from the scanning signal line GL (branched into a T-shape). The gate electrode GT protrudes beyond the respective active areas of the thin film transistors TFT1 and TFT2. Thin film transistor TFT
1. The respective gate electrodes GT of the TFT 2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of a single-layer second conductive film g2. As the second conductive film g2, for example, an aluminum (Al) film formed by sputtering is used, and an anodic oxide film AOF of Al is provided thereon.

This gate electrode GT is formed to be larger (as viewed from below) so as to completely cover the i-type semiconductor layer AS, and is designed so that external light or backlight light does not hit the i-type semiconductor layer AS. .

<< Scanning Signal Line GL >> The scanning signal line GL is
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. An anodic oxide film AOF of Al is also provided on the scanning signal line GL.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistors TFT1 and TFT2. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected, and is formed to a thickness of 1200 to 2700 ° (about 2000 ° in this embodiment). As shown in FIG. 7, the gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM. The insulating film GI has the scanning signal line G
It also contributes to the electrical insulation between L and the video signal line DL.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
Is formed to be an independent island for each of the thin film transistors TFT1 and TFT2 in this example, and is made of amorphous silicon to a thickness of 200 to 2200 ° (in this example, 2 mm).
(Thickness of about 000 °). The layer d0 is an N (+)-type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, and has an i-type semiconductor layer AS below and a conductive layer d2 (d3) above. It is left only where you do.

The i-type semiconductor layer AS is provided between both intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Transparent Pixel Electrode ITO1 >> Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is connected to the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T1.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut off by a laser beam or the like, and if not, the other thin film transistor operates normally. You can leave it. The transparent pixel electrode ITO1 is composed of a first conductive film d1.
Is a transparent conductive film (Indium-Tin) formed by sputtering.
-Oxide ITO: Nesa film), 1000-200
0 mm thick (in this embodiment, about 1400 mm thick)
It is formed.

<< Source electrode SD1, Drain electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is composed of a second conductive film d2 in contact with the N (+) type semiconductor layer d0 and a third conductive film d3 formed thereon.

The second conductive film d2 is formed of a chromium (Cr) film formed by sputtering and having a thickness of 500 to 1000 ° (about 600 ° in this embodiment). Since the stress increases when the Cr film is formed thick,
It is formed in a range not exceeding a film thickness of about 0 °. Cr film is N
It is used for the purpose of improving the adhesion to the (+) type semiconductor layer d0 and preventing the Al of the third conductive film d3 from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). Second
As the conductive film d2, in addition to the Cr film, a refractory metal (Mo, T
i, Ta, W) film, refractory metal silicide (MoS
_{i 2, TiSi 2, TaSi 2} , WSi 2) film may be used.

The third conductive film d3 is formed to a thickness of 3000 to 5000 ° by sputtering of Al (in this embodiment, 400 μm).
(Approximately 0 °). The Al film has a smaller stress than the Cr film and can be formed to have a large film thickness. The Al film has a source electrode SD1, a drain electrode SD2, and a video signal line DL.
Has the effect of reducing the resistance value of the gate electrode GT and ensuring the overstep due to the gate electrode GT and the i-type semiconductor layer AS (improving the step coverage).

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, using the same mask, or using the second conductive film d2 and the third conductive film d3 as a mask, an N (+) type The semiconductor layer d0 is removed. That is,
N (+)-type semiconductor layer d0 remaining on i-type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so as to remove all of its thickness, the surface of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

<< Video Signal Line DL >> The video signal line DL is composed of the second conductive film d2 and the third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2.

<< Protective Film PSV1 >> Thin Film Transistor TF
A protective film PSV1 is provided on T and the transparent pixel electrode ITO1. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like.
Use a material with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD device, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

As shown in FIG. 7, the protective film PSV1 is formed so as to surround the entire matrix portion AR, the peripheral portion is removed so as to expose the external connection terminals DTM and GTM, and the common electrode of the upper substrate side SUB2 is formed. COM is the lower substrate SUB
Silver paste A on the lead-out wiring INT for connecting the external connection terminal 1
Portions connected by GP are also removed. Protective film PSV1
And the thickness of the gate insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner in the transconductance gm of the transistor. Therefore, as shown in FIG.
The protection film PSV1 having a high protection effect is formed to be larger than the gate insulating film GI so as to protect the peripheral portion as much as possible.

<< Light shielding film BM >> Upper transparent glass substrate SUB
On the second side, external light or backlight light is applied to the i-type semiconductor layer A.
A light shielding film BM is provided so as not to enter S. FIG.
The closed polygonal contour line of the light shielding film BM shown in FIG. 3 indicates an opening on the inside of which the light shielding film BM is not formed. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property. In this embodiment, the chromium film is formed to a thickness of about 1300 ° by sputtering.

Therefore, the thin film transistors TFT1, TF
The i-type semiconductor layer AS of T2 is sandwiched between the upper and lower light shielding films BM and the large gate electrode GT,
External natural light and backlight light do not shine. The light-shielding film BM is formed in a grid around each pixel (a so-called black matrix), and an effective display area of one pixel is partitioned by the grid. Therefore, the outline of each pixel is changed to the light shielding film BM.
Clarity and contrast. That is, the light-shielding film BM has two functions of light-shielding for the i-type semiconductor layer AS and black matrix.

Since the edge portion (the lower right portion in FIG. 2) of the transparent pixel electrode ITO1 on the root side in the rubbing direction is also shielded by the light shielding film BM, even if a domain is generated in the above portion, the domain is not visible. The display characteristics do not deteriorate.

As shown in FIG. 6, the light-shielding film BM is also formed in a frame shape at the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. I have. As shown in FIGS. 6 to 9, the light-shielding film BM in the peripheral portion is extended outside the seal portion SL to prevent leaked light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion. . On the other hand, the light-shielding film BM is retained about 0.3 to 1.0 mm inside the edge of the substrate SUB2, and is formed so as to avoid the cut region of the substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed in a stripe shape by repeating red, green, and blue at a position facing the pixel. The color filter FIL is formed to be large so as to cover the entirety of the transparent pixel electrode ITO1, and the light shielding film BM is formed so that the transparent pixel electrode I1 overlaps the color filter FIL and the edge of the transparent pixel electrode ITO1.
It is formed inside the periphery of TO1.

The color filter FIL can be formed as follows. First, a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process.

<< Protective Film PSV2 >> The protective film PSV2 is provided to prevent the dye of the color filter FIL from leaking into the liquid crystal LC. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin.

<< Common Transparent Pixel Electrode ITO2 >> The common transparent pixel electrode ITO2 is opposed to the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is determined by each pixel electrode ITO1. In response to a potential difference (electric field) between the pixel electrode and the common transparent pixel electrode ITO2. The common transparent pixel electrode ITO2 is configured to apply a common voltage Vcom. In the present embodiment, the common voltage Vcom is the minimum level driving voltage Vdmin and the maximum level driving voltage Vdmin applied to the video signal line DL.
Although it is set to an intermediate DC potential with dmax, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal drive circuit to about half, an AC voltage may be applied. 6 and 7 for the plan shape of the common transparent pixel electrode ITO2.

<< Structure of Storage Capacitor Cadd >> The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. As is clear from FIG. 4, this overlapping is performed by setting the transparent pixel electrode ITO1 to one electrode PL2 and connecting the adjacent scanning signal line GL to the other electrode PL2.
A storage capacitance element (capacitance element) Cadd is set to 1. The dielectric film of the storage capacitor Cadd is an insulating film G used as a gate insulating film of the thin film transistor TFT.
I and an anodic oxide film AOF.

The storage capacitance element Cadd is formed in a portion of the scanning signal line GL where the width of the second conductive film g2 is increased. Note that the portion of the second conductive film g2 that intersects with the video signal line DL is thinned in order to reduce the probability of a short circuit with the video signal line DL.

Even if the transparent pixel electrode ITO1 breaks at the step of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive layer d2 are formed so as to extend over the step.
The defect is compensated for by the island region constituted by the conductive film d3.

<< Gate Terminal Portion >> FIGS. 10A and 10B are diagrams showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, wherein FIG. 10A is a plane view and FIG. 10B is a view B of FIG. 4 shows a cross section taken along section line -B. This figure corresponds to the vicinity of the lower part of FIG. 7, and the diagonal wiring portion is represented by a straight line for convenience.

AO is a mask pattern for photo processing, in other words, a photoresist pattern of selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but the locus remains because the oxide film AOF is selectively formed on the gate wiring GL as shown in the cross-sectional view. In the plan view, the left side is a region which is covered with the resist and is not anodized, and the right side is a region which is exposed from the resist and is anodized with reference to the boundary line AO of the photoresist. Anodized A
L layer g2 conductive portion of the lower formed its oxide the Al ₂ O ₃ film AOF on the surface volume decreases. Of course, anodic oxidation is performed by setting an appropriate time, voltage and the like so that the conductive portion remains. The mask pattern AO does not intersect the scanning line GL with a single straight line, but intersects by bending in a crank shape.

In the figure, the AL layer g2 is hatched for easy understanding, but the region not anodized is patterned in a comb shape. This is because, when the width of the Al layer is large, whiskers are generated on the surface. Therefore, the width of each one is narrowed, and a plurality of these are bundled in parallel to prevent the generation of whiskers and disconnect the wires. The aim is to minimize the probability and conductivity sacrifice. Therefore, in this example, the portion corresponding to the root of the comb is also shifted along the mask AO.

The gate terminal GTM has a Cr layer g1 which has good adhesion to the silicon oxide SIO layer and has a higher contact resistance than Al or the like.
Further, it is composed of a transparent conductive layer d1 having the same level (same layer, simultaneous formation) as the pixel electrode ITO1 for protecting the surface thereof.
Note that the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof are formed in such regions that the conductive layers g2 and g1 are not etched together due to a pinhole or the like when the conductive layers d3 and d2 are etched. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 extending rightward beyond the gate insulating film GI is a thorough countermeasure.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line, and the protective film PSV1 is formed on the right side of the boundary line.
Are exposed from them so that they can make electrical contact with external circuits. In the figure, only one pair of the gate line GL and the gate terminal is shown. However, in practice, a plurality of such pairs are arranged vertically as shown in FIG. 7, and the terminal group Tg (FIGS. 6 and 7) is formed. In the manufacturing process, the left end of the gate terminal is extended beyond the cutting region CT1 of the substrate to extend the wiring SH.
g. Such a short-circuit line SHg in the manufacturing process is useful for power supply during anodization and prevention of electrostatic breakdown during rubbing of the alignment film ORI1 and the like.

<< Drain Terminal DTM >> FIGS. 11A and 11B are diagrams showing the connection from the video signal line DL to its external connection terminal DTM, where FIG. 11A shows the plane and FIG. 11B shows the plane B of FIG.
4 shows a cross section taken along section line -B. 7 corresponds to the vicinity of the upper right of FIG. 7, and the direction of the drawing is changed for convenience, but the right end direction corresponds to the upper end (or lower end) of the substrate SUB1.

TSTd is an inspection terminal, which is not connected to an external circuit, but is wider than a wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal D
The TM is also wider than the wiring part so that it can be connected to an external circuit. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a staggered manner in the vertical direction. The inspection terminals TSTd are terminated without reaching the end of the substrate SUB1 as shown in the figure.
Constitutes a terminal group Td (subscript omitted) as shown in FIG. 7 and further extends beyond the cutting line CT1 of the substrate SUB1.
Shorted by Hd. A drain connection terminal is connected to the opposite side of the matrix of the video signal lines DL in which the inspection terminals TSTd exist, and conversely, an inspection terminal is located in the opposite side of the matrix of the video signal lines DL in which the drain connection terminals DTM exist. Is connected.

The drain connection terminal DTM is made of the Cr layer g1 and the ITO layer d1 for the same reason as the gate terminal GTM described above.
And is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. On the terminal DTM, the protective film PSV1 is removed as a matter of course for connection with an external circuit. AO is the anodic oxidation mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side from the boundary line is covered with the mask. This pattern is not directly relevant since it does not exist.

As shown in FIG. 8C, the lead wiring from the matrix portion to the drain terminal portion DTM is connected to the video signal line DL immediately above the layers d1 and g1 at the same level as the drain terminal portion DTM. Although the layers d2 and d3 of the same level are stacked halfway in the seal pattern SL, this minimizes the probability of disconnection and makes it easy to touch.
The purpose is to protect the l-layer d3 as much as possible with the protective film PSV1 and the seal pattern SL.

<< Equivalent Circuit of Entire Display Device >> FIG. 12 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X indicates a video signal line DL, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively. Y indicates the scanning signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP uses a TFT liquid crystal display device to transfer information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a plurality of divided and stabilized voltage sources from one voltage source. This is a circuit that includes a circuit that exchanges information for use.

<< Operation of Storage Capacitor Cadd >> The storage capacitor Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is represented by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg where Cgs is the gate electrode G of the thin film transistor TFT.
Parasitic capacitance formed between T and the source electrode SD1, C
pix is the capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM), ΔV
lc represents a change in the pixel electrode potential due to ΔVg. The change ΔVlc causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance Cadd is increased. In addition, the holding capacitance element Cadd also has a function of extending the discharge time, and the thin film transistor TFT
The video information after turning off is accumulated for a long time. Reduction of the DC component applied to the liquid crystal LC improves the life of the liquid crystal LC,
It is possible to reduce so-called burn-in in which a previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. The midpoint potential Vlc has an adverse effect of being easily affected by the gate (scan) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cadd.

The storage capacitance of the storage capacitor Cadd is 4 to 8 times (4 · C) the liquid crystal capacitance Cpix due to the writing characteristics of the pixel.
pix <Cadd <8 · Cpix), 8 to 3 for the parasitic capacitance Cgs
The value is set to about twice (8 · Cgs <Cadd <32 · Cgs).

The first-stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is connected to the common transparent pixel electrode ITO2.
(Vcom) is set to the same potential. In the example of FIG. 7, the first-stage scanning signal line is short-circuited to the common electrode COM through the terminal GT0, the lead line INT, the terminal DT0, and the external wiring. Alternatively, the first-stage storage capacitor electrode line Y ₀ is connected to the last-stage scanning signal line Ye.
connected to nd, it may be connected to receive one extra scan pulse Y ₀ or from the vertical scanning circuit V is connected to a DC potential point (AC ground point) other than Vcom.

<< Manufacturing Method >> Next, a method of manufacturing the liquid crystal display device on the substrate SUB1 side will be described with reference to FIGS.
This will be described with reference to FIG. In the same figure, the characters in the center are the abbreviations of the process names, and the left side shows the flow of processing as viewed from the cross-sectional shape near the gate terminal shown in FIG. Except for the process D, the processes A to I are classified according to the respective photographic processes, and any cross-sectional view of each process shows a stage where the processing after the photographic process is completed and the photoresist is removed. In the present description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 13 After a silicon oxide film SIO is provided on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a ceric ammonium nitrate solution as an etchant. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line SHg for connecting the gate terminal GTM, the bus line SHd for short-circuiting the drain terminal DTM, and the anodized pad connected to the anodized bus line SHg (not shown) To form

Step B, FIG. 13 Al-Pd, Al-Si, Al-S having a thickness of 2800 °
Second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Is provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acetic acid.

Step C, FIG. 13 After photo processing (after the formation of the anodic oxidation mask AO described above), 3
% Tartaric acid was adjusted to pH 6.25 ± 0.05 with ammonia, and the substrate SUB1 was immersed in an anodic oxidizing solution consisting of a solution obtained by diluting 1: 9 with an ethylene glycol solution, and the formation current density was 0.5 mA / cm. ² so as to adjust (constant current Kasei). Next, anodic oxidation is performed until the formation voltage 125 V necessary for obtaining a predetermined Al ₂ O ₃ film thickness is reached. Thereafter, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g2 is anodized,
An anodic oxide film AOF having a thickness of 1800 ° is formed on scanning signal line GL, gate electrode GT and electrode PL1.

Step D, FIG. 14 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 2000-nm thick Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus. Is provided with a 2000 ° i-type amorphous Si film, and then a hydrogen gas and a phosphine gas are introduced into a plasma CVD apparatus to form an N (+)-type amorphous Si film having a thickness of 300 °.

Step E, FIG. 14 After photographic processing, SF ₆ and CC are used as dry etching gases.
Using l ₄ , N (+) type amorphous Si film, i type amorphous Si
By selectively etching the film, islands of the i-type semiconductor layer AS are formed.

Step F, FIG. 14 After the photo processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Step G, FIG. 15 A first conductive film d1 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form

Step H, FIG. 15 A second conductive film d2 made of Cr having a thickness of 600 .ANG. Is provided by sputtering, and a second conductive film d2 having a thickness of 4000 .ANG.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as in the step B, and the second conductive film d2 is etched with the same liquid as in the step A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. I do. Next, CCl ₄ and SF ₆ are introduced into a dry etching apparatus to form an N (+) type amorphous S
By etching the i film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG. 15 An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to form a 1 μm-thick Si nitride film. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo etching technique using SF ₆ as a dry etching gas.

<< Overall Configuration of Liquid Crystal Display Module >> FIG.
FIG. 3 is an exploded perspective view showing each component of the liquid crystal display module MDL.

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW and its display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, MFR is an intermediate frame, BL is a backlight, and BLS is a backlight. The support and the LCA are lower cases, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble the module MDL.

The module MDL is a shield case SH
The whole is fixed by a claw CL and a hook FK provided on D.

The intermediate frame MFR is formed in a frame shape so that an opening corresponding to the display window LCW is provided, and the frame portion has a shape corresponding to the shape and thickness of the diffusion plate SPB, the backlight support member BLS, and various circuit components. Irregularities and openings for heat dissipation are provided.

The lower case LCA also serves as a reflector for backlight, and has a reflection peak RM corresponding to the fluorescent tube BL so as to efficiently reflect the light.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 17 is a top view showing a state in which video signal driving circuits He and Ho and a vertical scanning circuit V are connected to the display panel PNL shown in FIG. 5 and the like.

CHI is a driving IC chip for driving the display panel PNL (the lower three are driving ICs on the vertical scanning circuit side)
Chips, 6 each on the left and right, drive I on the video signal drive circuit side
C chip). TCP is a tape carrier package in which a driving IC chip CHI is mounted by a tape automated bonding method (TAB), as will be described later with reference to FIGS. 18 and 19, and PCB1 is a driving in which the above-described TCP, capacitor CDS and the like are mounted. The circuit board is divided into three parts. FGP is a frame ground pad,
A spring-shaped fragment FG provided by cutting into the shield case SHD is soldered. FC is a flat cable for electrically connecting the lower drive circuit board PCB1 to the left drive circuit board PCB1 and the lower drive circuit board PCB1 to the right drive circuit board PCB1. As shown in the drawing, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material plated with Sn) are sandwiched and supported by a stripe-shaped polyethylene layer and a polyvinyl alcohol layer.

<< Connection Structure of TCP >> FIG. 18 shows a cross-sectional structure of a tape carrier package TCP constituting the scanning signal drive circuit V and the video signal drive circuits He and Ho, on which the integrated circuit chip CHI is mounted on a flexible wiring board. FIG. 19 is a cross-sectional view of a main part of the liquid crystal display panel, showing a state where it is connected to a video signal circuit terminal DTM in this example.

FIG. 18 is a cross-sectional view of XVIII-XVI of FIG.
This corresponds to a cross-sectional view taken along line II.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu. ) Is the integrated circuit C
The HI bonding pads PAD are connected by a so-called face-down bonding method. Terminal TTB, T
The outer ends (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
CRT / TFT conversion circuit / power supply circuit S by soldering
A liquid crystal display panel P is formed on the UP by using an anisotropic conductive film ACF.
NL. The package TCP has a protective film PS whose leading end exposes the connection terminal DTM on the panel PNL side.
Since the external connection terminal DTM (GTM) is covered with at least one of the protective film PSV1 and the package TCP, the external connection terminal DTM (GTM) is resistant to electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that solder does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by an epoxy resin EPX or the like, and the space between the package TCP and the upper substrate SUB2 is further filled with a silicone resin SIL to multiplex protection.

FIG. 1 is a plan view of the package TCP, and the resin film PRE shown in FIG. 18 is omitted.

In FIG. 1, there is a base film BF1, and a hole 100 is formed in a region where the semiconductor integrated circuit chip CH1 is located.

Here, the semiconductor integrated circuit chip CH1 is
In the bonding pad PAD, a pad group PAD1 on the input terminal side and a pad group PAD2 on the output terminal side are formed.

Among them, the number of pads in the pad group PAD1 is small, and the distance between them is large. Further, the number of pads in the pad group PAD group 2 is large, and the distance between them is also small. And the pad group PA
D1 is arranged along and close to one side of the surface of the semiconductor integrated circuit chip CH1. The pad group 1 is positioned on the opposite side and away from the side, that is, substantially at the center of the semiconductor integrated circuit chip CH1.

Pad group PAD1 of semiconductor integrated circuit CH1
Of the wiring layer formed on the surface of the base film BF1, each pad is bonded at a tip portion referred to as an inner lead, and an outer lead at the other end of the wiring layer is used as an output terminal TTB as a base film. It is arranged on one side of BF1.

Similarly, in the pad group PAD2, each pad is bonded at a tip portion called an inner lead in a wiring layer formed on the surface of the base film BF1, and the other end of the wiring layer is connected to the other end of the pad layer PAD2. One outer lead is disposed on one side of the base film BF1 as an output terminal TTM.

Note that one side of the semiconductor integrated circuit CH1 on the side where the pad group PAD2 is formed and the pad group PAD
2, a film piece FC is disposed, and the film piece FC provides insulation protection between the main surface of the semiconductor integrated circuit CH1 and the wiring layer.

Next, the technical effect of the pad group PAD2 being positioned substantially at the center of the surface of the semiconductor integrated circuit chip CH1 as described above will be described below.

FIG. 21 shows the pad group PAD2 and the output terminal T.
FIG. 3 is a diagram showing a positional relationship between TMs and wirings positioned between them.

In the figure, the separation distance of each pad of the pad group PAD2 is T, for example, each of the N output terminals T
Assuming that the separation distance of the TM is U and the wiring pitch between them is G, the height of the wiring, that is, the separation distance H between the pad group PAD2 and the output terminal (group) TTM is as follows. Become.

H = (N / 2−1 / 4) · (UT) ta
n (sin (G / U)) H is the minimum value determined by the above equation, and the width cannot be further reduced.

Therefore, the arrangement position of pad group PAD2 is shifted from one side of semiconductor integrated circuit CH1 toward the center by I, thereby reducing the width of base film BF1 by the corresponding length. You can do it.

Accordingly, the size of the package TCP itself can be reduced.

When the size of the package TCP can be reduced in this way, the periphery of the liquid crystal display panel PNL, that is, a region of a space that does not contribute to display (commonly referred to as PNL).
(Referred to as a frame) can be reduced.

In the above embodiment, the pad group PA
Although the D group PAD2 is described as being positioned substantially at the center of the surface of the semiconductor integrated circuit CH1, for example, as shown in FIG.
It has been found that it is effective to be separated from one side with a relationship of L ≧ 1 / 4W.

In the above-described embodiment, of the pad groups PAD1 and PAD2 opposed to each other, only one pad group PAD2 is positioned substantially at the center of the semiconductor integrated circuit CH1, but the present invention is not limited to this. Never
It goes without saying that the same may be applied to the pad group PAD1.

<< Drive Circuit Board PCB2 >> Intermediate Frame M
As shown in FIG. 31, the drive circuit board PCB2 of the liquid crystal display portion LCD held and housed in the FR has an L-shape and has mounted thereon electronic components such as ICs, capacitors, and resistors. The drive circuit board PCB2 includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (upper processing unit). A circuit SUP including a circuit for converting information into information for a TFT liquid crystal display device is mounted. CJ is a connector connection portion to which a connector (not shown) connected to the outside is connected. The drive circuit board PCB2 and the inverter circuit board PCB3 are electrically connected by a backlight cable through a connector hole provided in the intermediate frame MFR.

Driving circuit board PCB1 and driving circuit board PC
B2 is electrically connected by a foldable flat cable FC. When assembling, drive circuit board PCB
2 is placed on the back side of the drive circuit board PCB1 by bending the flat cable FC by 180 °, and fitted into a predetermined recess of the intermediate frame MFR.

[0114]

As is apparent from the above description,
According to the liquid crystal display device of the present invention, further miniaturization is achieved.
A device having the semiconductor device described above can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view showing one embodiment of a semiconductor device provided in a liquid crystal display device according to the present invention.

FIG. 2 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix type color liquid crystal display device to which the present invention is applied;

FIG. 3 is a cross-sectional view showing one pixel and its surroundings taken along section line 3-3 in FIG. 2;

FIG. 4 is a sectional view of the additional capacitance Cadd taken along section line 4-4 in FIG. 2;

FIG. 5 is a plan view illustrating a configuration of a matrix peripheral portion of a display panel.

FIG. 6 is a panel plan view for explaining a more specific example by slightly exaggerating a peripheral portion of FIG. 5;

FIG. 7 is an enlarged plan view of a corner portion of a display panel including an electrical connection portion between upper and lower substrates.

FIG. 8 is a cross-sectional view showing the vicinity of a panel corner and the vicinity of a video signal terminal on both sides with the pixel portion of the matrix in the center.

FIG. 9 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 10 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 11 is a plan view and a sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 12 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device.

FIG. 13 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 14 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes D to F on the substrate SUB1 side.

FIG. 15 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes GI on the substrate SUB1 side.

FIG. 16 is an exploded perspective view of the liquid crystal display module.

FIG. 17 is a top view showing a state where peripheral driving circuits are mounted on the liquid crystal display panel.

FIG. 18 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.

FIG. 19 is a cross-sectional view of a principal part showing a state where the tape carrier package TCP is connected to a video signal circuit terminal DTM of the liquid crystal display panel PNL.

FIG. 20 is a peripheral drive circuit board PCB1 (the upper surface is visible).
FIG. 11 is a top view showing a connection state between the power supply circuit board PCB2 (the lower surface is visible).

FIG. 21 is an explanatory diagram showing technical effects of the semiconductor device according to the present invention.

[Explanation of symbols]

SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line GI: insulating film, GT: gate electrode, AS: i-type semiconductor layer SD: source electrode or drain electrode, PSV: protective film, BM: light shielding film LC: liquid crystal, TFT: thin film transistor, ITO: transparent pixel electrode g, d: conductive film, Cadd: storage capacitor element, AOF: anodized film AO: anodized mask, GTM: gate terminal, DTM ...
Drain terminal SHD: Shield case, PNL: Liquid crystal display panel, S
PB: Light diffusion plate, MFR: Intermediate frame, BL: Backlight, BLS ...
Backlight support, LCA: Lower case, RM: Backlight reflection mountain,
(Subscripts omitted above).

Continuation of front page (56) References JP-A-4-123447 (JP, A) JP-A-5-82585 (JP, A) JP-A-4-177224 (JP, A) JP-A-5-326622 (JP) , A) Hikaru 4-114026 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1345 H01L 21/60

Claims (2)

(57) [Claims] 1. A liquid crystal display device comprising a liquid crystal display panel and a driving circuit, wherein the liquid crystal display panel has a plurality of external connection terminals to which signals from the driving circuit are input, and the driving circuit has a flexible insulation. A substrate and a semiconductor chip mounted on the flexible insulating substrate, and a main surface of the semiconductor chip is formed with an electrode pad group including a plurality of electrode pads arranged in parallel in the first direction; a long side along said first direction, and a short side extending along the second direction intersecting with said first direction, the flexible insulating substrate surface, is bonded to the electrode pads of the electrode pad group of the semiconductor chip Around
A wiring layer group issued can pull, and electrically connected to the output terminal group by an anisotropic conductive film is connected to the wiring layer and the external connection terminals of the liquid crystal display panel, the output terminal group The output terminal for forming the semiconductor has a large separation distance with respect to the separation distance of the electrode pad.
Are arranged along the long side of the chip, is formed extends from the short side of the front Symbol semiconductor chip to the outside of the first direction, the wiring layer for connecting the electrode pad and said output terminal and a first direction An oblique line extending at an angle with respect to the second direction, wherein the main surface of the semiconductor chip is closer to the second direction than the long side.
With the film strip is arranged, the electrode pad group of the semiconductor chip toward the second direction from the long side of the main surface of said semiconductor chip, said Fi
A liquid crystal display device, wherein the liquid crystal display device is positioned on the inner side of the lum piece . 2. A liquid comprising a liquid crystal display panel and a drive circuit.
A liquid crystal display panel to which a signal from the driving circuit is input.
A plurality of external connection terminals, and the driving circuit includes a flexible insulating substrate and the flexible insulating substrate.
A semiconductor chip mounted on a shibble insulating substrate , wherein main surfaces of the semiconductor chip are juxtaposed in the first direction.
An electrode pad group including a plurality of electrode pads is formed.
And a long side along the first direction intersects with the first direction.
And a short side along the second direction in which the semiconductor chip is electrically connected to the flexible insulating substrate surface.
Peripheral parts are bonded to each electrode pad of the pole pad group
A wiring layer group drawn out to the external connection of the liquid crystal display panel connected to the wiring layer
Output terminal electrically connected to terminal by anisotropic conductive film
And an output terminal forming the output terminal group is provided with the electrode pad.
The semiconductor having a large separation distance with respect to the separation distance of the semiconductor
Arranged along the long side of the chip,
A wiring layer formed to extend from a side to an outside in a first direction and connecting the electrode pad and the output terminal;
Extends at an angle to the first and second directions
The electrode pad group of the semiconductor chip has a diagonal line.
So that the wiring layer to be
From the long side of the main surface of the semiconductor chip in the second direction
Liquid crystal display characterized by being positioned inside
apparatus.