JPH07333636A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide a liquid crystal display device of a thin type and small size with high accuracy which contributes to an increase in the density of tape carrier packages and a reduction in the size thereof. CONSTITUTION:This liquid crystal display device is constituted by linearly drawing out the wiring TL1 of the tape carrier package TCP connected to an output terminal CP1 of an integrated circuit chip CH1 from the output terminal CP1 and linearly drawing the wirings TL2, TL3 connected to the output terminals CP2, CP3 out of the output terminals CP2, CP3, then bending the wirings perpendicularly toward a long side TS1, drawing out the wirings to the long side TS1 and disposing the alignment mark AM for alignment to the liquid crystal display panel in the space between the wiring TL1 and the wirings TL2, TL3 adjacent to each other on the outermost side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display using a tape carrier package mounted with a semiconductor integrated circuit chip for electrically connecting a liquid crystal display panel and a circuit board for driving the liquid crystal display panel. Regarding the device.

[0002]

2. Description of the Related Art Generally, a liquid crystal display device is formed by stacking two transparent glass substrates with a predetermined gap so that the surfaces on which the transparent pixel electrodes for display and the alignment film are laminated face each other. With the frame-shaped sealing material at the edge between,
A liquid crystal display in which both substrates are bonded together, liquid crystal is sealed inside the sealing material between both substrates through a liquid crystal sealing port provided in a part of the sealing material, and a polarizing plate is provided outside both substrates. A panel (liquid crystal display element), a backlight arranged below the liquid crystal display panel to supply light to the liquid crystal display panel, a driving circuit board arranged outside the outer peripheral portion of the liquid crystal display panel, and It is configured to include a frame-shaped body that is a molded product that holds each member, and a metal frame that houses each of these members and has a liquid crystal display window opened.

The liquid crystal display panel and the circuit board are electrically connected by a tape carrier package (TCP) on which an integrated circuit chip for driving the liquid crystal is mounted.

Such a liquid crystal display device is disclosed in, for example, Japanese Patent Laid-Open No. 61-214548 and Japanese Utility Model Laid-Open No. 2-137.
No. 65, etc.

[0005]

In recent years, liquid crystal display devices (liquid crystal display modules) have become larger in screen size and higher in definition, and have been attracting attention as display devices next to cathode ray tubes (CRTs). The performance of an integrated circuit chip for driving a liquid crystal display panel has been improved in the direction of increasing the number of pins and increasing the definition. When a QFP (Quad Flat Package) is used as an integrated circuit chip, the area occupied by the integrated circuit chip on the circuit board is large, and there is a limit to thin and high-density mounting.
It has moved to a tape carrier package.

FIG. 21 is a plan view of an example of a conventional tape carrier package. TCP is a tape carrier package, CHI is a drive integrated circuit chip mounted on the tape carrier package TCP, TTM1, TTM.
2 and TTM3 are tape carrier packages TC
P is an output terminal, OL is a diagonal wiring, TTB is an input terminal of the tape carrier package TCP, and AM is an alignment mark for alignment with the liquid crystal display panel.

The tape carrier package can be thinly mounted, and the degree of freedom of connection leads (wiring from the terminals of the integrated circuit chip to the input terminals of the liquid crystal display panel. In other words, the terminal pitch of the integrated circuit chip is constant, Wiring is possible even if the input terminal pitch of the liquid crystal display panel is not constant)
Is characterized by high The pitch of the output terminals TTM1 to TTM1 of the tape carrier package is matched with the pitch of the input terminals of the liquid crystal display panel by utilizing this degree of freedom. Therefore, since the diagonal wiring OL must be formed between the output terminal of the integrated circuit chip CHI and the output terminals TTM1 to TTM1 of the tape carrier package TCP,
It was difficult to densify the wiring, and the length in the direction of arrow A was increased, so that the tape carrier package TCP could not be downsized.

Further, alignment marks AM for alignment with the liquid crystal display panel are provided outside the outermost output terminals on both sides of the output terminals TTM1 to TTM1 of the tape carrier package TCP. Therefore, the width in the direction of the arrow B becomes large, and the tape carrier package T
The CP could not be miniaturized.

Note that such a technique is described in, for example, "Hitachi L.
"CD Driver LSI Data Book" 36-66, 19
It is described in March 1992.

An object of the present invention is to make the tape carrier package itself highly densified and compact, and as a result,
An object is to provide a thin, compact, and high-definition liquid crystal display device.

[0011]

In order to achieve the above object, the present invention provides a liquid crystal display panel, a circuit board for driving the liquid crystal display panel, and an integrated circuit chip for driving the liquid crystal display panel. A liquid crystal display device that is mounted and that includes a tape carrier package that electrically connects an output terminal of the circuit board and an input terminal of the liquid crystal display panel, in accordance with a pitch of terminals of the integrated circuit chip. The terminals of the tape carrier package are arranged.

Further, the first wiring of the tape carrier package electrically connected to the plurality of first output terminals on the first side of the integrated circuit chip has the tape from the first output terminal to the tape. The tape carrier that is drawn out in a substantially straight line on the second side of the carrier package and is electrically connected to the plurality of second output terminals on the two sides of the integrated circuit chip adjacent to the first side. The second wiring of the package is slightly linearly extended from the second output terminal, and then is bent substantially vertically toward the second side and is extended to the second side. Characterize.

Further, alignment marks for aligning the tape carrier package with the liquid crystal display panel are located between the first wiring and the second wiring that are closest to each other on the outermost side (or the integrated circuit). It is provided in the space of the tape carrier package near the corners of the integrated circuit chip at both ends of the first side of the chip, or in the area where the pitch of the first wiring and the second wiring is increased). It is characterized by

[0014]

In the liquid crystal display device of the present invention, by arranging the terminals of the tape carrier package in accordance with the pitch of the terminals of the integrated circuit chip, the wiring becomes easy, so that high density wiring can be achieved, and the tape carrier package Can be miniaturized.

Further, the first of the tape carrier package connected to the first output terminal of the first side of the integrated circuit chip.
Of the wiring from the first output terminal to the second side of the tape carrier package in a substantially straight line and connected to the second output terminals of the two sides of the integrated circuit chip adjacent to the first side. Connect the second wiring of the carrier package to the second
After pulling out a little from the output terminal in a straight line, bending it almost vertically toward the second side and pulling it out to the second side, the wiring of the tape carrier package is not wired diagonally. And the wiring can be performed at high density, and the length of the tape carrier package (in the direction in which the first wiring extends) can be reduced, and therefore the tape carrier package can be downsized. it can.

Further, an alignment mark for alignment with the liquid crystal display panel is provided in a space on the tape carrier package where no wiring exists between the first wiring and the second wiring which are adjacent to each other on the outermost sides. Therefore, the alignment marks can be arranged efficiently, and the tape carrier package can be downsized.

Thus, the wiring of the tape carrier package can be densified, and the tape carrier package itself can be miniaturized. As a result, it is possible to provide a thin, small, and high-definition liquid crystal display device. You can

[0018]

The invention, further objects of the invention and further features of the invention will be apparent from the following description with reference to the drawings.

<< Active Matrix Liquid Crystal Display Device >>
An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In addition,
In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

<< TCP Connection Structure >> FIG. 18 shows a scanning signal drive circuit (see V in FIG. 12) and a video signal drive circuit (see FIG. 1).
FIG. 19 is a diagram showing a cross-sectional structure of a tape carrier package in which a semiconductor integrated circuit chip is mounted on a flexible wiring board, which constitutes He, Ho of FIG. 2), and FIG. It is a principal part sectional view which shows the state connected to the terminal for signal circuits (refer DTM of FIG. 7, FIG. 12).

In the figure, TCP is a tape carrier package, CHI is a drive integrated circuit chip mounted on the tape carrier package TCP, TTM is an output terminal of the tape carrier package TCP, and TTB is an input terminal of the tape carrier package TCP. Yes, output terminal T
The TM and the input terminal TTB are made of, for example, Cu, and their inner tip portions (commonly called inner leads) are connected to the bonding pads PAD of the integrated circuit chip CHI by a so-called face-down bonding method. Outer end portions (commonly called outer leads) of the input terminal TTB and the output terminal TTM respectively correspond to the input and output of the integrated circuit chip CHI, and are soldered or the like to the CRT / TFT.
The conversion circuit / power supply circuit (see SUP in FIG. 12) is connected to the liquid crystal display panel PNL by an anisotropic conductive film ACF. The tape carrier package TCP is connected to the panel so that its tip portion covers the protective film PSV1 exposing the connection terminal DTM on the liquid crystal display panel PNL side, and therefore, the external connection terminal DTM (GTM in FIGS. 7 and 12). Is also covered with at least one of the protective film PSV1 and the tape carrier package TCP, and thus is resistant to electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it will not be attached to unnecessary places during soldering. The gap between the upper and lower transparent glass substrates on the outside of the pattern of the seal material SL is cleaned with an epoxy resin E.
It is protected by a PX or the like, and a silicon resin SIL is further filled between the tape carrier package TCP and the upper transparent glass substrate SUB2 to multiplex protection.

FIG. 1 is a plan view of a tape carrier package TCP included in a liquid crystal display device according to an embodiment of the present invention.

TTM1 to 3 are output terminals of the tape carrier package TCP, TTB are input terminals of the tape carrier package TCP, and CP1 to CP3 are integrated circuit chips CHI.
, CP4 is an input terminal of the integrated circuit chip CHI, TL1 to 4 are wirings of the tape carrier package TCP, and AM is an alignment mark for alignment with the liquid crystal display panel.

The tape carrier package TC shown here
In P, the terminals T of the tape carrier package TCP are matched with the pitches of the terminals CP1 to CP4 of the integrated circuit chip CHI.
By arranging TM1 to 4 and TTB, wiring becomes easy, so wiring can be performed at high density and the tape carrier package TCP can be downsized.

More specifically, as shown in FIG. 1, the output terminal CP of the long side CS1 of the integrated circuit chip CHI.
The wiring TL1 of the tape carrier package TCP connected to 1 is linearly extended from the output terminal CP1 to the long side TS1 (parallel to the long side CS1) of the tape carrier package TCP. Further, the wirings TL2 and TL3 of the tape carrier package TCP connected to the output terminals CP2 and CP3 of the two short sides CS2 and CS3 of the integrated circuit chip CHI adjacent to the long side CS1 are connected to the output terminals CP2 and CP3.
After being slightly pulled out from 3 in a straight line, it is bent vertically toward the long side TS1 and pulled out to the long side TS1. Thus, the wiring TL of the tape carrier package TCP
Since the wirings 1 to 4 are not wired obliquely, wiring can be facilitated and wiring can be performed at high density, and the length in the direction of the arrow A can be reduced, so that the tape carrier package TCP can be downsized. it can. The output terminals C of the short sides CS2 and CS3 of the integrated circuit chip CHI
The pitch of the wirings TL2 and TL3 (and their output terminals TTM2 and TTM3) connected to P2 and CP3 may be matched with the pitch of the output terminal CP1 on the long side CS1 side of the integrated circuit chip CHI.

Further, as shown in FIG. 1, the alignment mark AM for alignment with the liquid crystal display panel is located between the wiring TL1 and the wirings TL2 and TL3 which are the outermost and closest to each other (that is, adjacent to each other). , Provided in a space above the tape carrier package TCP where no wiring exists. In this way, the tape carrier package TC
When the output terminals TTM1 to 3 of P are pulled out straight,
The vicinity of the corners of the integrated circuit chip CHI on both ends of the long side CS1 of the integrated circuit chip CHI, that is, the wirings TTL1 to TTL3
A space is formed at a position where the pitch is increased, and by disposing the alignment mark AM in this space, the alignment mark AM can be efficiently arranged on the tape carrier package TCP, and the width in the arrow B direction is reduced. be able to. As a result, the tape carrier package TCP can be downsized.

As described above, in the tape carrier package TCP shown in FIG. 1, the wirings TL1 to TL4 can be efficiently formed with high density, and the alignment mark AM for alignment with the liquid crystal display panel can be efficiently arranged. Therefore, the dimension of the tape carrier package TCP having a high density can be reduced. as a result,
A thin, small, and high-definition liquid crystal display device can be provided.

<< Outline of Matrix Unit >> FIG. 2 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device to which the present invention is applied, and FIG.
-3 is a view showing a section taken along a cutting line, and FIG.
It is sectional drawing in a cutting line.

As shown in FIG. 2, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL.
And an adjacent two video signal lines (drain signal line or vertical signal line) DL are intersected with each other (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the vertical direction. Video signal line DL
Extend in the up-down direction and are arranged in the left-right direction.

As shown in FIG. 3, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and a color filter FIL and a light-shielding film are provided on the upper transparent glass substrate SUB2 side. A black matrix pattern BM is formed. Silicon oxide films SIO formed by dipping or the like are provided on both surfaces of the transparent glass substrates SUB1 and SUB2.

On the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2, a light shielding film BM and a color filter FI are provided.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

<< Outline of Matrix Periphery >> FIG. 5 is a plan view of a main part around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2, and FIG. 7 is a diagram showing an enlarged plane near the seal portion SL corresponding to the upper left corner of the panel in FIGS. 5 and 6. Further, FIG. 8 is a diagram showing a cross section taken along a cutting line 8a-8a in FIG. 7 on the left side and a cross section near the external connection terminal DTM to which the video signal drive circuit is to be connected on the right side with the cross section of FIG. 3 as the center. is there. Similarly, FIG. 9 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side and a cross section near the seal portion where there is no external connection terminal on the right side.

[0034] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared In each type of product, a standardized glass substrate is processed, and then the size is reduced to a size suitable for each product. In each case, the glass is cut after going through one step. 5 to 7 show an example of the latter case. In both of FIGS. 5 and 6, the upper and lower substrates SUB1 and SUB are shown.
2 shows the state after cutting, and FIG. 7 shows the state before cutting. LN is the edge of both substrates before cutting, and CT1 and CT2 are the substrate SU.
The positions where B1 and SUB2 should be cut are shown. In either case, in the completed state, the external connection terminal groups Tg, Td (subscripts omitted)
Are present (on the upper and lower sides and the left side in the figure), the size of the upper substrate SUB2 is such that the lower substrate SUB2 is exposed.
It is restricted to the inside of 1. The terminal groups Tg and Td are a tape carrier package TC in which a scanning circuit connection terminal GTM, a video signal circuit connection terminal DTM, and their lead-out wiring portions, which will be described later, are mounted on an integrated circuit chip CHI.
A plurality of Ps (FIGS. 18 and 19) are collectively named. The lead wiring from the matrix portion of each group to the external connection terminal portion is inclined toward both ends. This is due to the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP on the display panel PN.
This is for matching the L terminals DTM and GTM.

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal sealing port INJ, the liquid crystal LC
A seal pattern SL is formed so as to seal the. The sealing material is made of epoxy resin, for example. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to at least one of the lead wirings INT formed on the lower transparent glass substrate SUB1 side by the silver paste material AGP at four corners of the panel in this embodiment. ing. The lead wiring INT is formed in the same manufacturing process as a gate terminal GTM and a drain terminal DTM described later.

The orientation films ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2, and the respective layers are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are lower transparent glass substrates SUB, respectively.
1. Formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is enclosed in a region partitioned by a seal pattern SL between a lower alignment film ORI1 and an upper alignment film ORI2 that set the orientation of liquid crystal molecules. The lower alignment film ORI1 is a protective film P on the lower transparent glass substrate SUB1 side.
It is formed on top of SV1.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and the seal pattern SL is provided on the substrate SUB2.
Formed on the side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, the liquid crystal LC is injected from the opening INJ of the sealing material SL, and the injection port INJ is sealed with epoxy resin or the like to form the upper and lower substrates. It is assembled by cutting.

<< Thin Film Transistor TFT >> Next, referring to FIG.
Returning to FIG. 3, the configuration on the TFT substrate SUB1 side will be described in detail.

The thin film transistor TFT has a gate electrode G
When a positive bias is applied to T, the channel resistance between the source and the drain decreases, and when the bias is zero, the channel resistance increases.

A plurality of (two) thin film transistors TFT1 and TFT2 are redundantly provided in each pixel. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same), and has a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic,
intrinsic, conductivity type determination impurities are not doped)
It has an i-type semiconductor layer AS made of amorphous silicon (Si), a pair of source electrodes SD1 and a drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

<< Gate Electrode GT >> The gate electrode GT has a shape protruding vertically from the scanning signal line GL (branched into a T shape). The gate electrode GT projects so as to extend beyond the respective active regions of the thin film transistors TFT1 and TFT2. Thin film transistor TFT
The gate electrodes GT of the TFT 1 and the TFT 2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of the single-layer second conductive film g2. An aluminum (Al) film formed by sputtering, for example, is used as the second conductive film g2, and an Al anodic oxide film AOF is provided thereon.

The gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below), and is devised so that the i-type semiconductor layer AS is not exposed to outside light or backlight light. .

<< Scanning Signal Line GL >> The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. Also, an Al anodic oxide film AOF is provided on the scanning signal line GL.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS in the thin film transistors TFT1 and TFT2 together with the gate electrode GT. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected and is formed to a thickness of 1200 to 2700Å (in this embodiment, about 2000Å). As shown in FIG. 7, the gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM. The insulating film GI is a scanning signal line G
It also contributes to the electrical insulation between L and the video signal line DL.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
In this example, each of the thin film transistors TFT1 and TFT2 is formed as an independent island, and is made of amorphous silicon and has a thickness of 200 to 2200Å (2 in this example.
The film thickness is about 000Å). The layer d0 is a phosphorus (P) -doped N (+)-type amorphous silicon semiconductor layer for ohmic contact, the i-type semiconductor layer AS exists on the lower side, and the conductive layer d2 (d3) exists on the upper side. It is left only where you do.

The i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Transparent Pixel Electrode ITO1 >> Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by laser light or the like, and if not, the other thin film transistor operates normally. You can leave it alone because it does. The transparent pixel electrode ITO1 is composed of the first conductive film d1.
Is a transparent conductive film (Indium-Tin) formed by sputtering.
-Oxide ITO: Nesa film), 1000-200
With a thickness of 0Å (in this embodiment, a film thickness of about 1400Å)
It is formed.

<< Source Electrode SD1, Drain Electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is composed of a second conductive film d2 in contact with the N (+) type semiconductor layer d0 and a third conductive film d3 formed thereon.

The second conductive film d2 is a chromium (Cr) film formed by sputtering and is formed to a thickness of 500 to 1000 Å (in this embodiment, about 600 Å). If the Cr film is formed thicker, the stress increases.
It is formed within a range not exceeding the film thickness of 0Å. Cr film is N
It is used for the purpose of improving adhesion to the (+) type semiconductor layer d0 and preventing Al of the third conductive film d3 from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). Second
As the conductive film d2, in addition to the Cr film, refractory metal (Mo, T
i, Ta, W) film, refractory metal silicide (MoS
An i ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used.

The third conductive film d3 is formed by sputtering Al to a thickness of 3000 to 5000Å (400 in this embodiment).
0 Å) formed. The Al film has less stress than the Cr film and can be formed to have a large film thickness, and the source electrode SD1, the drain electrode SD2 and the video signal line DL can be formed.
Of the gate electrode GT and the i-type semiconductor layer AS are ensured (step coverage is improved).

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, an N (+) type film is formed by using the same mask or by using the second conductive film d2 and the third conductive film d3 as a mask. The semiconductor layer d0 is removed. That is,
The N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so that the entire thickness thereof is removed, the surface portion of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

<Video Signal Line DL> The video signal line DL is composed of a second conductive film d2 and a third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2.

<< Protective Film PSV1 >> Thin Film Transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

As shown in FIG. 7, the protective film PSV1 is formed so as to surround the entire matrix portion AR, the peripheral portion is removed so as to expose the external connection terminals DTM and GTM, and the common electrode of the upper substrate side SUB2 is formed. COM to the lower substrate SUB
Silver paste A on the lead wire INT for connecting the external connection terminal 1
The part connected by GP is also removed. Protective film PSV1
Regarding the thickness relationship between the gate insulating film GI and the gate insulating film GI, the former is made thicker in consideration of the protection effect, and the latter is made thin in the transconductance gm of the transistor. Therefore, as shown in FIG.
The protective film PSV1 having a high protective effect is formed so as to be larger than the gate insulating film GI so as to protect the peripheral portion over as wide a range as possible.

<< Light-shielding film BM >> Upper transparent glass substrate SUB
On the second side, external light or backlight is exposed to the i-type semiconductor layer A.
A light shielding film BM is provided so as not to enter S. Figure 2
The closed polygonal contour line of the light-shielding film BM shown in (3) indicates an opening inside which the light-shielding film BM is not formed. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300Å.

Therefore, the thin film transistors TFT1 and TF
The i-type semiconductor layer AS of T2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT,
External natural light or backlight does not hit. The light-shielding film BM is formed in a lattice shape around each pixel (so-called black matrix), and the effective display area of one pixel is partitioned by this lattice. Therefore, the outline of each pixel is the light-shielding film BM.
Improves clarity and contrast. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

Since the edge portion of the transparent pixel electrode ITO1 on the base side in the rubbing direction (the lower right portion in FIG. 2) is also shielded by the light shielding film BM, even if a domain occurs in the above portion, the domain cannot be seen. The display characteristics do not deteriorate.

As shown in FIG. 6, the light-shielding film BM is also formed in a frame shape in the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. 2 in which a plurality of openings are formed in a dot shape. There is. As shown in FIGS. 6 to 9, the light-shielding film BM in the peripheral portion is extended to the outside of the seal portion SL to prevent leak light such as reflected light caused by a mounting machine such as a personal computer from entering the matrix portion. . On the other hand, the light-shielding film BM is retained inside about 0.3 to 1.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cut region of the substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed in stripes by repeating red, green, and blue at positions facing the pixels. The color filter FIL is formed to have a large size so as to cover all of the transparent pixel electrode ITO1, and the light shielding film BM overlaps with the edge portions of the color filter FIL and the transparent pixel electrode ITO1.
It is formed inside the peripheral portion of TO1.

The color filter FIL can be formed as follows. First, a dyeing base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

<< Protective Film PSV2 >> The protective film PSV2 is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal LC. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

<< Common Transparent Pixel Electrode ITO2 >> The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. In this embodiment, the common voltage Vcom is the minimum level drive voltage Vdmin and the maximum level drive voltage V applied to the video signal line DL.
Although it is set to an intermediate DC potential with respect to dmax, an AC voltage may be applied if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal drive circuit to about half. For the planar shape of the common transparent pixel electrode ITO2, see FIGS. 6 and 7.

<< Structure of Storage Capacitance Element Cadd >> The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. In this superposition, as is clear from FIG. 4, the transparent pixel electrode ITO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used as the other electrode PL.
A holding capacitance element (electrostatic capacitance element) Cadd which is 1 is configured. The dielectric film of the storage capacitor Cadd is an insulating film G used as a gate insulating film of the thin film transistor TFT.
I and the anodic oxide film AOF.

The storage capacitor element Cadd is formed in a portion where the width of the second conductive film g2 of the scanning signal line GL is widened. The second conductive film g2 at the portion intersecting the video signal line DL is thinned in order to reduce the probability of short circuit with the video signal line DL.

Even if the transparent pixel electrode ITO1 is broken at the step portion of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d2 formed so as to cross the step.
The defect is compensated by the island region formed of the conductive film d3.

<< Gate Terminal Portion >> FIG. 10 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to the external connection terminal GTM thereof. -B shows a cross section taken along the line B. It should be noted that the figure corresponds to the lower part of FIG. 7, and the diagonal wiring portions are shown in a straight line for convenience.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but since the oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view, its locus remains. In the plan view, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized. Anodized A
The oxide Al ₂ O ₃ film AOF is formed on the surface of the L layer g2, and the volume of the conductive portion therebelow is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. The mask pattern AO does not intersect with the scanning line GL by a single straight line, but is bent in a crank shape and intersects.

In the figure, the AL layer g2 is hatched for easy understanding, but the region which is not anodized is patterned in a comb shape. This is because whiskers are generated on the surface when the width of the Al layer is wide. Therefore, by narrowing the width of each one and arranging a plurality of them in parallel, whiskers can be prevented and wire breakage can be prevented. The aim is to minimize the probability of and the sacrifice of conductivity. Therefore, in this example, the portion corresponding to the base of the comb is also displaced along the mask AO.

The gate terminal GTM has a Cr layer g1 which has a good adhesiveness to the silicon oxide SIO layer and has a higher electric contact resistance than Al or the like.
Further, the surface thereof is protected and is composed of a transparent conductive layer d1 of the same level (same layer, simultaneously formed) as the pixel electrode ITO1.
In addition, the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof have their regions so that the conductive layers g2 and g1 are not etched together due to pinholes or the like during the etching of the conductive layers d3 and d2. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 which extends over the gate insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located at the left end.
Are exposed from them to allow electrical contact with external circuitry. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, a plurality of such pairs are arranged vertically as shown in FIG. 7 to form the terminal group Tg (FIGS. 6 and 7). In the manufacturing process, the left end of the gate terminal is extended beyond the cutting region CT1 of the substrate to form the wiring SH.
shorted by g. Such a short-circuit line SHg in the manufacturing process is useful for supplying power during anodization and preventing electrostatic breakdown during rubbing of the alignment film ORI1.

<< Drain Terminal DTM >> FIG. 11 is a diagram showing the connection from the video signal line DL to the external connection terminal DTM, (A) shows the plane, and (B) shows B of (A).
-B shows a cross section taken along the line B. 7 corresponds to the vicinity of the upper right of FIG. 7, and although the orientation of the drawing is changed for convenience, the right end direction corresponds to the upper end (or lower end) of the substrate SUB1.

TSTd is an inspection terminal, which is not connected to an external circuit, but is wider than the wiring portion so that a probe needle or the like can come into contact therewith. Similarly, the drain terminal D
The width of the TM is also wider than that of the wiring portion so that the TM can be connected to an external circuit. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the substrate SUB1 as shown in the figure, but the drain terminal DTM.
7 further extend beyond the cutting line CT1 of the substrate SUB1 to form a terminal group Td (subscripts omitted) as shown in FIG. 7, all of which are interconnected to each other to prevent electrostatic breakdown during the manufacturing process.
Shorted by Hd. The drain connection terminal is connected to the opposite side of the matrix of the video signal lines DL in which the inspection terminals TSTd are present, and conversely the inspection terminal is placed on the opposite side of the matrix of the video signal lines DL in which the drain connection terminals DTM are present. Are connected.

The drain connection terminal DTM has the Cr layer g1 and the ITO layer d1 for the same reason as the above-mentioned gate terminal GTM.
Is formed of two layers, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. The protective film PSV1 is, of course, removed on the terminal DTM to connect to an external circuit. AO is the anodizing mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side of the boundary line is covered with the mask, but the layer g2 is covered in the part not covered in this figure. This pattern is not directly relevant as it does not exist.

As shown in FIG. 8C, the lead wiring from the matrix portion to the drain terminal portion DTM is provided with the video signal line DL immediately above the layers d1 and g1 at the same level as the drain terminal portion DTM. Although the layers d2 and d3 of the same level are laminated part way up to the middle of the seal pattern SL, this minimizes the probability of disconnection and facilitates electrical contact.
The purpose is to protect the l layer d3 as much as possible with the protective film PSV1 and the seal pattern SL.

<< Equivalent Circuit of Entire Display Device >> FIG. 12 shows a connection diagram of the equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device that displays information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) to obtain a plurality of divided and stabilized voltage sources from one voltage source. It is a circuit including a circuit for exchanging information for use.

<< Function of Storage Capacitance Element Cadd >> The storage capacity element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, Cgs is the gate electrode G of the thin film transistor TFT.
Parasitic capacitance formed between T and source electrode SD1, C
pix is a capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM), ΔV
lc represents a change amount of the pixel electrode potential due to ΔVg. This variation ΔVlc causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the holding capacitance Cadd is increased. Further, the storage capacitor element Cadd also has the function of prolonging the discharge time, and thus the thin film transistor TFT
Accumulates video information for a long time after is turned off. The reduction of the direct current component applied to the liquid crystal LC improves the life of the liquid crystal LC,
It is possible to reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large enough to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and the parasitic capacitance Cgs is increased accordingly. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, this demerit can be eliminated by providing the storage capacitor element Cadd.

The holding capacitance of the holding capacitance element Cadd is 4 to 8 times (4.C
pix <Cadd <8 · Cpix), 8 to 3 for parasitic capacitance Cgs
Set to a value about twice (8 · Cgs <Cadd <32 · Cgs).

The scanning signal line GL (Y ₀ ) in the first stage, which is used only as the storage capacitor electrode line, is the common transparent pixel electrode ITO2.
Set to the same potential as (Vcom). In the example of FIG. 7, the scanning signal line at the first stage is short-circuited to the common electrode COM through the terminal GT0, the lead wire INT, the terminal DT0 and the external wiring. Alternatively, the storage capacitor electrode line Y ₀ in the first stage is the scanning signal line Ye in the last stage.
It may be connected to nd, connected to a DC potential point (AC ground point) other than Vcom, or connected to receive one extra scanning pulse Y ₀ from the vertical scanning circuit V.

<< Manufacturing Method >> Next, a manufacturing method for the substrate SUB1 side of the above-described liquid crystal display device will be described with reference to FIGS.
Will be described with reference to. In the figure, the letters in the center are abbreviations of process names, the left side shows the pixel portion shown in FIG. 3, and the right side shows the processing flow as seen in the sectional shape near the gate terminal shown in FIG. Except for the step D, steps A to I are divided corresponding to each photographic process, and all the cross-sectional views of each process show the stage after the photo process is finished and the photoresist is removed. In this description, the photographic processing means a series of operations from the application of the photoresist to the selective exposure using the mask to the development thereof, and the repetitive description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 13 A silicon oxide film SIO is formed on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dip processing, and then baked at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a cerium ammonium nitrate solution as an etching solution. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line SHg connecting the gate terminal GTM, the bus line SHd shorting the drain terminal DTM, and the anodized pad (not shown) connected to the anodized bus line SHg. To form.

Step B, FIG. 13 Al-Pd, Al-Si, Al-S having a film thickness of 2800Å
The second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Are provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step C, FIG. 13: After photographic processing (after forming the above-described anodic oxidation mask AO), 3
Substrate SUB1 is immersed in an anodizing solution consisting of a solution prepared by diluting 1% of tartaric acid with ammonia to pH 6.25 ± 0.05 with ethylene glycol solution, and the formation current density is 0.5 mA / cm. ² so as to adjust (constant current Kasei). Next, anodic oxidation is performed until the formation voltage 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g2 is anodized,
An anodic oxide film AOF having a film thickness of 1800Å is formed on scanning signal line GL, gate electrode GT and electrode PL1.

Step D, FIG. 14 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a 2000 Å-thickness Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus. After forming an i-type amorphous Si film having a thickness of 2000 Å, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N (+)-type amorphous Si film having a film thickness of 300 Å.

Step E, FIG. 14 After photo processing, SF ₆ and CC are used as dry etching gas.
Use l ₄ N (+) type amorphous Si film, i-type amorphous Si
The island of the i-type semiconductor layer AS is formed by selectively etching the film.

Step F, FIG. 14 After the photographic process, SF ₆ is used as a dry etching gas to selectively etch the Si nitride film.

Step G, FIG. 15 A first conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layers of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form.

Step H, FIG. 15: A second conductive film d2 made of Cr having a film thickness of 600 Å is provided by sputtering.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as the process B, and the second conductive film d2 is etched with the same liquid as the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do. Next, by introducing CCl ₄ and SF ₆ into the dry etching apparatus, N (+) type amorphous S
By etching the i film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG. 15 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a Si nitride film having a thickness of 1 μm. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo-etching technique using SF ₆ as a dry etching gas.

<< Overall Structure of Liquid Crystal Display Module >> FIG.
[Fig. 3] is an exploded perspective view showing each component of the liquid crystal display module MDL.

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, MFR is an intermediate frame, BL is a backlight, and BLS is a backlight. The support and the LCA are the lower case, and the modules MDL are assembled by stacking the respective members in a vertical arrangement relationship as shown in the figure.

The module MDL is a shield case SH.
The whole is fixed by the claw CL and the hook FK provided on D.

The intermediate frame MFR is formed in a frame shape so that an opening corresponding to the display window LCW is provided, and the frame portion has a diffusion plate SPB, a backlight support BLS, and various circuit components in accordance with their shapes and thicknesses. There are irregularities and openings for heat dissipation.

The lower case LCA also serves as a reflector for backlight light, and a reflection mountain RM is formed corresponding to the fluorescent tube BL so as to reflect light efficiently.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 17 is a top view showing a state in which the video signal drive circuits He and Ho and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.

CHI is a driving IC chip for driving the display panel PNL (the lower three are driving ICs on the vertical scanning circuit side).
Chips, 6 each on the left and right are drive I on the video signal drive circuit side
C chip). The TCP is a tape carrier package in which the drive IC chip CHI is mounted by the tape automated bonding method (TAB) as described above with reference to FIGS. 18 and 19, and the PCB 1 is mounted with the TCP, the capacitor CDS and the like. The drive circuit board is divided into three parts. FGP is a frame ground pad, and a spring-like fragment FG cut and provided in the shield case SHD is soldered. FC is a lower drive circuit board PCB1 and a left drive circuit board PCB1, and a lower drive circuit board PCB1 and a right drive circuit board PC.
It is a flat cable that electrically connects to B1. As the flat cable FC, as shown in the figure, a plurality of lead wires (phosphor bronze material plated with Sn) sandwiched between a striped polyethylene layer and a polyvinyl alcohol layer are used.

<< Drive Circuit Board PCB2 >> Intermediate Frame M
As shown in FIG. 31, the drive circuit board PCB2 of the liquid crystal display unit LCD which is held / stored in the FR is L-shaped, and has electronic parts such as ICs, capacitors and resistors mounted thereon. This drive circuit board PCB2 is provided with a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (upper processing unit). A circuit SUP including a circuit for converting into information for a TFT liquid crystal display device is mounted. CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected. The drive circuit board PCB2 and the inverter circuit board PCB3 are electrically connected by a backlight cable through a connector hole provided in the intermediate frame MFR.

Drive circuit board PCB1 and drive circuit board PC
B2 is electrically connected by a foldable flat cable FC. When assembled, drive circuit board PCB
2 is stacked on the back side of the drive circuit board PCB1 by bending the flat cable FC by 180 ° and fitted into a predetermined recess of the intermediate frame MFR.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. .

[0106]

As described above, according to the present invention,
The tape carrier package can be highly dense and compact, and as a result, a thin, compact, and high-definition liquid crystal display device can be provided.

[Brief description of drawings]

FIG. 1 is a plan view of a tape carrier package included in a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a main-portion plan view showing one pixel and its periphery of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied.

FIG. 3 is a cross-sectional view showing one pixel and its periphery taken along the section line 3-3 in FIG.

FIG. 4 is a cross-sectional view of the additional capacitance Cadd taken along the line 4-4 in FIG.

FIG. 5 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel.

FIG. 6 is a panel plan view for slightly exaggerating the peripheral portion of FIG. 5 to explain it more specifically.

FIG. 7 is an enlarged plan view of a corner portion of a display panel including electrical connection portions of upper and lower substrates.

FIG. 8 is a cross-sectional view showing the vicinity of a panel angle and the vicinity of a video signal terminal portion on both sides, with the pixel portion of the matrix at the center.

FIG. 9 is a cross-sectional view showing a scan signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 10 is a plan view and a cross-sectional view showing the vicinity of a connecting portion between a gate terminal GTM and a gate wiring GL.

FIG. 11 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 12 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device.

FIG. 13 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side.

FIG. 14 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes D to F on the side of the substrate SUB1.

FIG. 15 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps GI on the side of the substrate SUB1.

FIG. 16 is an exploded perspective view of a liquid crystal display module.

FIG. 17 is a top view showing a state in which a peripheral drive circuit is mounted on a liquid crystal display panel.

FIG. 18 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI forming a drive circuit is mounted on a flexible wiring board.

FIG. 19 is a cross-sectional view of essential parts showing a state in which the tape carrier package TCP is connected to the video signal circuit terminal DTM of the liquid crystal display panel PNL.

FIG. 20: Peripheral drive circuit board PCB1 (top surface visible)
It is a top view which shows the connection state of power supply circuit circuit board PCB2 (a lower surface is visible).

FIG. 21 is a plan view of an example of a conventional tape carrier package.

[Explanation of symbols]

TCP ... Tape carrier package, CHI ... Semiconductor integrated circuit chip, TTM1 to 3 ... Tape carrier package output terminal, TTB ... Tape carrier package input terminal, CP1 to 3 ... Integrated circuit chip output terminal, CP
4 ... Input terminals of integrated circuit chip, TL1-4 ... Wiring of tape carrier package, AM ... Alignment mark,
CS1 to 4 ... Edge of integrated circuit chip, TS1 ... Edge of tape carrier package.

Claims (3)

[Claims] 1. A liquid crystal display panel, a circuit board for driving the liquid crystal display panel, an integrated circuit chip for driving the liquid crystal display panel, and an output terminal of the circuit board and the liquid crystal display panel. In a liquid crystal display device including a tape carrier package electrically connecting the input terminal of the tape carrier package, the terminals of the tape carrier package are arranged according to the pitch of the terminals of the integrated circuit chip. Liquid crystal display device. 2. A liquid crystal display panel, a circuit board for driving the liquid crystal display panel, and an integrated circuit chip for driving the liquid crystal display panel are mounted, and the circuit board and the liquid crystal display panel are electrically connected. A liquid crystal display device including a tape carrier package that is electrically connected, the first wiring of the tape carrier package electrically connected to the first output terminal of the first side of the integrated circuit chip, From the first output terminal, the tape carrier package is drawn out to a second side in a substantially straight line, and is electrically connected to a second output terminal on two sides of the integrated circuit chip adjacent to the first side. The second wiring of the connected tape carrier package is slightly pulled out in a substantially straight line from the second output terminal, and then bent substantially vertically toward the second side. The liquid crystal display device, characterized by being drawn to the side. 3. An alignment mark for aligning the tape carrier package with the liquid crystal display panel,
The liquid crystal display device according to claim 2, wherein the liquid crystal display device is provided in a space of the tape carrier package between the first wiring and the second wiring that are closest to each other on the outermost sides.