JP2000035573A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of luminance unevenness of a backlight which utilizes a light transmission plate with a notch at least on a side where a wire shaped lamp is located. SOLUTION: A liquid crystal panel constructed by confronting the first and the second substrates keeping a specified gap, by sticking them at an outer periphery of a display region with a sealant together and by enclosing a liquid crystal layer in the gap, a backlight constructed with a light transmission plate GLB and a wire shaped lamp LP located along at least on a side of it and a molded member which holds the light transmission plate GLB constituting the backlight are comprised. A notch CUTC with a curved wall is formed at an edge of one side of the light transmission plate GLB confronting the linear lamp LP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which the entire surface of a light guide plate constituting a backlight corresponding to a narrower frame can be used as an effective illumination area.

[0002]

2. Description of the Related Art A high-definition and color display liquid crystal display device for a notebook computer or a computer monitor is provided with a light source (so-called backlight) for illuminating a liquid crystal panel from behind.

This type of liquid crystal display device basically forms a so-called liquid crystal panel in which a liquid crystal layer is sandwiched between two substrates at least one of which is made of transparent glass or the like, and is formed on the substrate of the liquid crystal panel. A type in which predetermined voltages are selectively applied to the various electrodes for pixel formation to turn on and off predetermined pixels (simple matrix), the various electrodes and active elements for pixel selection are formed, and the active elements are selected. Accordingly, it is broadly classified into a form (active matrix) for turning on and off a predetermined pixel.

A conventional active matrix type liquid crystal display device employs a so-called vertical electric field method in which an electric field for changing the orientation of a liquid crystal layer is applied between an electrode formed on one substrate and an electrode formed on the other substrate. Was adopted.

In recent years, a so-called in-plane switching (IPS) liquid crystal display device has been realized in which the direction of an electric field applied to a liquid crystal layer is substantially parallel to the substrate surface. As this in-plane switching type liquid crystal display device, a device in which a very wide viewing angle is obtained by using a comb electrode on one of two substrates is known (Japanese Patent Publication No. 63-21907, US Patent No. 4345249).

In any of the above types of liquid crystal display devices, a side edge type backlight comprising a light guide plate and a linear light source, or a plurality of linear light sources is directly provided on the back of the liquid crystal panel as an illumination light source for the liquid crystal panel. There is known a direct type backlight. In particular, the side-edge type backlight has at least one transparent plate such as an acrylic plate.
Linear lamps along one side edge (usually cold cathode fluorescent tubes)
And introduce the light from this linear lamp into the light guide plate,
The configuration is such that the liquid crystal panel arranged above is illuminated from the back surface by changing the path while the light propagates inside the light guide plate.

[0007] In recent years, with the spread of multimedia and mobile computing, notebook computers and the like having performance comparable to desktop machines have been spreading, and their display devices will also be large screens of the order of 14 to 15 inches. It is in the situation where the one of the size is put to practical use.

[0008]

In order to mount a liquid crystal display device having a panel size of 14 to 15 inches on an upper housing (lid portion) of a notebook personal computer or the like, almost all the area of the lid is effectively displayed. It is necessary to push frame narrowing to the limit so that it becomes an area.

However, since a fixing claw or the like must be arranged in the frame area of the liquid crystal display device, the light guide plate of the backlight, which is an illumination light source, is also required to have at least one corner (generally, two corners) for disposing them. Corners and four corners).

In order to push the narrowing of the frame to the limit, the entire surface of the light guide plate including the notch is used as an effective light emitting area, and light from a linear lamp (generally, a cold cathode fluorescent tube) also enters from the notch. However, since the light incident from this notch has a different light guiding state than the light incident from the normal light incident surface (the side facing the linear lamp), uneven brightness occurs. This leads to a decrease in visibility.

FIG. 28 is a schematic plan view illustrating a schematic structure of a conventional side edge type backlight. This side edge type backlight (hereinafter, simply referred to as a backlight) has a linear lamp LP arranged along one side edge of a light guide plate GLB made of a transparent acrylic plate having a flat or wedge-shaped cross section. From the light guide plate GLB. The light guide plate GLB is formed at its corner with a cutout CUTL whose plane wall intersects.

However, a backlight provided with a light guide plate having such a notch causes luminance unevenness as described below.

FIG. 29 is a diagram for explaining the occurrence of uneven brightness.
28 is an enlarged schematic view of the portion A, and the same reference numerals as those in FIG. 28 correspond to the same portions. When the narrowing of the frame is pushed forward, the linear lamp L
P has a length substantially equal to the width of the side surface that is the light incident surface of the light guide plate GLB. In such a case, at the corner of the light guide plate GLB,
A region where the light from the linear lamp LP is cut off and cut off by the cutouts CLTL occurs.

When the cutouts are formed by intersecting plane walls as shown, incident light is directed in a specific direction. For example, the notch C of the linear lamp LP
The light L1 emitted from the immediate vicinity a of the UTL wall surface has an angle φ determined by the refractive index n of the air and the light guide plate GLB near the intersection of the wall surfaces.
_{At 1 the} light enters the light guide plate GLB.

On the other hand, the light L2 emitted from the end point b of the linear lamp at an angle of θ is similarly refracted and enters the light guide plate GLB. The approach angle φ ₂ is φ ₂ = sin ⁻¹ · (1 /
n · sin θ). In the case of an acrylic resin light guide plate, φ ₁ ≒ 42 °.

The light between the point a and the point b is directed to the light incident surface side of the light L1 (above the light L1 in the figure) or the light incident surface side of the light L2 (below the light L2 in the figure). I will. Therefore, in the light guide plate GLB, a shadow SDW having low luminance is generated in a region indicated by oblique lines in the drawing, and the illumination light distribution of the liquid crystal panel is reduced in this region, causing display unevenness and causing deterioration in image quality.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to prevent the occurrence of uneven brightness of a backlight using a light guide plate having a cutout at least on the installation side of a linear lamp, thereby achieving high image quality. An object of the present invention is to provide a liquid crystal display device capable of displaying an image.

[0018]

In order to achieve the above object, the present invention provides a light guide plate in which a notch formed at a corner portion has a curved wall surface so that a line is formed. It is characterized in that light from the lamp is prevented from entering in a specific direction. In addition, the shape of this notch
Hereinafter, it is referred to as a notch having a curved wall.

Typical configurations of the present invention are as follows.

(1) The first substrate and the second substrate are opposed to each other at a predetermined gap, and the outer periphery of the display area is bonded with a sealant.
A back panel comprising a liquid crystal panel having a liquid crystal layer sealed in the gap, and a linear lamp provided along at least one side edge of the light guide plate, and installed on the back of the liquid crystal panel to illuminate the liquid crystal panel from the back. In a liquid crystal display device including a light and a mold member that holds a light guide plate constituting the backlight, a notch having a curved wall at an end of the one side edge of the light guide plate facing the linear lamp. I got it.

The light from the linear lamp incident on the curved wall is not directed in a specific direction, so that there is no luminance unevenness.

(2) A light incident portion from the linear lamp includes the cutout portion having the curved wall of the light guide plate in the above (1).

According to this configuration, a linear lamp having a length equal to the width of the light incident surface of the light guide plate can be used, and the frame is narrowed.

(3) The notched portion having the curved wall of the light guide plate in the above (1) or (2) is a space for installing the member for fixing the light guide plate or the liquid crystal display device.

The notch having the curved wall is not limited to the notch formed on the side wall facing the linear lamp, but can be applied to all the notches required for the light guide plate.

It should be noted that the present invention is not limited to the above-described configuration, and it is needless to say that various modifications can be made without departing from the technical idea of the present invention.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the illustrated embodiments.

FIG. 1 is a schematic plan view of a backlight for explaining a schematic structure of a first embodiment of a liquid crystal display device according to the present invention. In this backlight, a linear lamp LP is arranged along one side edge of a light guide plate GLB made of a transparent acrylic plate having a flat plate shape or a wedge-shaped cross section similarly to that described with reference to FIG.
The light from the linear lamp LP is introduced into the light guide plate GLB.

The light guide plate GLB is formed with a cut-out cutout TCTC having a curved wall at a corner thereof. The cut-out cutout having a curved wall is concave when viewed from above. The cutout cutout has a mounting member for mounting the liquid crystal display device on a lid of a notebook personal computer or the like, or a light guide plate itself. Claws or projections for fixing to the case are located.

FIG. 2 is an enlarged schematic view of the portion A in FIG. 1 for explaining the effect of the embodiment of the present invention, and the same reference numerals as those in FIG. 1 correspond to the same portions. Notched CU with curved wall of this embodiment
TC is formed in a concave shape with respect to the linear lamp LP.

With such a shape, the light incident from the linear lamp LP is not directed in a specific direction. That is, linear lamp LP notch light L1 the light guide plate at an angle phi ₃ from the wall surface of the track walls is determined by the refractive index n of the air and the light guide plate GLB emitted from nearest a of cutc GLB
To enter. At this time, since the wall surface is gentler than a line perpendicular to the linear lamp, the light L1 enters the light guide plate GLB in the illustrated direction.

On the other hand, the light L2 emitted at an angle of θ from the end b of the linear lamp similarly refracts and enters the light guide plate GLB. The entrance angle φ ₄ is not refracted as described in FIG. 9 because the wall surface is gentle, and enters the light guide plate GLB in the illustrated direction.

Therefore, the light between the point a and the point b is effectively introduced into the light guide plate GLB between the light L1 and the light L2, and the shadow as shown in FIG. Does not occur.

FIG. 3 is an exploded perspective view for explaining the whole structure of the embodiment of the liquid crystal display device according to the present invention. The liquid crystal display device (hereinafter, a liquid crystal panel, a circuit board, a backlight and other components are integrated). Liquid crystal display module: MDL
) Will be described.

In FIG. 3, SHD is a shield case (also referred to as a metal frame) made of a metal plate, WD is a display window, INS1 to 3 are insulating sheets, PCB1 to 3 are circuit boards (PCB1 is a drain side circuit board: a video signal). Line driving circuit board, PCB2 is gate side circuit board, PCB3 is interface circuit board), JN1-3 are circuit boards PC
Joiner for electrically connecting B1 to B1, TCP1,
TCP2 is a tape carrier package, PNL is a liquid crystal display panel, GC is a rubber cushion, ILS is a light shielding spacer, PRS is a prism sheet, SPS is a diffusion sheet, G
LB is a light guide plate, RFS is a reflection sheet, MCA is a lower case (mold frame) formed by integral molding,
MO is an opening of the MCA, LP is a fluorescent tube, LPC is a lamp cable, GB is a rubber bush supporting the fluorescent tube LP, B
AT denotes a double-sided adhesive tape, BL denotes a backlight made of a fluorescent tube, a light guide plate, or the like, and a liquid crystal display module MDL is assembled by stacking diffusion plate members in the arrangement shown in the drawing.

The liquid crystal display module MDL has two kinds of storage / holding members of a lower case MCA and a shield case SHD, and includes insulating sheets INS1 to INS3 and circuit boards PCB1 to PCB1.
3. A metal shield case SHD in which the liquid crystal display panel PNL is housed and fixed, and a lower case MCA in which a backlight BL including a fluorescent tube LP, a light guide plate GLB, a prism sheet PRS, and the like are housed are combined.

An integrated circuit chip for driving each pixel of the liquid crystal display panel PNL is mounted on the video signal line driving circuit board PCB1, and the interface circuit board PC
The B3 includes an integrated circuit chip that receives a video signal from an external host, receives a control signal such as a timing signal, and a timing converter TCON that processes a timing to generate a clock signal.

The clock signal generated by the timing converter is integrated on the video signal line driving circuit board PCB1 via the clock signal line CLL laid on the interface circuit board PCB3 and the video signal line driving circuit board PCB1. Supplied to the circuit chip.

The interface circuit board PCB3 and the video signal line driving circuit board PCB1 are multilayer wiring boards, and the clock signal line CLL is the interface circuit board PCB3 and the video signal line driving circuit board PC
It is formed as an inner wiring of B1.

The liquid crystal panel PNL has a drain-side circuit board PCB1, a gate-side circuit board PCB2, and an interface circuit board PCB3 for driving TFTs.
Are connected by tape carrier packages TCP1 and TCP2, and the circuit boards are connected by joiners JN1, JN2, JN3.

The backlight BL includes a light guide plate GLB, a linear lamp LP (fluorescent tube: cold cathode fluorescent tube) and a reflection sheet L.
S, and power is supplied from an inverter power supply (not shown) via a lamp cable LPC.

The light guide plate GLB is shown in FIGS.
As shown in (1), a notch CUTC having a curved wall is formed at a corner corresponding to the end of the linear lamp LP. A projection PJ for fixing and holding the light guide plate GLB is formed in a portion of the opening MO of the lower case MCA corresponding to the notch of the light guide plate GLB. The convex portion PJ is formed below the cutout CUTC having the curved wall of the light guide plate GLB so as to rise to such an extent that a part of the curved wall is locked, and has an effect on the incidence of light from the linear lamp LP. I will not give.

In this configuration example, the notch having the curved wall is the fixed holding portion of the light guide plate. However, the present invention is not limited to this, and the liquid crystal display device is provided in the notch having the curved wall. A mounting member to be mounted on a notebook computer or the like may be located.

FIG. 3 shows an active matrix type liquid crystal display device as an example. However, the present invention is not limited to this, and the present invention can be similarly applied to a backlight of a simple matrix type liquid crystal display device.

Hereinafter, an active matrix type color liquid crystal display device to which the present invention is applied will be described in detail.

FIG. 4 is a plan view illustrating a configuration of one pixel of an active matrix type liquid crystal display device to which the present invention is applied and the periphery thereof, FIG. 5 is a cross-sectional view taken along line 3-3 in FIG. 6 is a sectional view taken along line 4-4 in FIG. 4, and FIG. 7 is a plan view showing a state where a plurality of pixels shown in FIG. 4 are arranged.

As shown in FIG. 4, each pixel has two adjacent pixels.
Scanning signal lines (gate signal lines or horizontal signal lines) GL
And two adjacent video signal lines (drain signal lines or vertical signal lines) DL (in a region surrounded by four signal lines).

Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1, and a storage capacitor Cadd. The scanning signal lines GL extend in the column direction, and a plurality of the scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction and are arranged in a plurality in the column direction.

As shown in FIG. 5, the thin film transistor TF is provided on the lower transparent glass substrate SUB1 side with respect to the liquid crystal LC.
T and a transparent pixel electrode ITO1 are formed, and a color filter FIL and a light-blocking black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side.
The upper and lower transparent glass substrates SUB2, 1 are, for example, 1.1 m
m, and a silicon oxide film SIO is formed on both surfaces thereof by dipping or the like. Therefore, even if the surfaces of the transparent glass substrates SUB1 and SUB2 have fine scratches, the surface is flattened by the coating of the silicon oxide film SIO, and the scanning signal lines GL, light-shielding films (black matrix) BM and the like are formed thereon. Film quality can be kept uniform.

A light shielding film BM and a color filter FI are provided on the inner surface (the liquid crystal LC side) of the upper transparent glass substrate SUB2.
L and an upper alignment film ORI2 are sequentially laminated.

FIG. 8 shows a liquid crystal panel PN including upper and lower transparent glass substrates SUB2 and SUB1.
FIG. 9 is a plan view showing the periphery of the matrix AR shown in FIG. 8 in an exaggerated manner, and FIG. 10 is a plan view showing the periphery of the matrix AR shown in FIG. It is an enlarged plan view near the corresponding seal part SL. Also,
FIG. 11 is a cross-sectional view of FIG.
a cross-sectional view along the line a-19a, a cross-sectional view near the external connection terminal DTM to which the video signal line driving circuit is to be connected on the right side,
FIG. 12 is a cross-sectional view near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross-sectional view near the seal portion where there is no external connection terminal on the right side.

In the production of this liquid crystal panel, if the size is small, a plurality of glass substrates are simultaneously processed and then separated for improving the throughput. After processing a glass substrate of a standardized size even in a variety, the size is reduced to a size suitable for each type, and in each case, the glass substrate is cut after passing through a single process.

FIGS. 8 to 10 show the latter example. In both FIGS. 8 and 9, the upper and lower glass substrates SUB2 and SU
FIG. 10 shows the state after the cutting of B1, and FIG. 10 shows the state before the cutting. LN indicates the edge of the cutting line of the glass substrate, and CT1 and CT2 indicate the positions where the glass substrates SUB1 and SUB2 are to be cut.

In any case, in the completed state, the portions (the upper and lower sides and the left side in the figure) where the external connection terminal groups Tg and Td (subscripts are omitted) have a size of the upper glass substrate SUB2 such that they are exposed. It is limited inside the lower glass substrate SUB1.

The external connection terminal groups Tg and Td include a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, respectively, and a lead-out wiring portion thereof, which are described later.
Tape carrier package TCP (see FIG. 1)
3, see FIG. 14). The lead wiring from the matrix part of each group to the external connection terminal part is inclined as approaching both ends. This is because the terminals DTM and GTM of the liquid crystal panel PNL correspond to the arrangement pitch of the tape carrier package TCP and the connection terminal pitch of each tape carrier package TCP.
It is in order to match.

Between the transparent glass substrates SUB1 and SUB2, except for the liquid crystal sealing opening INJ along the edge thereof, the liquid crystal LC
Is formed so as to seal the sealing pattern SL (hereinafter, also referred to as a sealing material). The material of this seal pattern is made of, for example, epoxy resin. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the lead-out wiring INT formed on the lower transparent glass substrate SUB1 side by a silver paste material AGP at four corners of the liquid crystal panel at this point. This lead-out wiring INT has a gate terminal GTM and a drain terminal D which will be described later.
It is formed in the same manufacturing process as TM.

The layers of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO1, and the common transparent pixel electrode ITO2 are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are each a lower transparent glass substrate SUB
1. Formed on the outer surface of the upper transparent glass substrate SUB2.

The liquid crystal LC is sealed in a region partitioned by a seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 for setting the direction of the liquid crystal molecules. The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side to form a seal pattern SL on the upper transparent glass substrate SUB2 side.
1 and the upper transparent glass substrate SUB2 are superimposed, and liquid crystal is injected from the opening INJ (injection port) of the sealing material SL.
The inlet INJ is sealed with an epoxy resin or the like, and is assembled by cutting the upper and lower transparent glass substrates.

<< Thin Film Transistor TFT >> The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is reduced to zero, the channel resistance increases.

The thin film transistor TFT of each pixel is divided into two (a plurality) in the pixel, and is constituted by thin film transistors (divided thin film transistors) TFT1 and TFT2. Thin film transistor TFT1 and TFT
Each of the two has substantially the same size (channel length and channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 is
Gate electrode GT, gate insulating film GI, i-type (intrinsic, in
(Trinsic, not doped with conductivity type determining impurities) i-type semiconductor layer A made of amorphous silicon (Si)
S, a pair of a source electrode SD1 and a drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, and therefore, it should be understood that the source and the drain are switched during the operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.

<< Gate Electrode GT >> The gate electrode GT is shown in FIG.
As shown in FIG. 6 (a plan view depicting only the second conductive film g2 and the i-type semiconductor layer AS in FIG. 5), the shape protrudes in the vertical direction (upward in FIGS. 4 and 15) from the scanning signal line GL. (Branched into a T-shape).

The gate electrode GT is a thin film transistor TFT
1, and project beyond the respective active areas of the TFT2. The respective gate electrodes GT of the thin film transistors TFT1 and TFT2 are formed continuously. Here, the gate electrode GT is formed of a single-layer second conductive film g2. As the second conductive film g2, for example, an aluminum (Al) film formed by sputtering is used, and 1000 to 55 is used.
It is formed with a thickness of about 00 °. Further, an anodic oxide film AOF of aluminum is provided on the gate electrode GT.

As shown in FIGS. 4, 5 and 15, this gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below).
Therefore, when a backlight BL such as a fluorescent tube is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of this opaque aluminum film becomes a shadow, and light from the backlight is applied to the i-type semiconductor layer AS. The conductive phenomenon caused by light irradiation, that is, the thin film transistor T
Deterioration of the off characteristic of the FT hardly occurs. Note that the original size of the gate electrode GT is the minimum necessary for straddling between the source electrode SD1 and the drain electrode SD2 (the alignment margin between the gate electrode GT, the source electrode SD1, and the drain electrode SD2). The width of the source electrode SD1 and the depth of the drain electrode S1 determine the channel width W.
It is determined by the ratio to the distance (channel length) L from D2, that is, the factor W / L that determines the transconductance gm. The size of the gate electrode GT in this liquid crystal display device is, of course, made larger than the original size described above.

<< Scanning Signal Line GL >> The scanning signal line GL is
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is formed integrally. Further, an anodic oxide film AOF of aluminum Al is provided also on the scanning signal line GL.

<< Insulating Film GI >> The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 and TFT2. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. The insulating film GI is formed using a silicon nitride film formed by, for example, plasma CVD and having a thickness of 1200 to 2700 ° (about 2000 ° in this liquid crystal display device). As shown in FIG. 10, the gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion is formed with external connection terminals DTM,
It has been removed to expose the GTM.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
Are used as channel formation regions of the thin-film transistors TFT1 and TFT2 divided as shown in FIG. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film.
It is formed with a thickness of 0 ° (about 200 ° in this liquid crystal display device).

The i-type semiconductor layer AS is formed by changing the composition of the supply gas and forming the insulating film GI used as the gate insulating film made of Si ₂ N ₄ by the same plasma CVD.
It is formed by an apparatus and without being exposed to the outside from the plasma CVD apparatus.

An N (+) type semiconductor layer d0 doped with 2.5% of phosphorus (P) for ohmic contact is used.
(FIG. 5) is similarly formed continuously with a film thickness of 200 to 500 ° (about 300 ° in this liquid crystal display device). Thereafter, the lower transparent glass substrate SUB1 is taken out of the CVD apparatus and N (+)
The type semiconductor layer d0 and the i-type semiconductor layer AS are patterned into independent island shapes as shown in FIG. 4, FIG. 5, and FIG.

As shown in FIGS. 4 and 15, the i-type semiconductor layer AS is also provided between both intersections (crossover portions) between the scanning signal lines GL and the video signal lines DL.
The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Transparent Pixel Electrode ITO1 >> Transparent Pixel Electrode I
TO1 forms one of the pixel electrodes of the liquid crystal panel. The transparent pixel electrode ITO1 is connected to both the source electrode SD1 of the thin film transistor TFT2 and the source electrode SD1 of the thin film transistor TFT2. For this reason, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by a laser beam or the like, and if not, the other thin film transistor operates normally. You can leave it. The two thin film transistors TFT1, TFT1
It is seldom that defects occur simultaneously in the image data 2 and the probability of occurrence of point defects and line defects can be extremely reduced by such a redundant system.

The transparent pixel electrode ITO1 is composed of the first conductive film d1. This first conductive film d1 is a transparent conductive film (Indium-Tin) formed by sputtering.
-Oxide ITO: Nesa film)
A film thickness of 2000 ° ((1400 in this liquid crystal display device)
(Å film thickness).

<< Source electrode SD1, Drain electrode SD
2 >> Thin-film transistors TFT1, TF divided into a plurality
Source electrode SD1 and drain electrode SD of T2
2, as shown in FIG. 4, FIG. 5, and FIG. 16 (a plan view depicting only the first to third conductive films d1 to d3 of FIG. 4),
They are provided separately on the i-type semiconductor layer AS.

Each of the source electrode SD1 and the drain electrode SD2 is formed by sequentially stacking a second conductive film d2 and a third conductive film d3 from the lower side in contact with the N (+) type semiconductor layer d0. Second conductive film d of source electrode SD1
The second and third conductive films d3 are the second conductive films d3.
It is formed in the same manufacturing process as the conductive film d2 and the third conductive film d3.

The second conductive film d2 is formed of a chromium (Cr) film formed by sputtering, and has a thickness of 500 to 1000 Å (about 600 膜厚 in this liquid crystal display device). The Cr film is aluminum A of a third conductive film d3 described later.
A so-called barrier layer for preventing l from diffusing into the N (+) type semiconductor layer d0 is formed. Cr as the second conductive film d2
In addition to the film, a film of a high melting point metal (Mo, Ti, Ta, W, etc.), a high melting point metal silicide (MoSi ₂ , TiSi ₂ ,
TaSi ₂ , WSi _2, etc.) can also be used.

The third conductive film d3 is formed to a thickness of 3000 to 5000 ° (about 4000 ° in this liquid crystal display device) by sputtering of aluminum Al. The aluminum Al film has a smaller stress than the chromium Cr film and can be formed in a thick film.
It is configured to reduce the resistance values of D1, the drain electrode SD2, and the video signal line DL. As the third conductive film d3, an aluminum film containing silicon or copper (Cu) as an additive in addition to normal aluminum can be used.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, using the same mask or using the second conductive film d2 and the third conductive film d3 as a mask, an N (+) type The semiconductor layer d0 is removed. That is, in the N (+)-type semiconductor layer d0 remaining on the i-type semiconductor layer AS, portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, since the N (+)-type semiconductor layer d0 is etched so as to remove all of its thickness, the i-type semiconductor layer AS is also slightly etched at its surface. What is necessary is just to control by processing time.

The source electrode SD1 is a transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 is formed by a step of the i-type semiconductor layer AS (the thickness of the second conductive film d2, the anodic oxide film AOF).
, The thickness of the i-type semiconductor layer AS, and the thickness of the N (+)-type semiconductor layer d0). Specifically, the source electrode SD1 is i
Conductive film d formed along the step of the semiconductor layer AS
2 and a third conductive film d3 formed on the second conductive film d2. Since the third conductive film d3 of the source electrode SD1 cannot increase the thickness of the Cr film of the second conductive film d2 due to an increase in stress and cannot climb over the step of the i-type semiconductor layer AS, the third conductive film d3 needs to get over the i-type semiconductor layer AS. It is configured. That is, the step coverage is improved by increasing the thickness of the third conductive film d3. Third conductive film d3
Can be formed thick, which greatly contributes to a reduction in the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).

<< Protective Film PSV1 >> Thin Film Transistor TF
A protective film PSV1 is provided on T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture, and a film having high transparency and good moisture resistance is used. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD device, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

As shown in FIG. 10, the protective film PSV1 is formed so as to surround the entire matrix portion AR, the peripheral portion is removed so as to expose the external connection terminals DTM and GTM, and the upper transparent glass substrate is formed. Common electrode C of SUB2
The portion connecting the OM to the external connection terminal connection lead-out wiring INT of the lower transparent glass substrate SUB1 with the silver paste AGP is also removed. Regarding the thickness relationship between the protective film PSV1 and the gate insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner in consideration of the transconductance gm of the transistor. Therefore, as shown in FIG. 10, the protection film PSV1 having a high protection effect is formed to be larger than the gate insulating film GI so as to protect the peripheral portion as much as possible.

<< Light-shielding film BM >> Upper transparent glass substrate SUB
On the second side, a light-shielding film BM is provided so that external light (light from above in FIG. 5) does not enter the i-type semiconductor layer AS used as a channel formation region. The light-shielding film BM has a pattern as shown by hatching in FIG. FIG. 17 is a view showing a first example of the ITO film shown in FIG.
FIG. 3 is a plan view illustrating only a conductive film d1, a color filter FIL, and a light shielding film BM.

The light-shielding film BM has a high light-shielding property against light,
For example, it is formed of an aluminum film, a chromium film, or the like. In this liquid crystal display device, the chromium film is formed by sputtering at 130
It is formed to a thickness of about 0 °.

Therefore, the thin film transistors TFT1, TFT1
The i-type semiconductor layer AS of the TFT 2 is sandwiched by the upper and lower light shielding films BM and the large gate electrode GT, and the portion is not exposed to external natural light or backlight light. As shown by hatching in FIG. 17, the light-shielding film BM is formed around the pixels, that is, the light-shielding film BM is formed in a lattice shape (a so-called black matrix), and an effective display area of one pixel is partitioned by the lattice. ing. With the light-shielding film BM, the outline of each pixel is clear, and the contrast is improved. That is, the light shielding film BM is formed of the i-type semiconductor layer AS.
And a black matrix.

Since the portion (lower right portion in FIG. 4) of the transparent pixel electrode ITO1 facing the edge on the root side in the rubbing direction is shielded from light by the light shielding film BM, even if a domain is generated in the above portion. Since the domain is not visible, the display characteristics do not deteriorate.

The backlight may be attached to the upper transparent glass substrate SUB2 side, and the lower transparent glass substrate SUB1 may be set to the observation side (exposed side).

The light-shielding film BM is also formed in a peripheral portion in a frame-shaped pattern as shown in FIG. 11, and the pattern is continuous with the pattern of the matrix portion shown in FIG. It is formed. As shown in FIGS. 9 to 12, the peripheral light-shielding film BM is extended outside the seal portion SL to prevent leakage light such as reflected light due to a mounting device such as a personal computer from entering the matrix portion. I have.
On the other hand, the light-shielding film BM is fixed about 0.3 to 1.0 mm inside the edge of the upper transparent glass substrate SUB2, and is formed so as to avoid the cutting region of the upper transparent glass substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed by coloring a dye on a dye base made of a resin material such as an acrylic resin. Color filter F
The IL is formed in a stripe shape at a position facing the pixel (FIG. 18) and is dyed separately (FIG. 18 is the first in FIG. 7).
Only the conductive film d1, the light shielding film BM, and the color filter FIL are drawn, and each of the R, G, and B color filters FI is drawn.
L is hatched with 45 ° and 135 ° crosses, respectively. As shown in FIGS. 17 and 18, the color filter FIL is formed to be large so as to cover the entire transparent pixel electrode ITO1, and the light shielding film BM is formed of the color filter FIL.
Further, it is formed inside the periphery of the transparent pixel electrode ITO1 so as to overlap with the edge portion of the transparent pixel electrode ITO1.

The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, by performing similar steps, a green filter G and a blue filter B are sequentially formed.

<< Protective Film PSV2 >> The protective film PSV2 is composed of a liquid crystal L which is a dye obtained by dyeing the color filter FIL into different colors.
It is provided to prevent leakage to C. The protective film PSV2 is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin.

<< Common Transparent Pixel Electrode ITO2 >> The common transparent pixel electrode ITO2 is opposed to the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is determined by each pixel electrode ITO1. In response to a potential difference (electric field) between the pixel electrode and the common transparent pixel electrode ITO2. A common voltage V is applied to the common transparent pixel electrode ITO2.
com is applied. In this,
The common voltage Vcom includes a low-level driving voltage Vdmin and a high-level driving voltage Vd applied to the video signal line DL.
Although it is set to an intermediate potential with respect to dmax, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal driving circuit to about half, an AC voltage may be applied. The plan shape of the common transparent pixel electrode ITO2 should be referred to FIG. 9 and FIG.

<< Gate Terminal >> FIG. 19 shows a state where the scanning signal line GL of the display matrix part of the liquid crystal pattern is connected to the external connection terminal G.
It is explanatory drawing of the connection structure to TM, (A) is a top view,
(B) is a sectional view taken along line BB of (A). This drawing corresponds to the vicinity of the lower part of FIG. 10, and the diagonal wiring portion is represented by a straight line for convenience.

AO is a mask pattern for photo processing, in other words, a photoresist pattern of selective anodic oxidation. Therefore, this photoresist is removed after anodic oxidation, and the pattern AO shown in the figure does not remain as a finished product, but an oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view of FIG. So that the trajectory remains. In the plan view of (A), the boundary line A of the photoresist is shown.
With reference to O, the left side is a region covered with the resist and not subjected to anodization, and the right side is a region exposed from the resist and anodized. The oxide AAl ₂ O ₃ film AOF is formed on the surface of the anodized aluminum Al layer g2, and the volume of the lower conductive portion is reduced. Of course, anodic oxidation is performed by setting an appropriate time, voltage and the like so that the conductive portion remains. The mask pattern AO does not intersect the scanning signal line GL with a single straight line, but intersects by bending in a crank shape.

In the figure, the aluminum Al layer g2 is hatched for easy understanding, but the region not anodized is patterned in a comb shape. this is,
If the width of the aluminum Al layer is large, whiskers are generated on the surface. Therefore, the width of each one is narrowed, and by arranging a plurality of them in parallel, the occurrence of whiskers is prevented while preventing the occurrence of disconnections. The goal is to minimize sacrifices in probability and conductivity. Therefore, here, the portion corresponding to the root of the comb is also shifted along the mask AO.

The gate terminal GTM has good adhesion to the silicon oxide SIO layer, and has a chromium Cr layer g1 having higher corrosion resistance than aluminum Al.
Transparent conductive layer d1 at the same level (same layer, simultaneous formation) as TO1
It is composed of The conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof are formed so that the conductive layers g2 and g1 are not etched together due to a pinhole or the like at the time of etching the conductive layers d2 and d3. This remains as a result of covering the area with photoresist. In addition, the ITO layer d1 extending rightward beyond the gate insulating film GI is a thorough countermeasure.

In the plan view of FIG. 19A, the gate insulating film GI has a protective film PSV1 on the right side of the boundary line.
Are formed on the right side of the boundary line, and the terminal portion GTM located on the left side is exposed therefrom so as to be able to make electrical contact with an external circuit. Although only one pair of the gate line GL and the gate terminal is shown in FIG. 12, a plurality of such pairs are actually arranged vertically as shown in FIG. 10), and the left side of the gate terminal is a cutting region CT1 of the substrate in the manufacturing process.
And is short-circuited by the wiring SHg. Such a short-circuit line SHg in the manufacturing process has an effect of supplying power during anodization (at the time of anodizing treatment) and preventing electrostatic breakdown generated at the time of rubbing of the alignment film ORI1 or the like.

<< Drain Terminal DTM >> FIGS. 20A and 20B are explanatory diagrams of the connection from the video signal line DL to the external connection terminal DTM. FIG. 20A is a plan view, and FIG. 20B is a BB line of FIG. FIG. FIG. 20 corresponds to the vicinity of the upper right of FIG. 10, and the direction of the drawing is changed for convenience, but the right end direction is the upper end (or lower end) of the lower transparent glass substrate SUB1.
Corresponds to.

TSTd is an inspection terminal, to which an external circuit is not connected, but is wider than a wiring portion so that a probe needle or the like can be contacted. Similarly, the width of the drain terminal DTM is wider than that of the wiring portion so as to enable connection with an external circuit. A plurality of test terminals TSTd and external connection terminals DTM are alternately arranged in a staggered manner in the vertical direction, and the test terminals TSTd are connected to the lower transparent glass substrate S as shown in the figure.
Although the terminal ends without reaching the end of UB1, the drain terminal DTM forms a terminal group Td (subscript omitted) as shown in FIG. 10 and crosses the cutting line CT1 of the lower transparent glass substrate SUB1. All of them are further extended, and all of them are short-circuited to each other by the wiring SHd in order to prevent electrostatic destruction during the manufacturing process. The drain connection terminal is connected to the opposite side of the matrix of the video signal line DL where the inspection terminal TSTd exists, and the video signal line DL where the drain terminal DTM exists
An inspection terminal is connected to the opposite side of the matrix. The drain terminal DTM is formed of the chromium Cr layer g1 and the ITO layer d1 for the same reason as the gate terminal GTM.
It is formed of a layer, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. Gate insulating film GI
The semiconductor layer AS formed on the end of the gate insulating film GI
For etching the video signal in a tapered shape. On the drain terminal DTM, of course, the protective film PSV1 is removed for connection with an external circuit. AO
Is the anodized mask described above, and the mask is covered on the left side from the boundary line. However, since the layer g2 does not exist in the portion not covered in this figure, this pattern is not directly related.

As shown in FIG. 11C, the lead-out wiring from the matrix portion to the drain terminal DTM portion is connected to the video signal line DL immediately above the layers d1 and g1 at the same level as the drain terminal DTM portion. Although the layers d2 and d3 of the same level are stacked halfway through the seal pattern SL, this is to minimize the probability of disconnection and to replace the aluminum Al layer d3 which is easily corroded with the protective film PSV1 and the seal pattern SL. The aim is to protect as much as possible with SL.

<< Structure of Storage Capacitor Cadd >> The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. This superposition is shown in FIG.
As is clear from FIG. 8, a storage capacitor element (capacitance element) Cadd in which the transparent pixel electrode ITO1 is one electrode PL2 and the adjacent scanning signal line GL is the other electrode PL1.
Is configured. The dielectric film of the storage capacitor Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As is apparent from FIG. 15, the storage capacitance element Cadd is formed in a portion of the scanning signal line GL where the width of the second conductive film g2 is increased. The portion of the second conductive film g2 that intersects with the video signal line DL is thinned to reduce the probability of the video signal line DL and its short circuit.

In the step portion of the electrode PL1 of the storage capacitor element Cadd, even if the transparent pixel electrode ITO1 is disconnected, the second conductive film d2 and the third conductive film d3 are formed so as to straddle the step. The fault is compensated by the island region.

<< Equivalent Circuit of Entire Display Device >> FIG. 21 is a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
This figure is a circuit diagram, but is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and suffixes G, B and R are added corresponding to green, device and red pixels, respectively. Y means the scanning signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The video signal line X (subscript omitted) is connected to the upper video signal drive circuit He. That is, similarly to the scanning signal line Y, the video signal line X is connected to the video signal panel PNL.
The terminal is drawn out only on one side.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP uses a TFT liquid crystal display device to transfer information from a power supply circuit for obtaining a stabilized voltage source by dividing the voltage from one voltage source to a plurality and a CRT (cathode ray tube) from a host (upper processing unit). This is a circuit that includes a circuit that exchanges information for use.

<< Equivalent Circuit of Storage Capacitor Cadd and Its Operation >> FIG. 22 is an equivalent circuit diagram of the pixel shown in FIG.
In FIG. 22, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film of the parasitic capacitance element Cgs is the insulating film GI and the anodic oxide film AOF. Cpix is a transparent pixel electrode ITO1 (PIX) and a common transparent pixel electrode ITO2.
(COM). The dielectric film of the liquid crystal capacitor Cpix is the liquid crystal LC, the protective film PSV1, and the alignment films ORI1 and ORI2. V1c is a midpoint potential.

The capacitance of the storage capacitance element Cadd (the storage capacitance C
add) works to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) V1c when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔV1c = ｛Cgs / (Cgs + Cadd)
+ Cpix)｝ × ΔVg Here, ΔV1c represents a change in the midpoint potential due to ΔVg. The change ΔV1c causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance Cadd is increased. In addition, the storage capacitance element Cadd also has a function of prolonging the discharge time, and stores video information after the thin film transistor TFT is turned off for a long time. The reduction of the DC component applied to the liquid crystal LC
, The so-called image sticking, in which the previous image remains when the liquid crystal display screen is switched, can be reduced.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. , The midpoint potential V1c is easily affected by the gate (scanning) signal Vg. However, the storage capacitor Ca
By providing dd, this disadvantage can be eliminated.

The storage capacitor Cadd of the storage capacitor Cadd
Is 4 to the liquid crystal capacitance Cpix from the writing characteristics of the pixel.
８8 times (4 · Cpix <Cadd <8 · Cpix), and 8 to 32 times (8 · Cgs <Cad) with respect to the parasitic capacitance Cgs.
d <32 · Cgs).

<< Connection Method of Storage Capacitor Cadd Electrode Line >> As shown in FIG. 21, the first-stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line has a common transparent pixel electrode ITO2 (Vcom). ) To the same potential. FIG.
In the example shown in FIG. 0, the first-stage scanning signal line is short-circuited to the common electrode COM through the terminal GTO, the lead line INT, the terminal DT0, and the external wiring. Alternatively, the first-stage storage capacitor electrode line Y ₀ is connected to the last-stage scanning signal line Yend, connected to a DC potential point (AC ground point) other than Vcom, or one extra scanning pulse Y from the vertical scanning circuit V. _It may be connected to receive ₀ .

<< Connection Structure with External Circuit >> As shown in FIG. 13, the tape carrier package TCP includes an integrated circuit chip CHI constituting the scanning signal driving circuit V and the video signal driving circuits He and Ho, and a flexible wiring board ( Commonly known as TA
B; Tape, Automated Bonding)
FIG. 14 shows a state where this is connected to a video signal circuit terminal DTM of the video signal panel PNL.

TB is an input terminal / wiring portion of the integrated circuit CHI, and TM is an output terminal / wiring portion of the integrated circuit CHI.
A bonding pad PAD of the integrated circuit CHI is connected to each inner end portion (commonly referred to as an inner lead) by a so-called face-down bonding method. Terminal T
B, the outer end portions (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively, and the liquid crystal is formed by the anisotropic conductive film ACF on the CRT / TFT conversion circuit / power supply circuit SUP by soldering or the like. Panel PN
It is connected to the liquid crystal panel so as to cover the protective film PSV1 exposing the connection terminal DTM on the L side. Therefore, the external connection terminal DTM (GTM) is covered with at least one of the protective film PSV1 and the tape carrier package TCP.
It becomes strong against electric corrosion.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX or the like after cleaning, and the tape carrier package TCP and the upper transparent glass substrate S
Between UB2, silicone resin SIL is further filled to multiplex protection.

<< Manufacturing Method >> Next, a method of manufacturing the lower transparent glass substrate SUB1 side of the liquid crystal display device will be described with reference to FIGS. In each figure, the middle letter is the abbreviation of the process name, the left side shows the pixel portion shown in FIG. 5, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal shown in FIG. Except for the process D, the processes A to I are classified according to the respective photographic processes, and all the cross-sectional views of the respective processes show the stage where the processing after the photographic process is completed and the photoresist is removed. I have.
Note that photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description thereof will be omitted. Less than,
A description will be given according to the divided steps.

[0117]Step A (FIG. 23) Lower transparent glass substrate made of 7059 glass (trade name)
Dip processing of silicon oxide film SIO on both sides of SUB1
Baking at 500 ° C for 60 minutes.
U. The film thickness is 1100 on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium (Cr) is sputtered.
After photo processing, nitric acid
Selectively select first conductive film g1 with 2 cerium ammonium solution
And the gate terminal GTM and the drain terminal DT
M, anodizing bus line S connecting gate terminal GTM
Hg, bus line SH for shorting drain terminal DTM
d, the anodizing pattern connected to the anodizing bus line SHg
A pad (not shown) is formed. Step B (FIG. 23) Al-Pd, Al-Si, Al-S with a thickness of 2800 °
Second conductive film g2 made of i-Ta, Al-Si-Cu, or the like
Is provided by sputtering. After photographic processing,
Etch the second conductive film g2 with a mixed acid solution of nitric acid and glacial acetic acid
To

Step C (FIG. 23) After photographic processing (after formation of the above-described anodic oxidation mask AO), 3
% Tartaric acid was adjusted to pH 6.25 ± 0.05 with ammonia, and the lower transparent glass substrate SUB was placed in an anodic oxidation solution consisting of a solution diluted 1: 9 with an ethylene glycol solution.
1 is immersed and adjusted (constant current formation) so that the formation current density becomes 0.5 mA / cm ² . Next, a predetermined Al ₂ O
₃ Anodizing is performed until the formation voltage 125 V necessary for obtaining the film thickness is reached. Thereafter, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is because the uniform Al
_This is important for obtaining a ₂ O ₃ film. Thereby,
The conductive film g2 is anodized to form an anodic oxide film AOF having a thickness of 1800 ° on the scanning signal line GL, the gate electrode GT, and the electrode PL1.

Step D (FIG. 24) Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 2000-nm thick Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus. After providing an i-type amorphous Si film having a thickness of 2000 °, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus to form an N (+)-type amorphous Si film having a thickness of 300 °.

Step E (FIG. 24) After photographic processing, SF ₆ , CC are used as dry etching gases.
Using l ₄ , an N (+)-type amorphous Si film and an i-type amorphous S
By selectively etching the i-film, islands of the i-type semiconductor layer AS are formed.

Step F (FIG. 24) After the photographic processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Step G (FIG. 25) A first conductive film d1 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form

Step H (FIG. 25) A second conductive film d2 made of chromium chromium having a thickness of 600 ° is provided by sputtering, and further a Al-Pd, Al-Si, Al-Si-Ti, Al- S
A third conductive film d3 made of i-Cu or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as in the step B, the second conductive film d2 is etched with the same liquid as in the step A, and the video signal line DL and the source electrode SD are etched.
1. The drain electrode SD2 is formed. Next, by introducing CCl ₄ and SF ₆ into a dry etching apparatus and etching the N (+)-type amorphous Si film, the N (+)-type semiconductor layer d0 between the source and the drain is selectively formed. Remove.

Step I (FIG. 25) An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to form a 1 μm-thick Si nitride film. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo etching technique (photolithography technique) using SF ₆ as a dry etching gas.

An alignment film is formed on the innermost surface of the lower transparent glass substrate SUB1 manufactured in this way, and the upper transparent glass substrate SUB2 manufactured in a separate manufacturing process is bonded. The liquid crystal panel PNL is obtained by sandwiching and sealing with a sealing material, and attaching polarizing plates (POL1, POL2) on both sides.

As described with reference to FIG. 3, this liquid crystal panel PNL is laminated with a backlight and other optical films and the like, and various drive circuit boards are incorporated into a liquid crystal display device (liquid crystal display module).

FIG. 26 is a plan view showing a state where the liquid crystal panel and the drive circuit board are connected. CHI is liquid crystal panel P
An integrated circuit (IC) chip for driving the NL (the lower five ICs on the vertical scanning circuit side and the left ten ICs on the video signal driving circuit side).

As shown in FIG. 13 and FIG.
A tape carrier package (TCP) in which an IC chip CHI of a drive circuit is mounted by a tape automated bonding (TAB) method, and a PCB1 is a drive circuit board on which the above-described TCP and capacitors are mounted. It is divided into two for the drive circuit.

FGP is a frame ground pad.
A spring-shaped fragment provided by cutting into the shield case SHD is soldered. FC is the lower drive circuit board PC
This is a flat cable for electrically connecting B1 to the left drive circuit board PCB1.

As shown in the figure, as the flat cable FC, a plurality of lead wires (phosphor bronze material plated with Sn) were supported by being sandwiched between a striped polyethylene layer and a polyvinyl alcohol layer. Use things.

<< TCP Connection Structure >> FIG. 13 is a sectional view of a tape carrier package in which an integrated circuit chip CHI constituting the scanning signal driving circuit V and the video signal driving circuit H is mounted on a flexible wiring board. FIG. 4 is a sectional view of a main part of the liquid crystal panel, here showing a state connected to a scanning signal circuit terminal GTM.

TTB is an input terminal / wiring portion of the integrated circuit chip CHI, and TTM is an output terminal / wiring portion of the integrated circuit chip CHI. The TTM is made of, for example, Cu. As described above, the bonding pads PAD of the integrated circuit chip CHI are connected by a so-called face-down bonding method.

The outer ends (outer leads) of the terminals TTB and TTM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
As described above, the RT / TFT conversion circuit / power supply circuit SUP is connected to the liquid crystal panel PNL by the anisotropic conductive film ACF.

The package TCP has a protective film PSV whose leading end exposes the connection terminal GTM on the liquid crystal panel PNL side.
1 is connected to the liquid crystal panel PNL so as to cover the liquid crystal panel PNL. Therefore, the outer connection terminal GTM (DTM) is connected to the protective film PSV1.
Is covered with at least one of the package TCPs, and thus is resistant to electrolytic corrosion.

As described above, BF1 is a base film made of a resin such as polyimide, and SRS is a solder resist film for masking so that solder does not adhere to unnecessary portions during soldering. Seal pattern SL
The gap between the upper and lower transparent glass substrates on the outside is protected by an epoxy resin EPX or the like after cleaning, and a silicon resin SI is further provided between the package TCP and the upper transparent glass substrate SUB2.
L is filled and protection is multiplexed.

<< Drive Circuit Board PCB2 >> Drive Circuit Board P
Electronic components such as an IC, a capacitor, and a resistor are mounted on the CB2. As described above, this drive circuit board PC
B2 is equipped with a power supply circuit for dividing the voltage from one voltage source to obtain a plurality of stabilized voltage sources, and a circuit SUP including a circuit for converting CRT information from the host into information for the liquid crystal display device. Have been. CJ is a connector connecting portion for a connector (not shown) connected to the outside.

The drive circuit board PCB1 and the drive circuit board PC
B2 is electrically connected by a joiner JN such as a flat cable FC.

FIG. 27 is an external view of a notebook personal computer as an example of an electronic device on which the liquid crystal display device according to the present invention is mounted.

In this notebook personal computer, a keyboard unit and a display unit are connected by a hinge, and the keyboard unit has a CP.
A host computer made of a U or the like is mounted, and the liquid crystal display device according to the present invention is mounted on a display unit as a liquid crystal display module (MDL).

Driving circuit boards PCB1, PCB1 are provided around the liquid crystal panel PNL constituting the liquid crystal display module.
2, a PCB 3, an inverter power supply IV for backlight, and the like. Note that CT is a connector connected to the host, and TCON is a control circuit that generates signal processing for displaying an image on the liquid crystal panel PNL and a timing signal based on a display signal input from the host.

The liquid crystal display device according to the present invention can be used not only for a portable personal computer such as a notebook type as shown in FIG. Needless to say.

The present invention is not limited to the application of the above-described driving IC (integrated circuit chip) to a vertical electric field type active matrix type liquid crystal display device using TCP, but to a horizontal electric field type active matrix type liquid crystal display device. Chip-on-glass type liquid crystal display device in which a driving IC is directly mounted on one substrate of a liquid crystal display device or a liquid crystal panel. Alternatively, the present invention can be similarly applied to a simple matrix type liquid crystal display device.

[0143]

As described above, according to the present invention,
Provided is a liquid crystal display device capable of displaying a high-quality image by preventing the occurrence of luminance unevenness due to the notch of a backlight using a light guide plate having a notch at least on the installation side of the linear lamp. Can be.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a backlight illustrating a schematic structure of a first embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is an enlarged schematic view of a portion A in FIG. 1 for explaining effects in the embodiment of the present invention.

FIG. 3 is an exploded perspective view illustrating an overall configuration of an embodiment of a liquid crystal display device according to the present invention.

FIG. 4 is a plan view showing one pixel and a light-shielding region of a black matrix BM and its periphery, which constitute an active matrix type color liquid crystal display device according to the present invention.

FIG. 5 is a cross-sectional view showing one pixel and its surroundings taken along section line 3-3 in FIG. 4;

FIG. 6 shows an additional capacitance element Ca taken along the line 4-4 in FIG. 4;
It is sectional drawing of dd.

FIG. 7 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels of FIG. 4 are arranged.

FIG. 8 is a plan view for explaining a configuration of a matrix peripheral portion of the display panel.

FIG. 9 is a plan view for a more specific explanation by slightly exaggerating the peripheral portion of FIG. 8;

FIG. 10 is an enlarged plan view of a corner of a liquid crystal panel including an electrical connection between upper and lower transparent glass substrates.

FIG. 11 is a cross-sectional view showing the vicinity of a corner of a liquid crystal panel and the vicinity of a video signal terminal on both sides with a pixel portion of a matrix in the center.

FIG. 12 is a cross-sectional view showing a scanning signal terminal on the left side and a liquid crystal panel edge portion without an external connection terminal on the right side.

FIG. 13 is a cross-sectional view showing a structure of a tape carrier package in which an integrated circuit chip constituting a driving circuit is mounted on a flexible wiring board.

FIG. 14 is a cross-sectional view of a main part showing a state where the tape carrier package is connected to a video signal circuit terminal of the liquid crystal panel.

FIG. 15 is a plan view illustrating only a conductive layer g2 and an i-type semiconductor layer AS of the pixel illustrated in FIG. 4;

FIG. 16 shows conductive layers d1, d2, and d3 of the pixel shown in FIG.
It is the top view which drew only.

FIG. 17 is a plan view illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel illustrated in FIG. 4;

FIG. 18 is a plan view of an essential part showing only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel array shown in FIG. 7;

FIG. 19 is an explanatory diagram near a connection portion between a gate terminal and a gate wiring.

FIG. 20 is an explanatory diagram near a connection portion between a drain terminal and a video signal line.

FIG. 21 is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device.

FIG. 22 is an equivalent circuit diagram of the pixel shown in FIG.

FIG. 23 is an explanatory diagram of a manufacturing process on the lower transparent glass substrate side.

FIG. 24 is an explanatory view following FIG. 23 of the manufacturing process for the lower transparent glass substrate.

FIG. 25 is an explanatory view following FIG. 24 of the manufacturing process on the lower transparent glass substrate side;

FIG. 26 is a plan view showing a state where a liquid crystal panel and a drive circuit board are connected.

FIG. 27 is an external view of a notebook computer illustrating an example of an electronic device on which the liquid crystal display device of the present invention is mounted.

FIG. 28 is a schematic plan view illustrating a schematic structure of a conventional side edge type backlight.

FIG. 29 is an enlarged schematic diagram of a portion A in FIG. 28 for explaining the occurrence of uneven brightness.

[Explanation of symbols]

 LP Linear lamp (cold-cathode fluorescent tube) GLB Light guide plate Cut notch with curved wall SHD Shield case (metal frame) WD Display window INS1-3 Insulation sheet PCB1-3 Circuit board JN1-3 Joiner TCP1, TCP2 Tape carrier package PNL Liquid crystal display panel GC Rubber cushion ILS Light shielding spacer PRS Prism sheet SPS Diffusion sheet RFS Reflection sheet MCA Lower case (mold frame) MO MCA opening LPC Lamp cable GB Rubber bushing supporting fluorescent tube LP BAT Double-sided adhesive tape PJ Convex part BL backlight MDL Liquid crystal display (liquid crystal display module).

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H038 AA41 AA51 BA06 2H091 FA02Y FA23Z FA35Y FA41Z FB06 FC01 GA03 GA07 GA11 GA13 LA18 5G435 AA02 BB12 BB16 EE02 EE27 EE30 EE31 EE32 EE34 FF08 FF13 GG01H03 GG01GG

Claims (3)

[Claims] 1. A liquid crystal panel having a first substrate and a second substrate opposed to each other with a predetermined gap therebetween, and a periphery of a display area adhered with a sealant, and a liquid crystal layer sealed in the gap, and at least one of a light guide plate and a liquid crystal panel. A backlight comprising a linear lamp installed along a side edge and installed on the back of the liquid crystal panel to illuminate the liquid crystal panel from the back, and a mold member for holding a light guide plate constituting the backlight were provided. A liquid crystal display device, comprising: a notch having a curved wall at an end of the one side edge of the light guide plate facing the linear lamp. 2. The liquid crystal display device according to claim 1, wherein the light guide plate includes a cut-out portion having a curved wall as a light incident portion from the linear lamp. 3. The liquid crystal according to claim 1, wherein the cutout portion having a curved wall of the light guide plate is a space for installing the light guide plate or a fixing member of the liquid crystal display device. Display device.