JP2001091955A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a sealant from being released by improving the adhesive power of the sealant. SOLUTION: The liquid crystal display device is equipped with a pair of transparent substrates placed opposite to each other through a liquid crystal and the sealant, which sticks one transparent substrate to the other transparent substrate and encloses the liquid crystal. The surface of the transparent substrate on the side stuck to the sealant is roughened at least on a part of the sticking part of the sealant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art In a liquid crystal display device, a pair of transparent substrates disposed to face each other with a liquid crystal interposed therebetween is used as an envelope, and a display portion including a large number of pixels is formed in a direction in which the liquid crystal spreads.

[0006] The fixing of the other transparent substrate side to the one transparent substrate side is performed by a sealing material formed to surround the display portion and also to seal the liquid crystal.

[0004]

However, it has been pointed out that in the liquid crystal display device thus constructed, the sealing material may be peeled off due to impact or thermal stress applied thereto.

Further, it has been pointed out that contaminants from the sealing material may be dissolved in the liquid crystal and display defects may occur.

For this reason, it is preferable to use a sealing material that has a strong adhesive force and does not contaminate the liquid crystal.

However, it has been found that it is difficult to increase the adhesive strength when a sealing material is prepared using a material that does not contaminate the liquid crystal, giving priority to preventing the contamination of the liquid crystal.

[0008] The present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal display device having a seal material that is less likely to peel regardless of the type of material.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the liquid crystal display device according to the present invention comprises:
A pair of transparent substrates opposed to each other with a liquid crystal interposed therebetween, and a sealing material for sealing the liquid crystal together with the fixing of the other transparent substrate side to the one transparent substrate side, and the transparent substrate side to which the sealing material is bonded Is roughened at least in a part of the bonding portion of the sealing material.

In the liquid crystal display device configured as described above, the adhesive strength of the sealing material on the transparent substrate side is determined by the number and strength of the chemical bonds generated between the sealing material and the transparent substrate side.

In this case, since the rough surface is formed on the transparent substrate side, the contact area between the sealing material and the transparent substrate side increases, and the number of chemical bonds increases.

Therefore, when the same amount of the sealing material is applied, the adhesive force is increased, and the occurrence of peeling of the seal can be reduced.

Further, since it is possible to use a sealing material having a low adhesive strength and a small amount of liquid crystal contamination while ensuring high reliability, it is possible to improve display quality.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings described below, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

<< Active Matrix Liquid Crystal Display Device >> Hereinafter, an active matrix type color liquid crystal display device to which the present invention is applied will be described in detail.

<< Planar Configuration of Matrix Part (Pixel Part) >>
FIG. 1 is a plan view showing one pixel of an active matrix type color liquid crystal display device of the present invention and its periphery.

As shown in FIG. 1, each pixel has a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring) CL, and two adjacent video signal lines (drain). The signal line or the vertical signal line) is arranged in an intersecting region with the DL (in a region surrounded by four signal lines). Each pixel is a thin film transistor TFT, a storage capacitor Cst
g, the pixel electrode PX and the counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in FIG. Video signal line DL
Extend in the up-down direction and are arranged in a plurality in the left-right direction. The pixel electrode PX is connected to the thin film transistor TFT, and the counter electrode CT is integrated with the counter voltage signal line CL.

The pixel electrode PX and the counter electrode CT are opposed to each other, and the optical state of the liquid crystal LC is controlled by the electric field between each pixel electrode PX and the counter electrode CT to control the display. The pixel electrode PX and the counter electrode CT are formed in a comb shape, and each is an electrode that is elongated in the vertical direction in the figure.

<< Cross-Sectional Structure of Matrix (Pixel) >>
FIG. 2 is a view showing a cross section taken along line 3-3 in FIG.
Is a thin film transistor TFT along the section line 4-4 in FIG.
FIG. 4 is a view showing a cross section of the storage capacitor Cstg taken along the line 5-5 in FIG. As shown in FIGS. 2 to 4, the lower transparent glass substrate SUB is
A thin film transistor TFT, a storage capacitor Cstg, and an electrode group are formed on one side, and a color filter FIL and a light-shielding black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side.

Further, transparent glass substrates SUB1, SUB2
Are provided with alignment films ORI1 and ORI2 for controlling the initial alignment of the liquid crystal on the inner surface of each (liquid crystal LC side), and the polarizing axes are provided on the outer surfaces of the transparent glass substrates SUB1 and SUB2. A polarizing plate arranged orthogonally (crossed Nicols arrangement) is provided.

<< Thin Film Transistor TFT >> The thin film transistor TFT operates so that the channel resistance between the source and the drain decreases when a positive bias is applied to the gate electrode GT, and the channel resistance increases when the bias is reduced to zero.

As shown in FIG. 3, the thin film transistor TFT has a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic, intrinsic, not doped with conductivity type determining impurities) amorphous silicon (Si). Type semiconductor layer A
S, a pair of source electrode SD1 and drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are interchanged during the operation. However, in the following description, one is fixed and the other is fixed as a drain for convenience.

<< Gate Electrode GT >> The gate electrode GT is formed continuously with the scanning signal line GL.
Is configured to be a gate electrode GT. The gate electrode GT is a portion exceeding the active region of the thin film transistor TFT, and is formed larger than that so as to completely cover the i-type semiconductor layer AS (as viewed from below).

Thus, in addition to the role of the gate electrode GT, the device is designed so that external light and backlight do not hit the i-type semiconductor layer AS. In this example, the gate electrode GT
Is formed of a single-layer conductive film g1. As the conductive film g1, for example, aluminum (A
1) A film is used, on which an anodic oxide film AOF of Al
Is provided.

<< Scanning Signal Line GL >> The scanning signal line GL is formed of the conductive film g1. The conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, and is integrally formed. This scanning signal line G
L, the gate voltage Vg is applied from an external circuit to the gate electrode G.
Supply to T. An anodic oxide film AOF of Al is also provided on the scanning signal line GL. Note that the video signal line DL
The portion that intersects with the video signal line DL is made thin in order to reduce the probability of short-circuiting with the video signal line DL, and is made bifurcated so that even if it is short-circuited, it can be separated by laser trimming.

<< Counter Electrode CT >> The counter electrode CT is formed of a conductive film g1 in the same layer as the gate electrode GT and the scanning signal line GL. An Al anodic oxide film AOF is also provided on the counter electrode CT. Since the counter electrode CT is completely covered with the anodic oxide film AOF, even if the counter electrode CT is brought as close as possible to the video signal line, they are not short-circuited. Further, they may be configured to cross each other. The counter electrode CT is configured to apply a counter voltage Vcom. In this embodiment, the counter voltage Vcom is the minimum level drive voltage Vd applied to the video signal line DL.
From the intermediate DC potential between min and the maximum drive voltage Vdmax, the potential is set to a potential lower by a feedthrough voltage ΔVs generated when the thin film transistor element TFT is turned off, but is used in a video signal drive circuit. When it is desired to reduce the power supply voltage of the integrated circuit to about half, an AC voltage may be applied.

<< Counter voltage signal line CL >> Counter voltage signal line C
L is composed of the conductive film g1. The conductive film g1 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, the scanning signal line GL, and the counter electrode CT, and is formed integrally with the counter electrode CT. The opposing voltage signal line CL allows the opposing voltage Vcom
Is supplied to the counter electrode CT. Also, the counter voltage signal line CL
An anodic oxide film AOF of Al is also provided thereon. The portion that intersects with the video signal line DL is the scanning signal line GL.
In the same manner as described above, the width is made thinner in order to reduce the probability of short-circuiting with the video signal line DL, and it is made bifurcated so that even if it is short-circuited, it can be separated by laser trimming.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI includes the gate electrode GT and the scanning signal line GL.
Is formed in the upper layer. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected.
In a thickness of 200 to 2700 ° (in this embodiment, 2400
Å) formed. The gate insulating film GI is formed so as to surround the entire matrix part AR, and the peripheral part is removed so as to expose the external connection terminals DTM and GTM.
The insulating film GI includes the scanning signal line GL and the counter voltage signal line CL.
And the video signal line DL.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
Is amorphous silicon and is formed to a thickness of 200 to 2200 ° (in this embodiment, a film thickness of about 2000 °). The layer d0 is an N (+)-type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact. The i-type semiconductor layer AS is present on the lower side, and the conductive layer d1 (d
2) is left only where it exists.

The i-type semiconductor layer AS is also provided between the scanning signal line GL and the intersection (crossover portion) between the counter voltage signal line CL and the video signal line DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL at the intersection.

<< Source electrode SD1, drain electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is composed of a conductive film d1 in contact with the N (+) type semiconductor layer d0 and a conductive film d2 formed thereon.

The conductive film d1 uses a chromium (Cr) film formed by sputtering and is formed to a thickness of 500 to 1000 ° (about 600 ° in this embodiment). When the Cr film is formed with a large thickness, the stress becomes large.
The film is formed in a range not exceeding about 膜厚. Cr film is N
The adhesion to the (+) type semiconductor layer d0 is improved, and the conductive film d2 is formed.
Is used for the purpose of preventing Al from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). Conductive film d
In addition to the Cr film, refractory metals (Mo, Ti, T
a, W) film, refractory metal silicide (MoSi ₂ , Ti)
Si ₂ , TaSi ₂ , WSi ₂ ) film may be used.

The conductive film d2 has a thickness of 30
To a thickness of 00 to 5000 mm (in this embodiment, 4000 mm).
Degree) is formed. The Al film has a smaller stress than the Cr film and can be formed to have a large thickness, and can reduce the resistance values of the source electrode SD1, the drain electrode SD2 and the video signal line DL, and can reduce the gate electrode GT and the i-type semiconductor. Layer AS
Has the function of ensuring that the vehicle gets over a step (improves step coverage).

After patterning the conductive films d1 and d2 with the same mask pattern, the N (+) type semiconductor layer d0 is removed using the same mask or using the conductive films d1 and d2 as a mask. That is, the i-type semiconductor layer AS
The portion of the N (+) type semiconductor layer d0 remaining on the portion other than the conductive films d1 and d2 is removed by self-alignment. At this time, since the N (+)-type semiconductor layer d0 is etched so as to remove the entire thickness, the i-type semiconductor layer AS is also slightly etched at its surface, but the degree is controlled by the etching time. do it.

<< Video Signal Line DL >> The video signal line DL is composed of the second conductive film d2 and the third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2. The video signal line DL is formed integrally with the drain electrode SD2.

<< Pixel Electrode PX >> The pixel electrode PX is a second conductive film d of the same layer as the source electrode SD1 and the drain electrode SD2.
2, the third conductive film d3. Further, the pixel electrode PX is formed integrally with the source electrode SD1.

<< Storage Capacitor Cstg >> The pixel electrode PX is formed so as to overlap the counter voltage signal line CL at the end opposite to the end connected to the thin film transistor TFT. This superposition is clear from FIG.
The pixel electrode PX is used as one electrode PL2, and the counter voltage signal C
Storage capacitance (capacitance element) where L is the other electrode PL1
Construct Cstg. The dielectric film of the storage capacitor Cstg includes an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As shown in FIG. 1, the storage capacitance Cst
g is formed at a portion where the width of the conductive film g1 of the counter voltage signal line CL is increased. In this case, the storage capacity Cstg is
Since the material of the electrode positioned on the lower side of the insulating film GI is made of Al and the surface thereof is anodized, the point defect caused by so-called whiskers of Al (positioned on the upper side) (A short circuit with the electrode to be used) can be obtained.

<< Storage Capacitor Cstg >> The pixel electrode PX is formed so as to overlap the counter voltage signal line CL at the end opposite to the end connected to the thin film transistor TFT. This superposition is clear from FIG.
The pixel electrode PX is used as one electrode PL2, and the counter voltage signal C
Storage capacitance (capacitance element) where L is the other electrode PL1
Construct Cstg. The dielectric film of the storage capacitor Cstg includes an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As shown in FIG. 1, the storage capacitance Cst
g is formed at a portion where the width of the conductive film g1 of the counter voltage signal line CL is increased. In this case, the storage capacity Cstg is
Since the material of the electrode positioned on the lower side of the insulating film GI is made of Al and the surface thereof is anodized, the point defect caused by so-called whiskers of Al (positioned on the upper side) (A short circuit with the electrode to be used) can be obtained.

<< Configuration around Matrix >> FIG. 5 shows a display panel PNL including upper and lower glass substrates SUB1 and SUB2.
FIG. 4 is a diagram showing a main part plane around a matrix (AR). FIG. 6 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

[0043] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared A glass substrate of a standardized size is processed even in a variety, and the size is reduced to a size suitable for each type. In each case, the glass is cut after passing through one process.

FIGS. 5 and 6 show the latter example. Both FIGS. 5 and 6 show the upper and lower substrates SUB1 and SUB2 after cutting, and LN shows the edge of both substrates before cutting. . In any case, in the completed state, the external connection terminal groups Tg, Td
The size of the upper substrate SUB2 is limited to the inside of the lower substrate SUB1 so that the portions where the terminals CTM are present (the upper side and the left side in the figure) are exposed.

The terminal groups Tg and Td are a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, respectively, which will be described later.
1 and a tape carrier package TCP on which an integrated circuit chip CHI is mounted (see FIGS. 16 and 1).
A plurality of units are collectively named in the unit of 7). The lead wiring from the matrix part of each group to the external connection terminal part is inclined as approaching both ends. This is because the terminals DT of the display panel PNL correspond to the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP.
This is for matching M and GTM.

The counter electrode terminal CTM is connected to the counter electrode C
A terminal for applying a counter voltage to T from an external circuit.
The counter electrode signal line CL in the matrix section is drawn out on the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the respective counter voltage signal lines are grouped together by a common bus line CB and connected to the counter electrode terminal CTM. .

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal sealing opening INJ, the liquid crystal LC
Is formed to seal the sealing pattern SL. The sealing material is made of, for example, an epoxy resin.

The layers of the orientation films ORI1 and ORI2 are formed inside the seal pattern SL. Polarizing plates POL1, P
OL2 is formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
The liquid crystal LC is a lower alignment film ORI for setting the direction of liquid crystal molecules.
1 and the upper alignment film ORI2 are sealed in a region partitioned by a seal pattern SL.

The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are sealed. Assembled by cutting.

FIG. 19 is an enlarged view of the portion A (the sealing material SL coating portion) in FIG. In the sealing material SL application section, the sealing material application section SAA on the transparent glass substrate SUB1 is used.
1 and unevenness U on the sealant application portion SAA2 on SUB2
It has a rough surface on which EN is formed.

The unevenness UEN is formed by blowing high-pressure air containing an abrasive before applying the sealing material SL. Abrasive spraying is performed, for example, using SAA.
1. The masking is performed so that the abrasive does not hit parts other than SAA2.

The unevenness UEN is formed in order to increase the contact area between the sealing material SL and the transparent glass substrates SUB1 and SUB2.

In FIG. 19, the sealing material SL enters and is bonded to the unevenness UEN formed in the sealing material application portions SAA1 and SAA2.

Here, the sealing material application portion SA of the sealing material SL
Consider the adhesive strength to A1 and SAA2. The adhesive strength is determined by the strength and the number of chemical bonds generated at the interface between the adhesive and the adherend. The strength of the chemical bond is determined by the type of the adhesive and the adherend, and the number of chemical bonds is determined by the contact area between the adhesive and the adherend. Normally, a film is formed on the transparent glass substrates SUB1 and SUB2 (in this embodiment, the protective films PSV and SUB are formed on the SUB1).
2, only the overcoat film OC) is formed on the sealing material SLA and the sealing material application portions SAA1 and SAA2.
The contact area with is not wide.

On the other hand, in this embodiment, since the unevenness UEN is formed and the sealing material SL enters the unevenness UEN and adheres, the sealing material SL and the sealing material application are compared with the case where the unevenness UEN is not formed. The contact area with the portions SAA1 and SAA2 is significantly larger.

Therefore, the sealing material SL and the sealing material application portion SA
Since the number of chemical bonds generated at the interface with A1 and SAA2 increases, the sealing material application portions SAA1 and SA of the sealing material SL
The adhesive strength to A2 is improved.

The sealing material SL and the sealing material application section SAA1,
The advantages of improving the adhesive force by increasing the contact area of the SAA 2 include: (1) it is possible to reduce the peeling failure of the sealing material.

(2) It is possible to use a sealing material having a low adhesive force and a small amount of liquid crystal contamination, and display quality can be improved.

<< Gate Terminal >> FIG. 7 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, where (a) is a plane and (b) is B in (a). 4 shows a cross section taken along section line -B. This figure corresponds to the vicinity of the lower part of FIG. 7, and the diagonal wiring portion is represented by a straight line for convenience.

AO is a border line for direct drawing of photoresist, in other words, a photoresist pattern of selective anodic oxidation. Therefore, this photoresist is removed after anodic oxidation, and the pattern AO shown in the figure does not remain as a finished product, but the oxide film AO is formed on the gate wiring GL as shown in the sectional view.
Since F is selectively formed, its trace remains. In the plan view, the left side is a region which is covered with the resist and is not anodized, and the right side is a region which is exposed from the resist and is anodized with reference to the boundary line AO of the photoresist. The anodized AL layer g1 has an oxide Al ₂ O ₃ film AOF formed on its surface, and the lower conductive portion has a reduced volume. Of course, anodic oxidation is performed by setting an appropriate time, voltage and the like so that the conductive portion remains.

The gate terminal GTM protects the surface of the Al layer g1 and the surface thereof, and also uses a TCP (Tape Carrier Package).
e) transparent conductive layer g for improving the reliability of connection with
And 2. This transparent conductive film g2 is a transparent conductive film (Indium-Tin-Oxide I) formed by sputtering.
TO: Nessa film) and is formed to a thickness of 1000 to 2000 (in this embodiment, a thickness of about 1400). In addition, the conductive layers d1 and d2 formed on the Al layer g1 and on the side surfaces thereof have good connectivity to both the Al layer and the transparent conductive layer g2 in order to compensate for poor connection between the Al layer and the transparent conductive layer g2. This is for connecting the Cr layer d1 to reduce the connection resistance, and the conductive layer d2 remains because the same mask is formed as the conductive layer d1.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line, the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located on the left end is formed.
Are exposed from them so that they can make electrical contact with external circuits. In the figure, only one pair of the gate line GL and the gate terminal is shown. However, in practice, a plurality of such pairs are arranged vertically as shown in FIG. 7 to form a terminal group Tg (FIG. 5). The left end of the gate terminal is
It is extended beyond the cutting area of the substrate and short-circuited by a wiring SHg (not shown). Such a short-circuit line SHg in the manufacturing process is useful for power supply during anodization and prevention of electrostatic breakdown during rubbing of the alignment film ORI1 and the like.

<< Drain Terminal DTM >> FIGS. 8A and 8B are diagrams showing the connection from the video signal line DL to the external connection terminal DTM. FIG. 8A shows the plane, and FIG.
4 shows a cross section taken along section line B. 5 corresponds to the vicinity of the upper right of FIG. 5, and the direction of the drawing is changed for convenience, but the right end direction corresponds to the upper end of the substrate SUB1.

TSTd is an inspection terminal to which an external circuit is not connected, but is wider than a wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal D
The TM is also wider than the wiring part so that it can be connected to an external circuit. The external connection drain terminals DTM are vertically arranged, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and are further extended beyond the cutting line of the substrate SUB1. All of them are short-circuited to each other by a wiring SHd (not shown) to prevent electric breakdown.

The test terminals TSTd are formed on every other video signal line DL as shown in FIG.

The drain connection terminal DTM is connected to the transparent conductive layer g2.
It is formed of a single layer, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. Gate insulating film G
The semiconductor layer AS formed on the end of the gate insulating film G
This is for etching the edge of I into a tapered shape.
On the terminal DTM, a protective film P for connection with an external circuit is provided.
SV1 has of course been removed.

From the matrix portion to the drain terminal portion DTM
Up to the layer d of the same level as the video signal line DL.
1 and d2 are partially formed in the protective film PSV1,
The protective film PSV1 is connected to the transparent conductive film g2. This aims to protect the easily contacted Al layer d2 with the protective film PSV1 and the seal pattern SL as much as possible.

<< Counter Electrode Terminal CTM >> FIGS. 9A and 9B are diagrams showing the connection from the counter electrode signal line CL to its external connection terminal CTM. FIG. 9A shows the plane, and FIG. 4 shows a cross section taken along section line -B. This figure corresponds to the vicinity of the upper left of FIG.

Each counter voltage signal line CL is connected to a common bus line C
B collectively leads to the counter electrode terminal CTM. The common bus line CB has a conductive layer d on the conductive layer g1.
1. A structure in which conductive layers d2 are stacked. this is,
This is to reduce the resistance of the common bus line CB so that the opposing voltage is sufficiently supplied from the external circuit to each opposing voltage signal line CL. As a result, the counter electrode CT is sufficiently transmitted to the terminal pixel, and crosstalk (particularly, crosstalk in the horizontal direction of the screen) due to distortion according to the video signal supplied to the video signal line DL of each counter electrode CT is generated. Generation can be reduced. This structure is characterized in that the resistance of the common bus line can be reduced without particularly adding a new conductive layer. The conductive layer g1 of the common bus line CB is a conductive layer d.
1. No anodization is performed so as to be electrically connected to the conductive layer d2. Also, it is exposed from the gate insulating film GI.

The counter electrode terminal CTM has a structure in which a transparent conductive layer g2 is laminated on a conductive layer g1. The transparent conductive layer g2 covers the conductive layer g1 with the durable transparent conductive layer g2 to protect the surface and prevent electric contact and the like.

<< Equivalent Circuit of Entire Display Device >> FIG. 10 shows a connection diagram of the equivalent circuit of the display matrix portion and its peripheral circuits. Although the figure is a circuit diagram, it is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.

In the figure, X indicates a video signal line DL, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively. Y means the scanning signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.

The SUP uses a TFT liquid crystal display device to transfer information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a plurality of divided and stabilized voltage sources from one voltage source. This is a circuit that includes a circuit that exchanges information for use.

<< Driving Method >> FIG. 11 shows a driving waveform of the liquid crystal display device of the present invention. The opposite voltage is converted into a binary AC rectangular wave of Vch and Vcl, and the scanning signal Vg (i-1),
Vgh and Vg are applied to the non-selection voltage Vg (i) every scanning period.
It changes with two values of ll. The amplitude value of the counter voltage and the amplitude value of the non-selection voltage are the same. The video signal voltage is a voltage obtained by subtracting half of the amplitude of the counter voltage from the voltage to be applied to the liquid crystal layer.

The counter voltage may be DC, but by converting it to AC, the maximum amplitude of the video signal voltage can be reduced, and a video signal drive circuit (signal side driver) having a low withstand voltage can be used.

<< Function of Storage Capacitance Cstg >> Storage Capacitance Cstg
Is provided in order to accumulate video information (after the thin film transistor TFT is turned off) written in the pixel for a long time.
In the method of applying an electric field parallel to the substrate surface used in the present invention, unlike the method of applying the electric field perpendicular to the substrate surface, there is almost no capacitance (so-called liquid crystal capacitance) formed by the pixel electrode and the counter electrode. However, the storage capacity Cstg cannot store video information in the pixel. Therefore, in a system in which an electric field is applied in parallel with the substrate surface, the storage capacitor Cstg is an essential component.

The storage capacitor Cstg also works to reduce the effect of the gate potential change ΔVg on the pixel electrode potential Vs when the thin film transistor TFT switches. This situation is represented by the following equation.

[0080]

[Expression 1] ΔVs = {Cgs / (Cgs + Cstg + Cpix)} × △
Vg where Cgs is the gate electrode G of the thin film transistor TFT.
Parasitic capacitance formed between T and the source electrode SD1, C
pix represents a capacitance formed between the pixel electrode PX and the counter electrode CT, and ΔVs represents a so-called feedthrough voltage corresponding to a change in the pixel electrode potential due to ΔVg. This change ΔVs causes a DC component applied to the liquid crystal LC, but the storage capacitance Cst
The larger the value of g, the smaller the value. The reduction of the DC component applied to the liquid crystal LC
The life of C can be improved, and so-called burn-in in which the previous image remains when the liquid crystal display screen is switched can be reduced.

<< Manufacturing Method >> Next, a method of manufacturing the liquid crystal display device on the substrate SUB1 side will be described with reference to FIGS.
This will be described with reference to FIG. In the same figure, the letters at the center are abbreviations of the process names, and the left side shows the processing flow as viewed from the cross-sectional shape near the gate terminal shown in FIG.

Steps A to H except for Steps B and D are classified according to the respective photographic processes. Each of the cross-sectional views of each of the processes corresponds to the stage where the processing after the photographic process is completed and the photoresist is removed. Is shown. In the present description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 12 A 3000 mm thick Al-Pd or Al-Pd film is formed on a lower transparent glass substrate SUB1 made of AN635 glass (trade name).
A conductive film g1 made of Si, Al—Ta, Al—Ti—Ta, or the like is provided by sputtering. After the photographic processing, the conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acetic acid. Thereby, the gate electrode GT, the scanning signal line GL, the counter electrode CT, the counter voltage signal line CL, and the electrode P
L1, gate terminal GTM, first conductive layer of common bus line CB, first conductive layer of counter electrode terminal CTM, gate terminal G
Anodizing bus line SHg for connecting TM (not shown)
Then, an anodic oxidation pad (not shown) connected to the anodic oxidation bus line SHg is formed.

Step B, FIG. 12 After the formation of the anodic oxidation mask AO by direct writing, a solution in which 3% tartaric acid is adjusted to PH 6.25 ± 0.05 with ammonia and diluted 1: 9 with ethylene glycol liquid is used. The substrate SUB1 is immersed in an anodizing solution and adjusted so that the formation current density becomes 0.5 mA / cm ² (constant current formation). Next, anodic oxidation is performed until the formation voltage 125 V necessary for obtaining a predetermined Al ₂ O ₃ film thickness is reached. Thereafter, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g1 is anodized to form an anodic oxide film AOF having a thickness of 1800 ° on the gate electrode GT, the scanning signal line GL, the counter electrode CT, the counter voltage signal line CL, and the electrode PL1.

Step C, FIG. 12 A transparent conductive film g2 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photoprocessing, the transparent conductive film g2 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant to form the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the second conductive layer of the counter electrode terminal CTM. I do.

Step D, FIG. 13 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a Si nitride film having a thickness of 2200 °, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form a film. Is provided with a 2000 ° i-type amorphous Si film, and then a hydrogen gas and a phosphine gas are introduced into a plasma CVD apparatus to form an N (+)-type amorphous Si film having a thickness of 300 °.

Step E, FIG. 13 After photographic processing, SF ₆ and CC are used as dry etching gases.
Using l ₄ , N (+) type amorphous Si film, i type amorphous Si
By selectively etching the film, islands of the i-type semiconductor layer AS are formed.

Step F, FIG. 13 After the photographic processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Step G, FIG. 14 A conductive film d1 made of Cr having a thickness of 600 .ANG. Is provided by sputtering, and an Al-P film having a thickness of 4000 .ANG.
A conductive film d2 made of d, Al-Si, Al-Ta, Al-Ti-Ta, or the like is provided by sputtering. After the photographic processing, the conductive film d2 is etched with the same liquid as in Step B,
The conductive film d1 is etched with the same liquid as in step A, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the pixel electrode PX, the electrode PL2, the second conductive layer, the third conductive layer and the drain of the common bus line CB are formed. A bus line SHd (not shown) for short-circuiting the terminal DTM is formed. Next, CCl ₄ and SF ₆ were introduced into the dry etching apparatus,
By etching the (+) type amorphous Si film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step H, FIG. 14 An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to form a 1 μm-thick Si nitride film. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo etching technique using SF ₆ as a dry etching gas.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 15 is a top view showing a state where the video signal driving circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.

CHI is a driving IC chip for driving the display panel PNL (the lower five are driving ICs on the vertical scanning circuit side)
The left and right chips are the driving I on the video signal driving circuit side.
C chip). TCP is a tape carrier package in which a driving IC chip CHI is mounted by a tape automated bonding method (TAB), as will be described later with reference to FIGS. 16 and 17, and PCB1 is a driving circuit in which the above-described TCP, capacitors and the like are mounted. The substrate is divided into two, one for a video signal drive circuit and one for a scan signal drive circuit. FG
P is a frame ground pad, and a shield case S
A spring-shaped fragment provided by cutting into the HD is soldered. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1. As shown in the drawing, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material plated with Sn) are sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer.

<< Connection Structure of TCP >> FIG. 16 is a diagram showing a cross-sectional structure of a tape carrier package TCP which forms the scanning signal drive circuit V and the video signal drive circuit H and has the integrated circuit chip CHI mounted on a flexible wiring board. Yes,
FIG. 17 is a cross-sectional view of a main part of the liquid crystal display panel, showing a state where it is connected to a scanning signal circuit terminal GTM in this example.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu. ) Is the integrated circuit C
The HI bonding pads PAD are connected by a so-called face-down bonding method. Terminal TTB, T
The outer ends (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
CRT / TFT conversion circuit / power supply circuit S by soldering
A liquid crystal display panel P is formed on the UP by using an anisotropic conductive film ACF.
NL. The package TCP has a protective film PS whose leading end exposes the connection terminal GTM on the panel PNL side.
Since the external connection terminal GTM (DTM) is covered with at least one of the protective film PSV1 and the package TCP, the external connection terminal GTM (DTM) is covered with the panel so as to cover V1.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that solder does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by an epoxy resin EPX or the like, and the space between the package TCP and the upper substrate SUB2 is further filled with a silicone resin SIL to multiplex protection.

<< Drive Circuit Board PCB2 >> Drive Circuit Board P
The CB2 has electronic components such as an IC, a capacitor, and a resistor mounted thereon. The drive circuit board PCB2 includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CR (Crystal Control Unit) from a host (upper processing unit).
A circuit SUP including a circuit for converting information for T (cathode ray tube) into information for a TFT liquid crystal display device is mounted. C
J is a connector connection portion to which a connector (not shown) connected to the outside is connected. The drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a flat cable FC.

<< Overall Configuration of Liquid Crystal Display Module >> FIG.
FIG. 3 is an exploded perspective view showing each component of the liquid crystal display module MDL. SHD is a frame-shaped shield case (metal frame) made of metal plate, LCW display window, PNL
Is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide, RM is a reflection plate, BL is a backlight fluorescent tube, LCA
Reference numeral denotes a backlight case, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble a module MDL.

The module MDL is a shield case SH
The entirety is fixed by claws and hooks provided on D. The backlight case LCA includes a backlight fluorescent tube BL, a light diffusion plate SPB light diffusion plate, and a light guide LC.
B, a shape for storing the reflection plate RM, and the light guide L
The light of the backlight fluorescent tube BL arranged on the side surface of the CB is made uniform on the display surface by the light guide LCB, the reflection plate RM, and the light diffusion plate SPB, and the liquid crystal display panel PN is formed.
Light is emitted to the L side. An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL, and serves as a power supply for the backlight fluorescent tube BL.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various changes can be made without departing from the gist of the present invention. It is. Although the present invention has been described with respect to an example in which the present invention is applied to a horizontal electric field type active matrix type liquid crystal display device, the present invention is also applicable to a vertical electric field type or COG (chip-on-glass) type liquid crystal display device. It goes without saying that the present invention can be applied to an apparatus.

[0100]

As described above, according to the liquid crystal display device of the present invention, since the adhesive force of the sealing material can be improved, peeling of the sealing material can be prevented, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix type color liquid crystal display device of the present invention.

FIG. 2 is a sectional view of a pixel taken along section line 3-3 in FIG. 1;

FIG. 3 is a sectional view of the thin film transistor element TFT taken along section line 4-4 in FIG. 1;

FIG. 4 is a cross-sectional view of the storage capacitor Cstg taken along section line 5-5 in FIG. 1;

FIG. 5 is a plan view for describing a configuration of a matrix peripheral portion of a display panel.

FIG. 6 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 7 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 8 is a plan and cross-sectional view showing the vicinity of a connection between a drain terminal DTM and a video signal line DL.

FIG. 9 is a plan view and a sectional view showing the vicinity of a connection portion of a common electrode terminal CTM, a common bus line CB, and a common voltage signal line CL.

FIG. 10 is a circuit diagram including a matrix portion and its periphery of the active matrix type color liquid crystal display device of the present invention.

FIG. 11 is a diagram showing driving waveforms of the active matrix type color liquid crystal display device of the present invention.

FIG. 12 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 13 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes D to F on the substrate SUB1 side.

FIG. 14 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes G to H on the substrate SUB1 side.

FIG. 15 is a top view showing a state where peripheral driving circuits are mounted on the liquid crystal display panel.

FIG. 16 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.

FIG. 17 is a cross-sectional view of a main part showing a state where the tape carrier package TCP is connected to a scanning signal circuit terminal GTM of the liquid crystal display panel PNL.

FIG. 18 is an exploded perspective view of the liquid crystal display module.

19 is an enlarged view of a portion A in FIG.

[Explanation of symbols]

SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line, CL: counter voltage signal line, PX: pixel electrode, C
T: counter electrode, GI: insulating film, GT: gate electrode, AS
... i-type semiconductor layer, SD: source or drain electrode, PSV: protective film, BM: light shielding film, LC: liquid crystal, TF
T: thin film transistor, g, d: conductive film, Cstg: storage capacitor, AOF: anodized film, AO: anodized mask, G
TM: gate terminal, DTM: drain terminal, CB: common bus line, DTM: common electrode terminal, SHD: shield case, PNL: liquid crystal display panel, SPB: light diffusion plate,
LCB: Light guide, BL: Backlight fluorescent tube, LCA:
Backlight case, RM: reflector, UEN: unevenness, S
AA: Sealing material application section (subscripts are omitted above).

Claims (3)

[Claims] 1. A liquid crystal display device comprising: a pair of transparent substrates opposed to each other with a liquid crystal interposed therebetween; and a sealing member for sealing the liquid crystal together with the fixing of the other transparent substrate to the one transparent substrate side. A liquid crystal display device, characterized in that the surface on the side of the transparent substrate is roughened at least in a part of the bonding portion of the sealing material. 2. A transparent substrate to which a sealing material is adhered,
2. The liquid crystal display device according to claim 1, wherein the entire surface of the sealing material has a rough surface. 3. The liquid crystal display device according to claim 1, wherein the rough surface is formed as an uneven surface.