JPH10186410A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To drive a liquid crystal display device with a low voltage and a low power consumption by allowing electrode width of shorter side of pixel electrodes to exceed the thickness of a liquid crystal composition layer and to be smaller than the interval between the pixel electrode and a video signal line. SOLUTION: Each pixel is arranged ion the intersection area (in the area surrounded by four lines of signal lines) of a scanning signal line (a gate signal line or a horizontal signal line) GL, an counter voltage signal line (a counter electrode wiring) CL and adjacent two lines of video signal lines (a drain signal line or a cervical signal line) DL. Each pixel includes a thin film transistor TFT, a storage capacitance Cstg, pixel electrodes PX and counter electrodes CT. Electrode widths of the pixel electrodes PX and counter electrodes CT are respectively set to be sufficiently larger than values exceeding the maximum set thickness of a liquid crystal layer. Moreover, maximum values of electrode widths of respective electrodes PX, CT are made smaller than the interval between the pixel electrode PX and the counter electrode CT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an active device using a thin film transistor or the like.
The present invention relates to a matrix type liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device using an active element typified by a thin film transistor (TFT) is widely used as a display terminal of OA equipment and the like because of its thinness and light weight and high image quality comparable to a cathode ray tube. It is beginning to spread.

The display methods of this liquid crystal display device are roughly classified into the following two types. One is a method in which the liquid crystal is sandwiched between two substrates each having a transparent electrode and operated by a voltage applied to the transparent electrode, and light transmitted through the transparent electrode and incident on the liquid crystal is modulated for display. Currently, all of the products that are widely used adopt this method. The other is
In this method, the liquid crystal is operated by an electric field substantially parallel to the substrate surface between two electrodes formed on the same substrate, and light incident on the liquid crystal from a gap between the two electrodes is modulated and displayed. Although there is no such product, it has a feature that the viewing angle is extremely wide, and is a promising technology for an active matrix type liquid crystal display device.

[0004] Regarding the characteristics of the latter method, for example,
Patent Application Publication No. 5-505247 or JP-B-63-
21907 and JP-A-6-160878.

[0005]

However, the latter liquid crystal display device having such a structure has a structure in which an electric field substantially parallel to the substrate surface is generated through a thin film electrode of about several thousand degrees. Therefore, it is more difficult to effectively generate an electric field in the liquid crystal layer than in the former case.

For this reason, it is necessary to generate a higher electric field between the electrodes than in the former case.
The necessity of using a high-withstand-voltage LSI for the drive circuit cannot be avoided.

As another problem, in the former method, in order to improve the contrast ratio, a metal material having a good light-transmitting property is used for a black matrix (light-shielding film) covering a portion through which unnecessary light is transmitted. However, when this is applied to the latter as it is, there is a problem that the electric field between the electrodes is absorbed by the black matrix, and an effective electric field cannot be generated between the electrodes.

As another problem, in the former method, an electric field from a video signal line is absorbed by a counter electrode formed on substantially the entire surface of a substrate facing the substrate forming the video signal line, and the The electric field from the lines did not affect the electric field between the electrodes. However, in the latter method, since no electrode is present on the substrate facing the substrate forming the video signal line, the electric field from the video signal line affects the electric field between the electrodes. The crosstalk (particularly in the vertical direction of the screen) that also affects the display of the video information of the row (2) occurs, and a streak-like video called a so-called vertical smear appears.

Further, as another problem, in the latter method, the counter electrode must be formed in a linear shape. Therefore, the resistance from the input end to the end of the counter electrode is reduced by the fact that the counter electrode in the former method is formed in a planar shape. Significantly higher than in the case of As a result, the opposing voltage is not sufficiently transmitted to the terminal pixel,
Crosstalk (especially in the horizontal direction of the screen) occurs due to the counter voltage being distorted according to the video signal at the capacity of the portion where the counter voltage signal line intersects the video signal line. There was a problem that appeared.

The present invention has been made based on such circumstances, and an object of the present invention is to provide a liquid crystal display device which can be driven with low voltage and low power consumption and has good image quality without the above-mentioned adverse effects. It is in.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a liquid crystal composition layer in which liquid crystal molecules can be twisted and rotated, a first substrate and a second substrate sandwiching the liquid crystal composition layer, and a video signal line formed on the first substrate surface. And, at least one pixel electrode to which a video signal is applied via the video signal line, and at least one counter electrode to which a counter voltage is applied are arranged to face each other,
In a liquid crystal display device that controls the amount of twist of liquid crystal molecules by an electric field component generated between the pixel electrode and the counter electrode, the width of the pixel electrode in the lateral direction exceeds the thickness of the liquid crystal composition layer, The distance between the pixel electrode and the video signal line is smaller than the distance between the pixel electrode and the video signal line.

[0013]

Other objects and features of the present invention will become apparent from the following description with reference to the drawings.

<< Active matrix liquid crystal display device >>
An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

<< Planar Configuration of Matrix Part (Pixel Part) >> FIG. 1 is a plan view showing one pixel of an active matrix type color liquid crystal display device of the present invention and its periphery.

As shown in FIG. 1, each pixel has a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring) CL, and two adjacent video signal lines (drain). The signal line or the vertical signal line) is arranged in an intersecting region with the DL (in a region surrounded by four signal lines). Each pixel is a thin film transistor TFT, a storage capacitor Cst
g, the pixel electrode PX and the counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in FIG. Video signal line DL
Extend in the up-down direction and are arranged in a plurality in the left-right direction. The pixel electrode PX is connected to the thin film transistor TFT, and the counter electrode CT is integrated with the counter voltage signal line CL.

2 vertically adjacent to each other along the video signal line DL.
The pixel has a configuration in which the planar configuration overlaps when bent along the line in FIG. 1A. This is because the opposing voltage signal line CL is shared by two vertically adjacent pixels along the video signal line DL, and the electrode width of the opposing voltage signal line CL is increased, thereby reducing the resistance of the opposing voltage signal line CL. That's why.
This makes it easy to sufficiently supply a counter voltage from the external circuit to the counter electrode CT of each pixel in the left-right direction.

The pixel electrode PX and the counter electrode CT face each other, and the electric state between each pixel electrode PX and the counter electrode CT controls the optical state of the liquid crystal LC to control the display. The pixel electrode PX and the counter electrode CT are formed in a comb shape, and each is an electrode that is elongated in the vertical direction in the figure.

The number O (number of comb teeth) of the counter electrode CT in one pixel is equal to the number P (number of comb teeth) of the pixel electrode PX and O =
It is configured to always have the relationship of P + 1 (O = 3, P = 2 in this embodiment). This is because the counter electrode CT and the pixel electrode PX are alternately arranged, and the counter electrode CT is always adjacent to the video signal line DL. As a result, the electric field between the counter electrode CT and the pixel electrode PX is changed to the video signal line DL.
The lines of electric force from the video signal line DL can be shielded by the counter electrode CT so as not to be affected by the electric field generated from. The counter electrode CT is connected to a counter voltage signal line C described later.
Since the potential is always supplied from the outside by L, the potential is stable. Therefore, there is almost no change in potential even adjacent to the video signal line DL. In addition, since the geometrical position of the pixel electrode PX from the video signal line DL is farther away, the parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the image of the pixel electrode potential Vs Fluctuation due to the signal voltage can also be suppressed. Thus, crosstalk (defective image quality called vertical smear) occurring in the vertical direction can be suppressed.

The electrode width Wp of the pixel electrode PX and the counter electrode CT,
Each Wc is set to 6 μm, which is set to be sufficiently larger than 4.5 μm which exceeds the maximum set thickness of the liquid crystal layer described later. It is preferable to have a margin of 20% or more in consideration of processing variations in manufacturing. Therefore, it is preferable that the width be sufficiently larger than 5.4 μm. Thus, the electric field component applied to the liquid crystal layer parallel to the substrate surface becomes larger than the electric field component in the direction perpendicular to the substrate surface, so that an increase in the voltage for driving the liquid crystal can be suppressed. It is preferable that the maximum value of the electrode widths Wp and Wc of each electrode is smaller than the distance L between the pixel electrode PX and the counter electrode CT. This is because if the distance between the electrodes is too large, the curvature of the lines of electric force becomes too strong, and the area where the electric field component perpendicular to the substrate surface is larger than the electric field component parallel to the substrate surface increases. This is because a parallel electric field component cannot be efficiently applied to the liquid crystal layer. Therefore, the interval L between the pixel electrode PX and the counter electrode CT has a margin of 20%.
It is necessary that it be larger than 7.2 μm. In the present embodiment, the resolution is 10.4 inches diagonally 640 × 480 dots. Therefore, the pixel pitch is 110 μm, and by dividing the pixels into four, the interval L> 7.2 μm is realized. (By dividing the pixel into eight or less, the interval L> 7.
2 μm can be satisfied. On the other hand, when the distance is 10 or more, the interval L is 7 μm or less, which does not satisfy the condition. In addition, the electrode width of the video signal line DL is set to the pixel electrode P in order to prevent disconnection.
X is set to 8 μm, which is slightly wider than that of the counter electrode CT, and the interval between the video signal line DL and the counter electrode CT is set to 1 μm to prevent a short circuit. Here, the electrode width of the video signal line DL is set to be equal to or less than twice the electrode width of the adjacent counter electrode CT. Alternatively, when the electrode width of the video signal line DL is determined from the productivity of the yield, the electrode width of the counter electrode CT adjacent to the video signal line DL is changed to the video signal line D.
Make the width of the electrode L equal to or more than 電極. This is the video signal line D
The lines of electric force generated from L
In order to absorb a line of electric force generated from a certain electrode width, an electrode having an electrode width equal to or larger than that is necessary. Accordingly, the counter electrodes CT on both sides only need to absorb electric lines of force generated from half (4 μm each) of the electrodes of the video signal line DL.
The electrode width of the counter electrode CT adjacent to L is 以上 or more. As a result, crosstalk due to the influence of the video signal,
(Particularly crosstalk in the vertical direction (vertical direction)) is prevented.

The width of the scanning signal line GL is set so as to satisfy a resistance value sufficient to apply a scanning voltage to the gate electrode GT of the pixel on the terminal side (opposite to a scanning electrode terminal GTM described later). Further, the counter voltage signal line CL is also connected to the counter electrode C of the terminal pixel (the opposite side of the common bus line CB described later).
The electrode width is set so as to satisfy a resistance value enough to apply a common voltage to T.

On the other hand, the electrode interval between the pixel electrode PX and the counter electrode CT changes depending on the liquid crystal material used. this is,
Since the electric field strength that achieves the maximum transmittance varies depending on the liquid crystal material, the electrode spacing is set according to the liquid crystal material, and within the range of the maximum amplitude of the signal voltage set by the withstand voltage of the video signal driving circuit (signal side driver) used. , So that the maximum transmittance can be obtained. When a liquid crystal material described later is used, the electrode interval is 16 μm.

<< Cross-Sectional Structure of Matrix Part (Pixel Part) >> FIG. 2 is a cross-sectional view taken along the line 3-3 in FIG. 1, and FIG. 4 is the storage capacitance C at the section line 5-5 in FIG.
It is a figure showing the section of stg. As shown in FIGS.
On the lower transparent glass substrate SUB1 side, a thin film transistor TFT, a storage capacitor Cstg and an electrode group are formed on the side of the liquid crystal layer LC, and on the upper transparent glass substrate SUB2 side, a color filter FIL and a light shielding black matrix pattern BM are formed. I have.

Further, the transparent glass substrates SUB1, SUB2
Are provided with alignment films ORI1 and ORI2 for controlling the initial alignment of the liquid crystal on the inner surface of each (liquid crystal LC side), and the polarizing axes are provided on the outer surfaces of the transparent glass substrates SUB1 and SUB2. A polarizing plate arranged orthogonally (crossed Nicols arrangement) is provided.

<< TFT Substrate >> First, the configuration of the lower transparent glass substrate SUB1 side (TFT substrate) will be described in detail.

<< Thin Film Transistor >> The thin film transistor TFT operates so that the channel resistance between the source and the drain decreases when a positive bias is applied to the gate electrode GT, and the channel resistance increases when the bias is set to zero.

As shown in FIG. 3, the thin film transistor TFT has a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic, intrinsic, not doped with conductivity type determining impurities) amorphous silicon (Si). Type semiconductor layer A
S, a pair of source electrode SD1 and drain electrode SD2. It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are interchanged during the operation. However, in the following description, one is fixed and the other is fixed as a drain for convenience.

<< Gate Electrode GT >> The gate electrode GT is formed continuously with the scanning signal line GL.
Is configured to be a gate electrode GT. The gate electrode GT is a portion exceeding the active region of the thin film transistor TFT, and is formed larger than that so as to completely cover the i-type semiconductor layer AS (as viewed from below). Thereby, in addition to the role of the gate electrode GT, a device is devised so that external light and backlight do not hit the i-type semiconductor layer AS. In this example, the gate electrode GT is formed of a single-layer conductive film g1. As the conductive film g1, for example, an aluminum (Al) film formed by sputtering is used, and an anodic oxide film AOF of Al is provided thereon.

<< Scanning Signal Line GL >> The scanning signal line GL is formed of the conductive film g1. The conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, and is integrally formed. This scanning signal line G
L, the gate voltage Vg is applied from an external circuit to the gate electrode G.
Supply to T. An anodic oxide film AOF of Al is also provided on the scanning signal line GL. Note that the video signal line DL
The portion that intersects with the video signal line DL is made thin in order to reduce the probability of short-circuiting with the video signal line DL, and is made bifurcated so that even if it is short-circuited, it can be separated by laser trimming.

<< Counter Electrode CT >> The counter electrode CT is formed of the same conductive film g1 as the gate electrode GT and the scanning signal line GL. An Al anodic oxide film AOF is also provided on the counter electrode CT. Since the counter electrode CT is completely covered with the anodic oxide film AOF, even if the counter electrode CT is brought as close as possible to the video signal line, they are not short-circuited. Further, they may be configured to cross each other. The counter electrode CT is configured to apply a counter voltage Vcom. In this embodiment, the counter voltage Vcom is the minimum level drive voltage Vd applied to the video signal line DL.
From the intermediate DC potential between min and the maximum drive voltage Vdmax, the potential is set to a potential lower by a feedthrough voltage ΔVs generated when the thin film transistor element TFT is turned off, but is used in a video signal drive circuit. When it is desired to reduce the power supply voltage of the integrated circuit to about half, an AC voltage may be applied.

<< Counter Voltage Signal Line CL >> Counter Voltage Signal Line C
L is composed of the conductive film g1. The conductive film g1 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, the scanning signal line GL, and the counter electrode CT, and is formed integrally with the counter electrode CT. The opposing voltage signal line CL allows the opposing voltage Vcom
Is supplied to the counter electrode CT. Also, the counter voltage signal line CL
An anodic oxide film AOF of Al is also provided thereon. The portion that intersects with the video signal line DL is the scanning signal line GL.
In the same manner as described above, the width is made thinner in order to reduce the probability of short-circuiting with the video signal line DL, and it is made bifurcated so that even if it is short-circuited, it can be separated by laser trimming.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI includes the gate electrode GT and the scanning signal line GL.
Is formed in the upper layer. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected.
In a thickness of 200 to 2700 ° (in this embodiment, 2400
Å) formed. The gate insulating film GI is formed so as to surround the entire matrix part AR, and the peripheral part is removed so as to expose the external connection terminals DTM and GTM. The insulating film GI also contributes to electrical insulation between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
Is amorphous silicon and is formed to a thickness of 200 to 2200 ° (in this embodiment, a film thickness of about 2000 °). The layer d0 is an N (+)-type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact. The i-type semiconductor layer AS is present on the lower side, and the conductive layer d1 (d
2) is left only where it exists.

The i-type semiconductor layer AS is also provided between the scanning signal line GL and the intersection (crossover portion) between the counter voltage signal line CL and the video signal line DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL at the intersection.

<< Source electrode SD1, drain electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is composed of a conductive film d1 in contact with the N (+) type semiconductor layer d0 and a conductive film d2 formed thereon.

The conductive film d1 is formed of a chromium (Cr) film formed by sputtering and has a thickness of 500 to 1000 ° (about 600 ° in this embodiment). When the Cr film is formed with a large thickness, the stress becomes large.
The film is formed in a range not exceeding about 膜厚. Cr film is N
The adhesion to the (+) type semiconductor layer d0 is improved, and the conductive film d2 is formed.
Is used for the purpose of preventing Al from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). Conductive film d
In addition to the Cr film, refractory metals (Mo, Ti, T
a, W) film, refractory metal silicide (MoSi ₂ , Ti)
Si ₂ , TaSi ₂ , WSi ₂ ) film may be used.

The conductive film d2 is formed by sputtering Al
To a thickness of 00 to 5000 mm (in this embodiment, 4000 mm).
Degree) is formed. The Al film has a smaller stress than the Cr film and can be formed to have a large thickness, and can reduce the resistance values of the source electrode SD1, the drain electrode SD2 and the video signal line DL, and can reduce the gate electrode GT and the i-type semiconductor. Layer AS
Has the function of ensuring that the vehicle gets over a step (improves step coverage).

After patterning the conductive films d1 and d2 with the same mask pattern, the N (+) type semiconductor layer d0 is removed using the same mask or using the conductive films d1 and d2 as a mask. That is, the i-type semiconductor layer AS
In the N (+) type semiconductor layer d0 remaining above, portions other than the conductive films d1 and d2 are removed by self-alignment. At this time, since the N (+)-type semiconductor layer d0 is etched so as to entirely remove the thickness thereof, the surface of the i-type semiconductor layer AS is also slightly etched, but the degree is controlled by the etching time. do it.

<< Video Signal Line DL >> The video signal line DL is composed of the second conductive film d2 and the third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2. The video signal line DL is formed integrally with the drain electrode SD2.

<< Pixel Electrode PX >> The pixel electrode PX is a second conductive film d of the same layer as the source electrode SD1 and the drain electrode SD2.
2, the third conductive film d3. Further, the pixel electrode PX is formed integrally with the source electrode SD1.

<< Storage Capacitor Cstg >> The pixel electrode PX is formed so as to overlap the counter voltage signal line CL at the end opposite to the end connected to the thin film transistor TFT. This superposition is clear from FIG.
The pixel electrode PX is used as one electrode PL2, and the counter voltage signal C
Storage capacitance (capacitance element) where L is the other electrode PL1
Construct Cstg. The dielectric film of the storage capacitor Cstg includes an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As shown in FIG. 1, the storage capacitance Cst
g is formed at a portion where the width of the conductive film g1 of the counter voltage signal line CL is increased.

In this case, the storage capacitor Cstg is formed by the material of the electrode positioned on the lower side with respect to the insulating film GI.
1 and the surface thereof is anodized, so that the storage capacitance which makes it difficult to cause adverse effects due to point defects (short-circuit with the electrode positioned on the upper side) caused by so-called whiskers of Al or the like. Obtainable.

<< Protective Film PSV1 >> Thin Film Transistor TF
On T, a protective film PSV1 is provided. Protective film PS
V1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a material having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of about 1 μm.

The protective film PSV1 is formed so as to surround the entire matrix part AR, and the peripheral part is connected to the external connection terminal DT.
M and GTM have been removed to expose. Protective film PS
Regarding the relationship between V1 and the thickness of the gate insulating film GI, the former is made thicker in consideration of the protection effect, and the latter is made smaller in the transconductance gm of the transistor. Therefore, the protective film PSV1 having a high protective effect is formed larger than the gate insulating film GI so as to protect the peripheral portion as much as possible.

<< Color Filter Substrate >> Next, FIGS. 1 and 2
Returning to, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.

<< Light shielding film BM >> Upper transparent glass substrate SUB
On the second side, an unnecessary gap (pixel electrode PX and counter electrode CT)
Transmitted light from the gap other than the gap between
A light-shielding film BM (a so-called black matrix) is formed so as not to lower the contrast ratio and the like. Light shielding film B
M indicates that the external light or the backlight light is the i-type semiconductor layer AS
It also plays a role in preventing light from entering. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched between the upper and lower light-shielding films BM and the large gate electrode GT, so that external natural light or backlight does not shine.

The closed polygonal outline of the light-shielding film BM shown in FIG. 1 indicates an opening inside which the light-shielding film BM is not formed. This contour pattern is an example, and when the opening portion is further enlarged, it is also possible to use a pattern as shown in FIG. In the region A in FIG. 19, the direction of the electric field is disturbed.
The display of that portion corresponds to the video information in the pixel on a one-to-one basis, and is black as black and white as white, so that it can be used as a part of the display. . Also, the vertical boundary in the figure is determined by the alignment accuracy of the upper and lower substrates, and if the alignment accuracy is better than the electrode width of the counter electrode CT adjacent to the video signal line DL, it is set between the widths of the counter electrodes. If this is the case, the opening can be further enlarged.

The light-shielding film BM has a light-shielding property and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT. By doing so, an electric field parallel to the substrate surface is effectively applied to the liquid crystal layer, and a rise in the voltage for driving the liquid crystal can be suppressed. As a material of the light-shielding film BM, for example, a material obtained by mixing a black pigment into a resist material is used, and is formed with a thickness of about 1.2 μm. Further, as another embodiment, a material in which palladium and electroless plated Ni are mixed in a resist material can be used.

In this case, the pixel electrode P
Since the distance between X and the counter electrode CT can be increased to some extent, there is also an effect that the aperture ratio can be improved.

The light-shielding film BM is formed in a grid around each pixel, and the grid partitions an effective display area of one pixel. Therefore, the outline of each pixel becomes clear by the light shielding film BM. That is, the light shielding film BM has two functions of a black matrix and light shielding for the i-type semiconductor layer AS.

The light-shielding film BM is also formed in the peripheral part in a frame shape, and its pattern is a pattern shown in FIG.
Are formed continuously with the pattern of the matrix section shown in FIG. The light-shielding film BM in the peripheral portion is extended outside the seal portion SL to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion. On the other hand, the light-shielding film BM is about 0.3 to 1.0 more than the edge of the substrate SUB2.
mm, and is formed so as to avoid the cutting area of the substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed in a stripe shape by repeating red, green and blue at a position facing the pixel. The color filter FIL is formed so as to overlap the edge portion of the light shielding film BM.

The color filter FIL can be formed as follows. First, a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process.

<< Overcoat Film OC >> The overcoat film OC prevents the dye of the color filter FIL from leaking to the liquid crystal LC, and prevents the color filter FIL and the light-shielding film BM.
It is provided for flattening the step due to the above. The overcoat film OC is formed of a transparent resin material such as an acrylic resin and an epoxy resin.

<< Liquid Crystal Layer and Polarizing Plate >> Next, the liquid crystal layer, the alignment film, the polarizing plate and the like will be described.

<< Liquid Crystal Layer >> As the liquid crystal material LC, the dielectric anisotropy Δ △ is positive, the value is 13.2, and the refractive index anisotropy Δn
Is 0.081 (589 nm, 20 ° C.), a nematic liquid crystal having a negative dielectric anisotropy Δε of -7.3 and a refractive index anisotropy Δn of 0.053 (589 nm, 20 ° C.). Was used. The thickness (gap) of the liquid crystal layer was more than 2.8 μm and less than 4.5 μm when the dielectric anisotropy Δ △ was positive. This is because the retardation Δn · d exceeds 0.25 μm.
When the thickness is less than 32 μm, transmittance characteristics having almost no wavelength dependence within the visible light range can be obtained, and most of the liquid crystals having a positive dielectric anisotropy Δ △ have a birefringence anisotropy Δn of 0.1. Over 07.
This is because it is less than 09. On the other hand, when the dielectric anisotropy Δ △ was negative, the thickness (gap) of the liquid crystal layer was set to more than 4.2 μm and less than 8.0 μm. This is because, like the liquid crystal having a positive dielectric anisotropy Δ △, the retardation Δn · d exceeds 0.25 μm.
Most of the liquid crystal having a negative dielectric anisotropy Δ △ has a birefringence anisotropy Δn of more than 0.04 to suppress the dielectric constant anisotropy Δ △ to be less than 32 μm.
It is because it is less than 06.

In addition, the liquid crystal molecules are moved from the rubbing direction to the electric field direction by a combination of an alignment film and a polarizing plate described later.
Maximum rotation can be obtained when rotated by °.

The thickness (gap) of the liquid crystal layer is controlled by polymer beads.

The liquid crystal material LC is not particularly limited as long as it is a nematic liquid crystal. The larger the value of the dielectric anisotropy Δ △, the lower the driving voltage. Also, the smaller the refractive index anisotropy Δn, the thicker the liquid crystal layer (gap), the shorter the time for filling the liquid crystal, and the smaller the gap variation.

<< Orientation Film >> Polyimide is used as the orientation film ORI. The rubbing direction RDR is parallel to the upper and lower substrates, and the angle between the rubbing direction RDR and the applied electric field direction EDR is 75.
°. FIG. 20 shows the relationship.

The angle between the rubbing direction RDR and the applied electric field direction EDR is 45 ° C. or more and less than 90 ° C. if the dielectric anisotropy Δ △ of the liquid crystal material is positive.
If the value is negative, it may be more than 0 ° and 45 ° or less.

<Polarizing Plate> As the polarizing plate POL, G1220DU manufactured by Nitto Denko Corporation was used, and the polarization transmission axis MAX1 of the lower polarizing plate POL1 was made to coincide with the rubbing direction RDR.
The polarization transmission axis MAX2 of the upper deflection plate POL2 is made orthogonal to it. FIG. 20 shows the relationship. Accordingly, it is possible to obtain a normally closed characteristic in which the transmittance increases as the voltage (the voltage between the pixel electrode PX and the counter electrode CT) applied to the pixel of the present invention increases.

<< Structure around the Matrix >> FIG. 5 is a diagram showing a main part plane around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2. FIG. 6 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

[0065] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared A glass substrate of a standardized size is processed even in a variety, and the size is reduced to a size suitable for each type. In each case, the glass is cut after passing through one process. FIGS. 5 and 6 show the latter example. Both FIGS. 5 and 6 show the upper and lower substrates SUB1 and SUB.
2 shows the state after cutting, and LN indicates the edge of both substrates before cutting. In any case, in the completed state, the external connection terminal group T
The size of the upper substrate SUB2 is limited to the inside of the lower substrate SUB1 so that g, Td, and the terminal CTM are present (the upper side and the left side in the figure) so as to expose them. The terminal groups Tg and Td are respectively provided with a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM and their lead-out wiring portions of a tape carrier package TCP (FIGS. 16 and 17) on which an integrated circuit chip CHI is mounted. The unit is named plurally. The lead wiring from the matrix section of each group to the external connection terminal section is inclined as approaching both ends. This is the package TC
This is for adjusting the terminals DTM and GTM of the display panel PNL to the arrangement pitch of P and the connection terminal pitch in each package TCP. The counter electrode terminal CTM is a terminal for applying a counter voltage to the counter electrode CT from an external circuit. The counter electrode signal line CL of the matrix section is drawn out on the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the respective counter voltage signal lines are grouped together by a common bus line CB and connected to the counter electrode terminal CTM. .

Between the transparent glass substrates SUB1 and SUB2, along the edges thereof, except for the liquid crystal filling opening INJ, the liquid crystal LC
Is formed to seal the sealing pattern SL. The sealing material is made of, for example, an epoxy resin.

The layers of the orientation films ORI1 and ORI2 are formed inside the seal pattern SL. Polarizing plates POL1, P
OL2 is formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
The liquid crystal LC is a lower alignment film ORI for setting the direction of liquid crystal molecules.
1 and the upper alignment film ORI2 are sealed in a region partitioned by a seal pattern SL. Lower alignment film ORI1
Is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are sealed. Assembled by cutting.

<< Gate Terminal Portion >> FIGS. 7A and 7B are diagrams showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, where FIG. 7A is a plane view and FIG. 7B is a view B of FIG. 4 shows a cross section taken along section line -B. This figure corresponds to the vicinity of the lower part of FIG. 7, and the diagonal wiring portion is represented by a straight line for convenience.

AO is a boundary line for direct drawing of photoresist, in other words, a photoresist pattern of selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but the locus remains because the oxide film AOF is selectively formed on the gate wiring GL as shown in the cross-sectional view. In the plan view, the left side is a region which is covered with the resist and is not anodized, and the right side is a region which is exposed from the resist and is anodized with reference to the boundary line AO of the photoresist. Anodized A
L layer g1 conductive portion of the lower formed its oxide the Al ₂ O ₃ film AOF on the surface volume decreases. Of course, anodic oxidation is performed by setting an appropriate time, voltage and the like so that the conductive portion remains.

In the figure, the AL layer g1 is hatched for easy understanding, but the region not anodized is patterned in a comb shape. This is because, when the width of the Al layer is large, whiskers are generated on the surface. Therefore, the width of each one is narrowed, and a plurality of these are bundled in parallel to prevent the generation of whiskers and disconnect the wires. The aim is to minimize the probability and conductivity sacrifice.

The gate terminal GTM protects the surface of the Al layer g1 and the surface thereof, and furthermore, the TCP (Tape Carriage).
er Package) and a transparent conductive layer g2 for improving the reliability of connection. This transparent conductive film g2 is a transparent conductive film (I
ndium-Tin-Oxide ITO (Nesa film), and is formed to a thickness of 1000 to 2000 (in this embodiment, about 1400). Al layer g
1 and conductive layers d1 and d2 formed on side surfaces thereof
In order to compensate for poor connection between the Al layer and the transparent conductive layer g2, Cr having good connectivity to both the Al layer and the transparent conductive layer g2 is used.
This is for connecting the layer d1 to reduce the connection resistance, and the conductive layer d2 remains because the same mask as the conductive layer d1 is formed.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line, and the protective film PSV1 is formed on the right side of the boundary line.
Are exposed from them so that they can make electrical contact with external circuits. In the figure, only one pair of the gate line GL and the gate terminal is shown. However, in practice, a plurality of such pairs are arranged vertically as shown in FIG. 7 to form a terminal group Tg (FIG. 5). The left end of the gate terminal is
It is extended beyond the cutting area of the substrate and short-circuited by a wiring SHg (not shown). Such a short-circuit line SHg in the manufacturing process is useful for power supply during anodization and prevention of electrostatic breakdown during rubbing of the alignment film ORI1 and the like.

<< Drain Terminal DTM >> FIGS. 8A and 8B are diagrams showing the connection from the video signal line DL to the external connection terminal DTM. FIG. 8A shows the plane, and FIG.
4 shows a cross section taken along section line B. 5 corresponds to the vicinity of the upper right of FIG. 5, and the direction of the drawing is changed for convenience, but the right end direction corresponds to the upper end of the substrate SUB1.

TSTd is an inspection terminal to which an external circuit is not connected, but is wider than a wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal D
The TM is also wider than the wiring part so that it can be connected to an external circuit. The external connection drain terminals DTM are vertically arranged, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and are further extended beyond the cutting line of the substrate SUB1. All of them are short-circuited to each other by a wiring SHd (not shown) to prevent electric breakdown. The inspection terminal TSTd is formed on every other video signal line DL as shown in FIG.

The drain connection terminal DTM is connected to the transparent conductive layer g2.
It is formed of a single layer, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. Gate insulating film G
The semiconductor layer AS formed on the end of the gate insulating film G
This is for etching the edge of I into a tapered shape.
On the terminal DTM, a protective film P for connection with an external circuit is provided.
SV1 has of course been removed.

The lead-out wiring from the matrix portion to the drain terminal portion DTM is a layer d of the same level as the video signal line DL.
1 and d2 are partially formed in the protective film PSV1,
The protective film PSV1 is connected to the transparent conductive film g2. This aims to protect the easily contacted Al layer d2 with the protective film PSV1 and the seal pattern SL as much as possible.

<< Counter Electrode Terminal CTM >> FIGS. 9A and 9B are diagrams showing the connection from the counter electrode signal line CL to its external connection terminal CTM. FIG. 9A shows the plane, and FIG. 4 shows a cross section taken along section line -B. This figure corresponds to the vicinity of the upper left of FIG.

Each counter voltage signal line CL is connected to a common bus line C
B collectively leads to the counter electrode terminal CTM. The common bus line CB has a conductive layer d on the conductive layer g1.
1. A structure in which conductive layers d2 are stacked. this is,
This is to reduce the resistance of the common bus line CB so that the opposing voltage is sufficiently supplied from the external circuit to each opposing voltage signal line CL. As a result, the counter electrode CT is sufficiently transmitted to the terminal pixel, and crosstalk (particularly, crosstalk in the horizontal direction of the screen) due to distortion according to the video signal supplied to the video signal line DL of each counter electrode CT is generated. Generation can be reduced. This structure is characterized in that the resistance of the common bus line can be reduced without particularly adding a new conductive layer. The conductive layer g1 of the common bus line CB is a conductive layer d.
1. No anodization is performed so as to be electrically connected to the conductive layer d2. Also, it is exposed from the gate insulating film GI.

The counter electrode terminal CTM has a structure in which a transparent conductive layer g2 is laminated on a conductive layer g1. The transparent conductive layer g2 covers the conductive layer g1 with the durable transparent conductive layer g2 to protect the surface and prevent electric contact and the like.

In the above-described embodiment, the conductive layer d1 and the conductive layer d2 are stacked on the common bus line CB. However, the present invention is not necessarily limited to these conductive layers. This is because the resistance of the common bus line CB can be reduced in this case as well.

<< Equivalent Circuit of Entire Display Device >> FIG. 10 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X indicates a video signal line DL, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively. Y indicates the scanning signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.

The SUP uses a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source and information for a CRT (cathode ray tube) from a host (upper processing unit) as a TFT liquid crystal display device. This is a circuit that includes a circuit that exchanges information for use.

<< Driving Method >> FIG. 11 shows a driving waveform of the liquid crystal display device of the present invention. The opposite voltage is converted into a binary AC rectangular wave of Vch and Vcl, and the scanning signal Vg (i-1),
Vgh and Vg are applied to the non-selection voltage Vg (i) every scanning period.
It changes with two values of ll. The amplitude value of the counter voltage and the amplitude value of the non-selection voltage are the same. The video signal voltage is a voltage obtained by subtracting half of the amplitude of the counter voltage from the voltage to be applied to the liquid crystal layer.

The counter voltage may be DC, but by converting it to AC, the maximum amplitude of the video signal voltage can be reduced, and a video signal drive circuit (signal-side driver) having a low withstand voltage can be used.

<< Function of Storage Capacitance Cstg >> Storage Capacitance Cstg
Is provided in order to accumulate video information (after the thin film transistor TFT is turned off) written in the pixel for a long time.
In the method of applying an electric field parallel to the substrate surface used in the present invention, unlike the method of applying the electric field perpendicular to the substrate surface, there is almost no capacitance (so-called liquid crystal capacitance) formed by the pixel electrode and the counter electrode. However, the storage capacity Cstg cannot store video information in the pixel. Therefore, in a system in which an electric field is applied in parallel with the substrate surface, the storage capacitor Cstg is an essential component.

The storage capacitor Cstg also works to reduce the influence of the gate potential change ΔVg on the pixel electrode potential Vs when the thin film transistor TFT switches. This situation is represented by the following equation.

[0090]

[Expression 1] ΔVs = {Cgs / (Cgs + Cstg + Cpix)} × ΔV
g where Cgs is the gate electrode G of the thin film transistor TFT.
Parasitic capacitance formed between T and the source electrode SD1, C
pix represents a capacitance formed between the pixel electrode PX and the counter electrode CT, and ΔVs represents a so-called feedthrough voltage corresponding to a change in the pixel electrode potential due to ΔVg. This change ΔVs causes a DC component applied to the liquid crystal LC, but the storage capacitance Cst
The larger the value of g, the smaller the value. The reduction of the DC component applied to the liquid crystal LC
The life of C can be improved, and so-called burn-in in which the previous image remains when the liquid crystal display screen is switched can be reduced.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the area of overlap with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. The pixel electrode potential Vs is susceptible to the gate (scanning) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cstg.

<< Manufacturing Method >> Next, a method of manufacturing the liquid crystal display device on the substrate SUB1 side will be described with reference to FIGS.
This will be described with reference to FIG. In the same figure, the letters at the center are abbreviations of the process names, and the left side shows the processing flow as viewed from the cross-sectional shape near the gate terminal shown in FIG. Except for Step B and Step D, Step A to Step I are classified according to each photographic process, and any cross-sectional view of each process shows a stage where the processing after the photographic process is completed and the photoresist is removed. . In addition,
In the present description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 12 A 3000 mm thick Al-Pd or Al-Pd film is formed on a lower transparent glass substrate SUB1 made of AN635 glass (trade name).
A conductive film g1 made of Si, Al—Ta, Al—Ti—Ta, or the like is provided by sputtering. After the photographic processing, the conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acetic acid. Thereby, the gate electrode GT, the scanning signal line GL, the counter electrode CT, the counter voltage signal line CL, and the electrode P
L1, gate terminal GTM, first conductive layer of common bus line CB, first conductive layer of counter electrode terminal CTM, gate terminal G
Anodizing bus line SHg for connecting TM (not shown)
Then, an anodic oxidation pad (not shown) connected to the anodic oxidation bus line SHg is formed.

Step B, FIG. 12 After the formation of the anodic oxidation mask AO by direct writing, a solution in which 3% tartaric acid is adjusted to PH 6.25 ± 0.05 with ammonia and diluted 1: 9 with ethylene glycol liquid is used. The substrate SUB1 is immersed in an anodizing solution and adjusted so that the formation current density becomes 0.5 mA / cm ² (constant current formation). Next, anodic oxidation is performed until the formation voltage 125 V necessary for obtaining a predetermined Al ₂ O ₃ film thickness is reached. Thereafter, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g1 is anodized to form an anodic oxide film AOF having a thickness of 1800 ° on the gate electrode GT, the scanning signal line GL, the counter electrode CT, the counter voltage signal line CL, and the electrode PL1.

Step C, FIG. 12 A transparent conductive film g2 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photoprocessing, the transparent conductive film g2 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant to form the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the second conductive layer of the counter electrode terminal CTM. I do.

Step D, FIG. 13 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a Si nitride film having a thickness of 2200 °, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus. Is provided with a 2000 ° i-type amorphous Si film, and then a hydrogen gas and a phosphine gas are introduced into a plasma CVD apparatus to form an N (+)-type amorphous Si film having a thickness of 300 °.

Step E, FIG. 13 After photographic processing, SF ₆ and CC are used as dry etching gases.
Using l ₄ , N (+) type amorphous Si film, i type amorphous Si
By selectively etching the film, islands of the i-type semiconductor layer AS are formed.

Step F, FIG. 13 After photo processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Step G, FIG. 14 A conductive film d1 made of Cr having a thickness of 600 .ANG. Is provided by sputtering, and an Al-P film having a thickness of 4000 .ANG.
A conductive film d2 made of d, Al-Si, Al-Ta, Al-Ti-Ta, or the like is provided by sputtering. After the photographic processing, the conductive film d2 is etched with the same liquid as in Step B,
The conductive film d1 is etched with the same liquid as in step A, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the pixel electrode PX, the electrode PL2, the second conductive layer, the third conductive layer and the drain of the common bus line CB are formed. A bus line SHd (not shown) for short-circuiting the terminal DTM is formed. Next, CCl ₄ and SF ₆ were introduced into the dry etching apparatus,
By etching the (+) type amorphous Si film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step H, FIG. 14 An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to form a 1 μm-thick Si nitride film. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo etching technique using SF ₆ as a dry etching gas.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 15 is a top view showing a state where the video signal driving circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.

CHI is a drive IC chip for driving the display panel PNL (the lower five are drive ICs on the vertical scanning circuit side)
The left and right chips are the driving I on the video signal driving circuit side.
C chip). TCP is a tape carrier package in which a driving IC chip CHI is mounted by a tape automated bonding method (TAB), as will be described later with reference to FIGS. 16 and 17, and PCB1 is a driving circuit in which the above-described TCP, capacitors and the like are mounted. The substrate is divided into two, one for a video signal drive circuit and one for a scan signal drive circuit. FG
P is a frame ground pad, and a shield case S
A spring-shaped fragment provided by cutting into the HD is soldered. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1. As shown in the drawing, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material plated with Sn) are sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer.

<< Connection Structure of TCP >> FIG. 16 is a diagram showing a cross-sectional structure of a tape carrier package TCP which forms the scanning signal drive circuit V and the video signal drive circuit H and has the integrated circuit chip CHI mounted on a flexible wiring board. Yes,
FIG. 17 is a cross-sectional view of a main part of the liquid crystal display panel, showing a state where it is connected to a scanning signal circuit terminal GTM in this example.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu. ) Is the integrated circuit C
The HI bonding pads PAD are connected by a so-called face-down bonding method. Terminal TTB, T
The outer ends (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
CRT / TFT conversion circuit / power supply circuit S by soldering
A liquid crystal display panel P is formed on the UP by using an anisotropic conductive film ACF.
NL. The package TCP has a protective film PS whose leading end exposes the connection terminal GTM on the panel PNL side.
The external connection terminal GTM (DTM) is covered with at least one of the protective film PSV1 and the package TCP, so that the external connection terminal GTM (DTM) is covered with V1.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that solder does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by an epoxy resin EPX or the like, and the space between the package TCP and the upper substrate SUB2 is further filled with a silicone resin SIL to multiplex protection.

<< Drive Circuit Board PCB2 >> Drive Circuit Board P
The CB2 has electronic components such as an IC, a capacitor, and a resistor mounted thereon. The drive circuit board PCB2 includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CR (Crystal Control Unit) from a host (upper processing unit).
A circuit SUP including a circuit for converting information for T (cathode ray tube) into information for a TFT liquid crystal display device is mounted. C
J is a connector connection portion to which a connector (not shown) connected to the outside is connected.

The drive circuit board PCB1 and the drive circuit board PC
B2 is electrically connected by a flat cable FC.

<< Overall Configuration of Liquid Crystal Display Module >> FIG.
FIG. 3 is an exploded perspective view showing each component of the liquid crystal display module MDL.

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW and its display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide,
RM is a reflection plate, BL is a backlight fluorescent tube, LCA is a backlight case, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble a module MDL.

The module MDL is a shield case SH
The entirety is fixed by claws and hooks provided on D.

The backlight case LCA includes a backlight fluorescent tube BL, a light diffusion plate SPB, a light diffusion plate, a light guide LCB,
The light guide LCB has a shape to accommodate the reflection plate RM.
The light of the backlight fluorescent tube BL arranged on the side surface is made uniform on the display surface by the light guide LCB, the reflection plate RM, and the light diffusion plate SPB, and emitted to the liquid crystal display panel PNL side.

An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL, and serves as a power supply for the backlight fluorescent tube BL.

Although the present invention has been described in detail with reference to the above embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the scope of the invention. It is. For example, in the above embodiment, an amorphous silicon thin film transistor TFT is used as an active element. However, a polysilicon thin film transistor, a MOS type transistor on a silicon wafer, or an MIM (Metal-Intrins) may be used.
It is also possible to use a two-terminal element such as an ic-metal) diode. The present invention is also applicable to a reflection type liquid crystal display device including at least one of a pair of transparent substrates, a reflection unit, and a polarization unit.

[0114]

As is apparent from the above description,
According to the liquid crystal display device of the present invention, an electric field generated between the pixel electrode and the counter electrode in parallel with the transparent substrate is sufficiently generated, whereby the display quality can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix type color liquid crystal display device of the present invention.

FIG. 2 is a sectional view of a pixel taken along section line 3-3 in FIG. 1;

FIG. 3 is a sectional view of the thin film transistor element TFT taken along section line 4-4 in FIG. 1;

FIG. 4 is a cross-sectional view of the storage capacitor Cstg taken along section line 5-5 in FIG. 1;

FIG. 5 is a plan view illustrating a configuration of a matrix peripheral portion of a display panel.

FIG. 6 is a cross-sectional view showing a scanning signal terminal on the left and a panel edge portion without an external connection terminal on the right.

FIG. 7 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 8 is a plan and cross-sectional view showing the vicinity of a connection between a drain terminal DTM and a video signal line DL.

FIG. 9 is a plan view and a sectional view showing the vicinity of a connection portion of a common electrode terminal CTM, a common bus line CB, and a common voltage signal line CL.

FIG. 10 is a circuit diagram including a matrix portion and its periphery of the active matrix type color liquid crystal display device of the present invention.

FIG. 11 is a diagram showing driving waveforms of the active matrix type color liquid crystal display device of the present invention.

FIG. 12 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 13 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes D to F on the substrate SUB1 side.

FIG. 14 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes G to H on the substrate SUB1 side.

FIG. 15 is a top view showing a state where peripheral driving circuits are mounted on the liquid crystal display panel.

FIG. 16 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.

FIG. 17 is a cross-sectional view of a main part showing a state where the tape carrier package TCP is connected to a scanning signal circuit terminal GTM of the liquid crystal display panel PNL.

FIG. 18 is an exploded perspective view of the liquid crystal display module.

FIG. 19 shows a pattern 1 of a black matrix of the present invention.
It is a figure showing an example.

FIG. 20 is a diagram showing a relationship among a direction of an applied electric field, a rubbing direction, and a transmission axis of a polarizing plate.

[Explanation of symbols]

SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line, CL: counter voltage signal line, PX: pixel electrode, C
T: counter electrode, GI: insulating film, GT: gate electrode, AS
... i-type semiconductor layer, SD: source or drain electrode, PSV: protective film, BM: light shielding film, LC: liquid crystal, TF
T: thin film transistor, g, d: conductive film, Cstg: storage capacitor, AOF: anodized film, AO: anodized mask, G
TM: gate terminal, DTM: drain terminal, CB: common bus line, DTM: common electrode terminal, SHD: shield case, PNL: liquid crystal display panel, SPB: light diffusion plate,
LCB: Light guide, BL: Backlight fluorescent tube, LCA:
Backlight case, RM ... Reflective plate (subscripts are omitted above).

Continuing from the front page (72) Inventor Yasuyuki Mishima 3300 Hayano Mobara-shi, Chiba Prefecture Electronic Device Division, Hitachi, Ltd. (72) Inventor Kazuhiro Ogawa 3300 Hayano Mobara-shi, Chiba Prefecture Electronic Device Division, Hitachi, Ltd. (72 Inventor Masato Oe 3300 Hayano, Mobara City, Chiba Pref.Electronic Devices Division, Hitachi, Ltd. (72) Inventor Katsumi Kondo 7-1-1, Omika-cho, Hitachi City, Ibaraki Pref.Hitachi Research Laboratory, Hitachi, Ltd. Inventor Masahiro Yanai 3300 Hayano Mobara-shi, Chiba Electronic Device Division, Hitachi, Ltd.

Claims (3)

[Claims] 1. A liquid crystal composition layer in which liquid crystal molecules can be twisted and rotated; a first substrate and a second substrate sandwiching the liquid crystal composition layer; and a video signal line formed on the first substrate surface. And at least one pixel electrode to which a video signal is applied via the video signal line, and at least one counter electrode to which a counter voltage is applied are arranged to face each other, and between the pixel electrode and the counter electrode. A liquid crystal display device that controls the amount of twist of liquid crystal molecules by an electric field component generated in the liquid crystal display device, wherein the width of the pixel electrode in the lateral direction exceeds the thickness of the liquid crystal composition layer, and the pixel electrode and the video signal line A liquid crystal display device characterized by being smaller than the distance between 2. An alignment film for controlling an initial alignment direction of liquid crystal molecules of the liquid crystal composition layer, wherein the initial alignment direction is substantially parallel on both of the pair of substrates. 2. The liquid crystal display device according to 1. 3. A liquid crystal display device comprising: a pair of polarizing plates, one of the polarizing plates has a polarization transmission axis substantially parallel to an initial alignment direction of the liquid crystal molecules, and the other polarization transmission axis has a polarization transmission axis of the liquid crystal molecules. The liquid crystal display device according to claim 2, wherein the liquid crystal display device is substantially orthogonal to the initial alignment direction.