JP4055778B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a high-quality active matrix liquid crystal display device having thin film transistor elements.

A color liquid crystal display device referred to as a so-called lateral electric field method is provided on a region surface corresponding to a unit pixel on one or both liquid crystal sides of a transparent substrate disposed opposite to each other with a liquid crystal layer interposed therebetween. A display electrode and a reference electrode are provided, and light transmitted through the liquid crystal layer is modulated by an electric field generated in parallel with the transparent substrate surface between the display electrode and the reference electrode. Such a color liquid crystal display device can recognize a clear image even when observed from a large angle visual field with respect to the display surface, and has been known to be excellent in a so-called wide angle visual field.
The liquid crystal display device having such a configuration is described in detail in Patent Document 1, Patent Document 2, and Patent Document 3, for example.

Japanese Patent Application Publication No. 5-505247 Japanese Examined Patent Publication No. 63-21907 JP-A-6-160878

However, in the liquid crystal display device configured as described above, an unnecessary electric field generated from the video signal line fluctuates the electric field between the display electrode and the reference electrode, and the direction along the video signal line on the display surface In other words, there remains a problem that image quality defects, that is, so-called vertical smears (crosstalk) are generated. Means for solving this problem is described in detail in JP-A-6-202127. However, since the liquid crystal display element configured in this manner is provided with a shield electrode and a potential is supplied to it from the outside, the charge / discharge of current to the capacitor between the shield electrode and the signal electrode is large, and the drive circuit In other words, the load becomes too large, the power consumption is large, or the drive circuit is too large. Further, there is a need for connection means for applying a potential to the shield electrode, resulting in an increase in processes and poor connection. Remained.
The present invention has been made based on such circumstances, and an object of the present invention is to provide a liquid crystal display element that can suppress so-called vertical smear, has good productivity, and achieves low power consumption. is there.

  In order to achieve the above object, according to the present invention, as a first configuration, a plurality of pixels each including a plurality of video signal lines and a plurality of scanning electrodes are provided, and an electric field parallel to the substrate surface is provided in the pixels. In an active matrix liquid crystal display device having a pixel electrode and a counter electrode that can be applied, and a video signal can be supplied from a thin film transistor connected to the video signal line and the scanning signal line to the pixel electrode, the counter electrode and the pixel electrode are planar Active in which an insulating film having a relative dielectric constant of 4 or less is formed on the video signal line, and the counter electrode is formed on the insulating film so as to cover the video signal line A matrix type liquid crystal display device is constituted.

As a second configuration including the first configuration, an active matrix liquid crystal display device in which a pixel electrode is formed on the insulating film is configured.

  As a third structure including the first structure, an active matrix liquid crystal display device in which an insulating film and at least one of a gate insulating film and a protective film of a thin film transistor element are formed in the same pattern is formed.

  As a fourth configuration including the first configuration, an active matrix liquid crystal display device in which a light shielding film is formed in a stripe shape extending in the horizontal direction is configured.

  As a fifth configuration including the first to third configurations, an active matrix liquid crystal display device having an insulating film thickness of 1 μm to 3 μm is configured.

  4. The active matrix liquid crystal display device according to claim 1, wherein the insulating film is a resist material as a sixth structure including the first to third structures.

As a seventh configuration including the first to third configurations, an active matrix liquid crystal display device in which the thickness of the inorganic insulating film protecting the thin film transistor element is 0.05 μm or more and 0.3 μm or less is configured.

  The liquid crystal display element configured as described above is generated by the following three actions.

<Action 1>
Generated from the video signal line by forming the reference electrode on the organic insulating film in a state of being completely overlapped with the video signal line formed on one transparent substrate side in plan view. Almost all unnecessary lines of electric force terminate at the reference electrode. Therefore, crosstalk caused by a leakage electric field peculiar to a display method such as the display method of the present invention using a horizontal electric field is eliminated. Thus, in order to reduce crosstalk, the leakage electric field can be completely shielded from the shield electrodes that have been disposed on both sides of the video signal line or on the opposite substrate in the past. And can be occupied by the reference electrode and the opening. In addition, since it is not necessary to hide the gap between the video signal line and the reference electrode, there is no vertical light shielding film (black matrix). This can drastically improve the low aperture ratio, which is the greatest drawback of the display method using a lateral electric field, and can realize an aperture ratio exceeding 50%. That is, in the present invention, both high aperture ratio and low smear can be achieved.

<Action 2>
The organic insulating film has a relative dielectric constant of about half (relative dielectric constant εr is about 3) compared to the inorganic insulating film. In addition, since the organic film can be easily made thicker than the inorganic film, the distance between the video signal line and the reference electrode is increased. Even if the reference electrode is completely covered with the video signal line, the capacitance formed between the video signal line and the reference electrode can be considerably reduced. Therefore, since the load when viewed from the video signal line is lightened, the wiring propagation delay of the video signal is reduced, the signal voltage can be sufficiently charged to the display electrode, and the driving circuit for driving the video signal line is provided. Can be reduced.

<Action 3>
Since the organic film has very good flatness, the flatness of the substrate on which the organic film is formed can be improved by applying the organic film to the uppermost layer of the substrate on which the active element is formed. Thereby, variation in luminance (transmittance) -voltage characteristics due to variation in gap between substrates can be eliminated, and uniformity in luminance can be improved.

  The present invention, other objects of the present invention, and other features of the present invention will be apparent from the following description with reference to the drawings.

<Active matrix liquid crystal display device>
Hereinafter, an embodiment in which the present invention is applied to an active matrix color liquid crystal display device will be described. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.

<< Planar structure of matrix part (pixel part) >>
FIG. 1 is a plan view showing one pixel of an active matrix type color liquid crystal display device of the present invention and its periphery.

  As shown in FIG. 1, each pixel includes a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode line) CL, and two adjacent video signal lines (drain signal line or line). The vertical signal line (DL) is arranged in a region intersecting with DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX (referred to as a pixel electrode in this embodiment, that is, a display electrode) and a counter electrode CT (referred to as a counter electrode in this embodiment). That is, it is a reference electrode). The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL and counter voltage signal lines CL are arranged in the up-down direction. The video signal lines DL extend in the vertical direction, and a plurality of video signal lines DL are arranged in the horizontal direction. The pixel electrode PX is electrically connected to the thin film transistor TFT via the source electrode SD1, and the counter electrode CT is also electrically connected to the counter voltage signal line CL.

  The pixel electrode PX and the counter electrode CT are opposed to each other, and the optical state of the liquid crystal composition LC is controlled by an electric field substantially parallel to the substrate surface generated between each pixel electrode PX and the counter electrode CT. Control. The pixel electrode PX and the counter electrode CT are formed in a comb-teeth shape, and are each an elongated electrode in the vertical direction of the figure.

  The electrode width of the pixel electrode PX and the counter electrode CT is 6 μm. In order to apply a sufficient electric field to the entire liquid crystal layer with respect to the thickness direction of the liquid crystal layer, this is set to be sufficiently larger than a thickness of 3.9 μm of a liquid crystal composition layer described later. Desirably, it is set to 1.5 times or more of the liquid crystal composition layer. Also, it is made as thin as possible to increase the aperture ratio. The video signal line DL is also 6 μm. The electrode width of the video signal line DL may be slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection.

  The scanning signal line GL sets the electrode width so as to satisfy a resistance value sufficient to propagate the scanning voltage to the gate electrode GT of the pixel on the end side (opposite side of the scanning electrode terminal GTM described later). Further, the counter voltage signal line CL also has a resistance value sufficient to apply a counter voltage to the counter electrode CT of the pixel on the end side (the pixel farthest from common bus lines CB1 and CB2, which will be described later, that is, a pixel intermediate between CB1 and CB2). The electrode width is set so as to satisfy.

  On the other hand, the electrode interval between the pixel electrode PX and the counter electrode CT varies depending on the liquid crystal material used. This is because the electric field strength that achieves the maximum transmittance differs depending on the liquid crystal material, so the electrode spacing is set according to the liquid crystal material, and the maximum amplitude of the signal voltage set by the withstand voltage of the video signal drive circuit (signal side driver) This is because the maximum transmittance can be obtained within the above range. When a liquid crystal material described later is used, the electrode interval is about 15 μm.

<< Cross-sectional structure of matrix part (pixel part) >>
2 is a cross-sectional view taken along line 6-6 of FIG. 1, FIG. 3 is a cross-sectional view of thin film transistor TFT taken along line 7-7 of FIG. 1, and FIG. 4 is a storage capacitor Cstg taken along line 8-8 of FIG. FIG. As shown in FIGS. 5 to 7, a thin film transistor TFT, a storage capacitor Cstg, and an electrode group are formed on the lower transparent glass substrate SUB1 side based on the liquid crystal composition layer LC, and a color filter is formed on the upper transparent glass substrate SUB2 side. An FIL and a light shielding film (black matrix) BM are formed.

  In addition, alignment films ORI1 and ORI2 for controlling the initial alignment of the liquid crystal are provided on the inner surfaces (liquid crystal LC side) of the transparent glass substrates SUB1 and SUB2, and the outer surfaces of the transparent glass substrates SUB1 and SUB2. A polarizing plate is provided on the surface.

<< TFT substrate >>
First, the configuration of the lower transparent glass substrate SUB1 side (TFT substrate) will be described in detail.

<< Thin Film Transistor TFT >>
The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases.

  As shown in FIG. 3, the thin film transistor TFT includes a gate electrode GT, an insulating film GI, an i-type semiconductor layer AS made of i-type (intrinsic, intrinsic, undoped with conductivity-determining impurity) amorphous silicon (Si). And a pair of source electrode SD1 and drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so that the source and drain are interchanged during operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.

<< Gate electrode GT >>
The gate electrode GT is formed continuously with the scanning signal line GL, and a part of the scanning signal line GL is configured to be the gate electrode GT. The gate electrode GT is a portion exceeding the active region of the thin film transistor TFT. In this example, the gate electrode GT is formed of a single-layer conductive film g3. For example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used as the conductive film g3, but the conductive film g3 is not limited thereto.

<< Scanning signal line GL >>
The scanning signal line GL is composed of a conductive film g3. The conductive film g3 of the scanning signal line GL is formed in the same manufacturing process as that of the conductive film g3 of the gate electrode GT and is integrally formed. Through this scanning signal line GL, a gate voltage (scanning voltage) Vg is supplied from an external circuit to the gate electrode GT. In this example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering, for example, is used as the conductive film g3. Further, the scanning signal line GL and the gate electrode GT are not limited to the chromium-molybdenum alloy, but may be a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum to reduce resistance, for example. Good. Further, the portion intersecting with the video signal line DL may be narrowed to reduce the probability of short circuit with the video signal line DL, or it may be bifurcated so that it can be separated by laser trimming even if shorted.

<< Counter voltage signal line CL >>
The counter voltage signal line CL is composed of a conductive film g3. The conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, the scanning signal line GL, and the counter electrode CT, and is configured to be electrically connected to the counter electrode CT. Yes. The counter voltage signal line CL supplies the counter voltage Vcom from the external circuit to the counter electrode CT. Further, the counter voltage signal line CL is not limited to the chromium-molybdenum alloy, and may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum, for example, to reduce resistance. Further, the portion intersecting with the video signal line DL may be narrowed to reduce the probability of short circuit with the video signal line DL, or it may be bifurcated so that it can be separated by laser trimming even if shorted.

<Insulating film GI>
The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected, and is formed to a thickness of 2000 to 4500 mm (in this embodiment, about 3500 mm). The insulating film GI also functions as an interlayer insulating film between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL, and contributes to their electrical insulation.

<< i-type semiconductor layer AS >>
The i-type semiconductor layer AS is made of amorphous silicon and has a thickness of 150 to 2500 mm (in this embodiment, a film thickness of about 1200 mm). The layer d0 is an N (+) type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, only where the i type semiconductor layer AS is present on the lower side and the conductive layer d3 is present on the upper side. Is left behind.

  The i-type semiconductor layer AS and the layer d0 are also provided between the scanning signal line GL and the crossing portion (crossover portion) between the counter voltage signal line CL and the video signal line DL. This crossing portion i-type semiconductor layer AS reduces a short circuit between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL at the crossing portion.

<< Source electrode SD1, drain electrode SD2 >>
Each of the source electrode SD1 and the drain electrode SD2 includes a conductive film d3 that is in contact with the N (+) type semiconductor layer d0. .

  The conductive film d3 is made of a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering and is formed to a thickness of 500 to 3000 mm (in this embodiment, about 2500 mm). Since the Cr—Mo film has low stress, it can be formed with a relatively large film thickness, which contributes to reducing the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi2, TiSi2, TaSi2, WSi2) film may be used in addition to the Cr-Mo film, and aluminum or the like. A laminated structure may be used.

<< Video signal line DL >>
The video signal line DL is composed of a conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2. The video signal line DL is formed integrally with the drain electrode SD2. In this example, the conductive film d3 is made of a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering, and is formed to a thickness of 500 to 3000 mm (in this embodiment, about 2500 mm). Since the Cr—Mo film has low stress, it can be formed with a relatively large film thickness, which contributes to reducing the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, in addition to the Cr—Mo film, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi2, TiSi2, TaSi2, WSi2) film may be used. In order to prevent this, a laminated structure with aluminum or the like may be used.

<< Storage capacity Cstg >>
The conductive film d3 is formed so as to overlap with the counter voltage signal line CL in the source electrode SD2 portion of the thin film transistor TFT. As is apparent from FIG. 1, this superposition forms a storage capacitor (capacitance element) Cstg having the source electrode SD2-d3 as one electrode and the counter voltage signal CL as the other electrode. The dielectric film of the storage capacitor Cstg is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT.

  As shown in FIG. 1, the storage capacitor Cstg is formed in a part of the counter voltage signal line CL in plan view.

<< Protective film PSV1 >>
A protective film PSV1 is provided on the thin film transistor TFT. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and a film having high transparency and good moisture resistance is used. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and is formed with a film thickness of about 0.05 to 0.3 μm. Since the main purpose of the protective film PSV1 is to protect the back channel portion of the thin film transistor element TFT, that is, to stabilize the threshold voltage Vth, in this embodiment, the protective film PSV1 is formed in an island shape only in the thin film transistor TFT portion. Thereby, the curvature of the board | substrate by the stress of protective film PSV1 can be reduced significantly.

  The protective film PSV1 is removed so as to expose the external connection terminals DTM and GTM. Regarding the thickness relationship between the protective film PSV1 and the insulating film GI, the former is thickened considering the protective effect, and the latter is thinned considering the mutual conductance gm of the transistor.

<< Organic protective film PSV2 >>
The protective film PSV1 is provided with an organic film PSV2. The organic film PSV2 is formed for the following purposes, and a film having high transparency and a low dielectric constant of about 3 is used. The organic film PSV2 is formed of a resist film formed by a coating apparatus, for example, and is formed with a film thickness of about 1 to 3 μm. Thereby, the capacity | capacitance between a video signal line and the counter electrode covered on it can be reduced significantly. As a result, the load on the video signal line is greatly reduced, and the circuit scale of the drive LSI for driving the video signal can be greatly reduced. Further, as described in the operation, the organic protective film PSV2 is also useful for improving the flatness of the thin film transistor substrate. This is because the organic film can be formed with better flatness than the inorganic film.

  The organic film PSV2 is removed so as to expose the external connection terminals DTM and GTM. Further, in the pixel portion, through holes TH2 and TH1 are provided for electrical connection between the counter voltage signal line CL and a counter electrode CT described later and for electrical connection between the source electrode SD2 and the pixel electrode PX. . In the through hole TH2, since the organic film PSV2 and the insulating film GI are processed at once, there is a hole up to the g3 layer, and in the through hole TH1, a hole up to the d3 layer is formed because it is blocked by d3.

  In this embodiment, an organic film having a relative dielectric constant of about 3 is used, but 4 or less is preferable in order to bring out the effects of this embodiment.

<< Pixel electrode PX >>
The pixel electrode PX is formed on the organic film PSV2 with the transparent conductive layer i1. This transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering, and is formed to a thickness of 100 to 2000 mm (in this embodiment, a film thickness of about 1400 mm). . The pixel electrode PX is connected to the source electrode SD2 through the through hole TH1.

  Since the pixel electrode becomes transparent as in this embodiment, the maximum transmittance at the time of white display is improved by the transmitted light of the portion, so that a brighter display is performed than when the pixel electrode is opaque. be able to. At this time, as will be described later, when no voltage is applied, the liquid crystal molecules maintain the initial alignment state, and the arrangement of the polarizing plates is configured so as to display black in that state (a normally black mode is set). Therefore, even if the pixel electrode is transparent, light of that portion is not transmitted, and high-quality black can be displayed. Thereby, the maximum transmittance can be improved and a sufficient contrast ratio can be achieved.

<< Counter electrode CT >>
The counter electrode CT is formed on the organic film PSV2 by the transparent conductive layer i1. This transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering, and is formed to a thickness of 100 to 2000 mm (in this embodiment, a film thickness of about 1400 mm). . The counter electrode CT is connected to the counter voltage signal line CL through the through hole TH2. Similar to the pixel electrode PX, by making the counter electrode transparent, the maximum transmittance when performing white display is improved. Further, the counter electrode CT is configured to completely cover the video signal line DL, and most of the electric lines of force from the video signal line DL are terminated at the counter electrode CT. As a result, the leakage electric field from the video signal line peculiar to the horizontal electric field method is completely eliminated, so that the crosstalk is completely eliminated. This is an effect peculiar to the active matrix type liquid crystal display device using the horizontal electric field method.

  Further, the counter voltage CT is applied to the counter electrode CT. In this embodiment, the counter voltage Vcom is a feed generated when the thin film transistor element TFT is turned off from an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL. The potential is set lower by the through voltage ΔVs.

<Color filter substrate>
Next, returning to FIGS. 1 and 2, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.

<< Light shielding film BM >>
A light shielding film is provided on the upper transparent glass substrate SUB2 side so that transmitted light from an unnecessary gap (gap other than between the pixel electrode PX and the counter electrode CT) is emitted to the display surface side and the contrast ratio or the like is not lowered. A BM (so-called black matrix) is formed. The light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched by the upper and lower light shielding films BM and the large gate electrode GT, and is not exposed to external natural light or backlight light.

  FIG. 1 shows an example of the pattern of the light shielding film BM.

In this embodiment, a matrix pattern having holes in the display portion of the pixel is used. In this embodiment, the light shielding film BM uses a chromium thin film. Further, chromium oxide and chromium nitride are formed on the glass surface side of the chromium thin film. This is to reduce the reflectance on the glass surface side and to make the display surface of the liquid crystal display device have low reflection.
In addition, the effective display area of each row and column is partitioned by the light shielding film BM. Therefore, the outline of the pixels in each row is clarified by the light shielding film BM.

  Further, the light shielding film BM is also formed in a frame shape in the peripheral portion, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. The peripheral light shielding film BM is extended to the outside of the seal portion SL to prevent leakage light such as reflected light from a mounting device such as a personal computer from entering the matrix portion, and light such as a backlight is out of the display area. It also prevents leaks. On the other hand, the light-shielding film BM is retained about 0.3 to 1.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cutting region of the substrate SUB2.

  In this embodiment, a metal film having a high light-shielding property is used even for a thin film. However, an insulating light-shielding film may be used if a sufficient light-shielding property is obtained.

<Color filter FIL>
The color filter FIL is formed in stripes by repeating red, green, and blue at positions facing the pixels. The color filter FIL is formed so as to overlap the edge portion of the light shielding film BM.

  The color filter FIL can be formed as follows. First, a dye base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base material other than the red filter forming region is removed by a photolithography technique. Thereafter, the dyed substrate is dyed with a red pigment, and a fixing process is performed to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing the same process. A dye may be used for dyeing.

<< Overcoat film OC >>
The overcoat film OC is provided for preventing leakage of the dye of the color filter FIL to the liquid crystal composition layer LC and for flattening the steps by the color filter FIL and the light shielding film BM. The overcoat film OC is formed of a transparent resin material such as an acrylic resin or an epoxy resin. Further, as the overcoat film o C, an organic film such as polyimide having good fluidity may be used.

<Liquid crystal layer and deflection plate>
Next, a liquid crystal layer, an alignment film, a polarizing plate, etc. are demonstrated. .

<Liquid crystal layer>
As the liquid crystal material LC, nematic liquid crystal having a positive dielectric anisotropy Δε, a value of 13.2, and a refractive index anisotropy Δn of 0.081 (589 nm, 20 ° C.) is used. The thickness (gap) of the liquid crystal layer is 3.9 μm, and the retardation Δn · d is 0.316. With this retardation Δn · d value, the maximum transmittance can be obtained when the liquid crystal molecules are rotated 45 ° from the rubbing direction to the electric field direction in combination with an alignment film and a polarizing plate, which will be described later. Transmitted light with almost no property can be obtained. The retardation is preferably in the range of 0.25 to 0.32 μm in order to obtain a sufficient transmission term. The thickness (gap) of the liquid crystal layer is controlled by polymer beads.

  The liquid crystal material LC is not particularly limited, and the dielectric anisotropy Δε may be negative. Further, as the dielectric anisotropy Δε is larger, the driving voltage can be reduced. Further, when the refractive index anisotropy Δn is small, the thickness (gap) of the liquid crystal layer can be increased, the liquid crystal sealing time can be shortened, and the gap variation can be reduced.

The specific resistance of the liquid crystal composition is 10 ⁹ Ωcm or more and 10 ¹⁴ Ωcm or less, preferably 10 ¹¹ Ωcm or more and 10 ¹³ Ωcm or less. In this method, even when the resistance of the liquid crystal composition is low, the voltage charged between the pixel electrode and the counter electrode can be sufficiently maintained, and the lower limit is 10 ⁹ Ωcm, preferably 10 ¹¹ Ωcm. This is because the pixel electrode and the counter electrode are formed on the same substrate. Further, if the resistance is too high, it is difficult to reduce static electricity that has entered the manufacturing process, so that it is 10 ¹⁴ Ωcm or less, preferably 10 ¹³ Ωcm or less.

  Further, the twist elastic constant K2 of the liquid crystal material is preferably small. Specifically, 2 pN or more is good.

《Alignment film》
As the alignment film ORI, polyimide is used. The rubbing direction is parallel to each other on the upper and lower substrates, and the angle formed with the applied electric field direction is 75 °.

  The angle formed between the rubbing direction and the applied electric field direction is 45 ° or more and less than 90 ° when the dielectric anisotropy Δε of the liquid crystal material is positive, and 0 ° when the dielectric anisotropy Δε is negative. Must be less than 45 °.

"Polarizer"
As the polarizing plate POL, G1220DU manufactured by Nitto Denko Corporation is used, the polarizing transmission axis MAX1 of the lower polarizing plate POL1 is made to coincide with the rubbing direction RDR, and the polarizing transmission axis MAX2 of the upper deflecting plate POL2 is made orthogonal thereto. As a result, a normally closed characteristic in which the transmittance increases as the voltage applied to the pixel of the present invention (the voltage between the pixel electrode PX and the counter electrode CT) increases can be obtained. When it is added, a good quality black display can be achieved. Further, the relationship between the upper and lower polarizing plates may be reversed, and there is no significant change in characteristics.

In this embodiment, the polarizing plate is made conductive to take measures against display defects and EMI due to external static electricity. Concerning conductivity, it is desirable that the sheet resistance is 10 ⁸ Ω / b or less if it is only for countermeasures against static electricity, and 10 ⁴ Ω / b or less if measures are taken against EMI. Moreover, you may provide a conductive layer in the back surface (surface which adhere | attaches a polarizing plate) of the clamping surface of the liquid crystal composition of a glass substrate.

<Configuration around the matrix>
FIG. 5 is a view showing a principal plane around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2. FIG. 6 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

  In the manufacture of this panel, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for improving throughput, standardized any breed for shared manufacturing facilities if large size After processing the glass substrate of the size, the glass substrate is reduced to a size suitable for each type, and in any case, the glass is cut after going through a single process. FIG. 5 and FIG. 6 show the latter example. Both of FIG. 5 and FIG. 6 show the upper and lower substrates SUB1 and SUB2 after cutting, and LN indicates the edge before cutting both substrates. In any case, the size of the upper substrate SUB2 is lower so that the external connection terminal groups Tg, Td and the terminal COT (subscript omitted) are present in the completed state (the upper side and the left side in the drawing) are exposed. It is limited to the inner side than the substrate SUB1. The terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, which will be described later, and a tape carrier package TCP (FIGS. 16 and 17) on which an integrated circuit chip CHI is mounted. Multiple units are named collectively. The lead-out wiring from the matrix portion of each group to the external connection terminal portion is inclined as it approaches both ends. This is because the terminals DTM and GTM of the display panel PNL are matched with the arrangement pitch of the package TCP and the connection terminal pitch in each package TCP. The counter electrode terminal COT is a terminal for applying a counter voltage to the counter electrode CT from an external circuit. The counter voltage signal line CL of the matrix portion is drawn to the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the counter voltage signal lines are grouped together by a common bus line CB and connected to the counter electrode terminal COT. .

  A seal pattern SL is formed between the transparent glass substrates SUB1 and SUB2 so as to seal the liquid crystal LC along the edge except for the liquid crystal sealing inlet INJ. The sealing material is made of, for example, an epoxy resin.

  The layers of the alignment films ORI1 and ORI2 are formed inside the seal pattern SL. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively. The liquid crystal LC is sealed in a region partitioned by a seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 that set the direction of liquid crystal molecules. The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

  In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2 side, so that the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are formed. And the liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with an epoxy resin or the like, and the upper and lower substrates are cut.

<Gate terminal section>
FIG. 7 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, FIG. 7A is a plan view, and FIG. 7B shows a cross section taken along the line BB of FIG. 7A. The figure corresponds to the lower part of FIG. 5 and the diagonal wiring portion is represented by a straight line for convenience.
In the drawing, the Cr—Mo layer g3 is hatched for easy understanding.

  The gate terminal GTM is composed of a Cr—Mo layer g3 and a transparent conductive layer i1 for further protecting the surface of the Cr—Mo layer g3 and improving the reliability of connection with TCP (Tape Carrier Package). The transparent conductive layer i1 uses a transparent conductive film ITO formed in the same process as the pixel electrode PX.

  In the plan view, the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located at the left end is exposed from them so as to be able to make electrical contact with an external circuit. . In the figure, only one pair of the gate line GL and the gate terminal is shown, but actually, a plurality of such pairs are arranged vertically as shown in FIG. 5 to form a terminal group Tg (FIG. 5). In the manufacturing process, the left end of the gate terminal extends beyond the cutting region of the substrate and is short-circuited by the wiring SHg (not shown). This is useful for preventing electrostatic breakdown during rubbing of the alignment film ORI1 during the manufacturing process.

<< Drain terminal DTM >>
FIG. 8 is a diagram showing the connection from the video signal line DL to the external connection terminal DTM, FIG. 8A shows the plane, and FIG. 8B shows a cross section taken along the line BB of FIG. 8A. This figure corresponds to the vicinity of the upper right of FIG. 5 and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end of the substrate SUB1.

  TSTd is an inspection terminal, to which no external circuit is connected, but is wider than the wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal DTM is also wider than the wiring portion so that it can be connected to an external circuit. The external connection drain terminals DTM are arranged vertically, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and are further extended beyond the cutting line of the substrate SUB1, during the manufacturing process. All of them are short-circuited to each other by wiring SHd (not shown) in order to prevent electrostatic breakdown. The inspection terminals TSTd are formed on every other video signal line DL as shown in FIG.

The drain connection terminal DTM is formed of the transparent conductive layer i1, and is connected to the video signal line DL at a portion where the protective film PSV1 is removed. The transparent conductive film i1 is made of the transparent conductive film ITO formed in the same process as the pixel electrode PX as in the case of the gate terminal GTM.
A layer d3 having the same level as that of the video signal line DL is formed in the lead-out wiring from the matrix portion to the drain terminal portion DTM.

<< Counter electrode terminal CTM >>
FIG. 9 is a diagram showing the connection from the counter voltage signal line CL to the external connection terminal CTM, FIG. 9A shows the plane, and FIG. 9B shows a cross section taken along the line BB in FIG. 9A. This figure corresponds to the vicinity of the upper left of FIG.

  Each counter voltage signal line CL is gathered by a common bus line CB1 and led to the counter electrode terminal CTM. The common bus line CB has a structure in which the conductive layer 3 is stacked on the conductive layer g3 and these are electrically connected by the transparent conductive layer i1. This is to reduce the resistance of the common bus line CB so that the counter voltage is sufficiently supplied from the external circuit to each counter voltage signal line CL. This structure is characterized in that the resistance of the common bus line can be lowered without particularly loading a conductive layer.

  The counter electrode terminal CTM has a structure in which a transparent conductive layer i1 is laminated on a conductive layer g3. This transparent conductive film i1 uses the transparent conductive film ITO formed in the same process as the pixel electrode PX as in the case of the other terminals. The conductive layer g3 is covered with the transparent conductive layer i1 having good durability in order to protect the surface by the transparent conductive layer i1 and prevent electrolytic corrosion and the like. The transparent conductive layer i1, the conductive layer g3, and the conductive layer d3 are electrically connected by forming a through hole through the protective film PSV1 and the insulating film GI.

  On the other hand, FIG. 10 is a diagram showing a connection from the other end of the counter voltage signal line CL to the external connection terminal CTM2, FIG. 10A shows a plan view thereof, and FIG. 10B is a sectional view taken along the line BB of FIG. A cross section is shown. The figure corresponds to the vicinity of the upper right of FIG. Here, in the common bus line CB2, the other end (gate terminal GTM side) of each counter voltage signal line CL is gathered together and led to the counter electrode terminal CTM2. The difference from the common bus line CB1 is that the conductive layer d3 and the transparent conductive layer i1 are formed so as to be insulated from the scanning signal line GL. Insulation with the scanning signal line GL is performed by the insulating film GI.

<< Equivalent circuit for the entire display device >>
FIG. 11 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.
In the figure, X means a video signal line DL, and subscripts G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means the scanning signal line GL, and subscripts 1, 2, 3,..., End are added according to the order of scanning timing.
The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.
SUP uses CRT (cathode ray tube) information from a power supply circuit or host (high-order processing unit) to obtain a plurality of stabilized voltage sources divided from one voltage source, and information for TFT liquid crystal display devices. This is a circuit including a circuit to be replaced.

<Driving method>
FIG. 12 shows drive waveforms of the liquid crystal display device of this example. The counter voltage Vch is a constant voltage. The scanning signal Vg takes an on level every scanning period, and the other takes an off level. The video signal voltage is applied so that the positive and negative electrodes are inverted every frame and transmitted to one pixel with an amplitude twice that of the voltage to be applied to the liquid crystal layer. Here, the polarity of the video signal voltage Vd is inverted every column, and the polarity is inverted every row. Accordingly, the pixels whose polarities are reversed are arranged vertically and horizontally, and flicker and crosstalk (smear in the horizontal direction) can be made difficult to occur. Further, the counter voltage Vc is set to a voltage that is a certain amount less than the center voltage of the polarity inversion of the video signal voltage. This corrects the feedthrough voltage that occurs when the thin film transistor element changes from on to off, and is applied to apply an alternating voltage with a small direct current component to the liquid crystal. , Because deterioration becomes severe).

<Function of storage capacity Cstg>
The storage capacitor Cstg is provided for storing video information (after the thin film transistor TFT is turned off) written in the pixel for a long time. The method of applying the electric field used in the present invention in parallel to the substrate surface differs from the method of applying the electric field perpendicular to the substrate surface because there is almost no capacitance (so-called liquid crystal capacitance) composed of the pixel electrode and the counter electrode. The storage capacitor Cstg cannot store the video information in the pixel. Therefore, the storage capacitor Cstg is an indispensable component in the method in which the electric field is applied parallel to the substrate surface.
The storage capacitor Cstg also works to reduce the influence of the gate potential change ΔVg on the pixel electrode potential Vs when the thin film transistor TFT is switched. This situation can be expressed as follows.
ΔVs = {Cgs / (Cgs + Cstg + Cpix)} × ΔVg
Here, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT, Cpix is a capacitance formed between the pixel electrode PX and the counter electrode CT, and ΔVs is a pixel electrode potential by ΔVg. This represents a so-called feedthrough voltage. This change ΔVs causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the storage capacitor Cstg is increased. Reduction of the direct current component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.
As described above, since the gate electrode GT is enlarged so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and thus the parasitic capacitance Cgs is increased. The potential Vs has the adverse effect of being easily affected by the gate (scanning) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cstg.

"Production method"
Next, a manufacturing method on the substrate SUB1 side of the liquid crystal display device described above will be described with reference to FIGS. In the figure, the central letter is an abbreviation of the process name, the left side shows the thin film transistor TFT portion shown in FIG. 3, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal shown in FIG. Processes A to G, except for process B and process D, are divided corresponding to each photographic process, and any cross-sectional view of each process shows a stage where the processing after the photographic process is finished and the photoresist is removed. . In this description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask and development thereof, and repeated description is avoided. This will be described in accordance with the divided steps.

Process A, FIG. 13
On the lower transparent glass substrate SUB1 made of AN635 glass (trade name), a conductive film g3 made of Cr—Mo or the like having a film thickness of 2000 mm is provided by sputtering. After the photographic processing, the conductive film g3 is selectively etched with ceric ammonium nitrate. Thereby, the gate line connecting the gate electrode GT, the scanning signal line GL, the counter voltage signal line CL, the gate terminal GTM, the first conductive layer of the common bus line CB1, the first conductive layer of the counter electrode terminal CTM1, and the gate terminal GTM. SHg (not shown) is formed.

Process B, FIG. 13
Introducing ammonia gas, silane gas, and nitrogen gas into the plasma CVD apparatus to provide a Si nitride film with a thickness of 3500 mm, introducing silane gas and hydrogen gas into the plasma CVD apparatus, and an i-type amorphous film with a thickness of 1200 mm After providing the Si film, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to provide an N (+) type amorphous Si film having a thickness of 300 mm.

Process C, FIG.
After the photo processing, the N (+) type amorphous Si film and the i type amorphous Si film are selectively etched using SF6 and CCl4 as dry etching gases, thereby forming the island of the i type semiconductor layer AS. Form.

Process D, FIG. 14
A conductive film d3 made of Cr having a thickness of 300 mm is provided by sputtering. After the photo processing, the conductive film d3 is etched with the same solution as in step A, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the first conductive layer of the common bus line CB2, and the bus line that short-circuits the drain terminal DTM. SHd (not shown) is formed. Next, CCl4 and SF6 are introduced into a dry etching apparatus to etch the N (+) type amorphous Si film, thereby selectively removing the N (+) type semiconductor layer d0 between the source and drain. . After patterning the conductive film d3 with a mask pattern, the N (+) type semiconductor layer d0 is removed using the conductive film d3 as a mask. That is, the N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS is removed by self-alignment except for the conductive film d1 and the conductive film d2. At this time, since the N (+) type semiconductor layer d0 is etched so that the entire thickness thereof is removed, the surface portion of the i type semiconductor layer AS is also slightly etched, but the degree is controlled by the etching time. do it.

Process E, FIG. 14
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a Si nitride film having a thickness of 0.3 μm. After the photographic processing, the protective film PSV1 is patterned by selectively etching the Si nitride film using SF6 as a dry etching gas.

Process F, FIG. 15
After the photosensitive organic film PSV2 is applied, it is exposed and patterned with a photomask. Using this as a mask, the insulating film GI is dry-etched by the same method as in step E. Therefore, the organic film PSV2 and the insulating film GI are patterned with the same photomask and processed together.

Process G, FIG. 15
A transparent conductive film i1 made of an ITO film having a thickness of 1400 mm is provided by sputtering. After the photographic processing, the transparent conductive film i1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the second conductive layers of the counter electrode terminals CTM1 and CTM2 Form.

<< Display Panel PNL and Drive Circuit Board PCB1 >>
FIG. 16 is a top view showing a state in which the video signal driving circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.
CHI is a driving IC chip for driving the display panel PNL (the lower five are driving IC chips on the vertical scanning circuit side, and the left ten are driving IC chips on the video signal driving circuit side). TCP is a tape carrier package in which a driving IC chip CHI is mounted by a tape automated bonding method (TAB) as will be described later with reference to FIGS. 13 and 14, and PCB 1 is a driving circuit in which the TCP, capacitor, etc. are mounted. The substrate is divided into two for a video signal driving circuit and for a scanning signal driving circuit. FGP is a frame ground pad, and a spring-shaped piece cut into the shield case SHD is soldered. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1. As shown in the figure, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material Sn plated) are sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer.

<< TCP connection structure >>
FIG. 17 is a diagram showing a cross-sectional structure of a tape carrier package TCP that constitutes the scanning signal driving circuit V and the video signal driving circuit H and in which an integrated circuit chip CHI is mounted on a flexible wiring board. FIG. It is principal part sectional drawing which shows the state connected to the terminal GTM for scanning signal circuits of the panel in this example.

  In the figure, TTB is an input terminal / wiring part of the integrated circuit CHI, and TTM is an output terminal / wiring part of the integrated circuit CHI, which is made of, for example, Cu, and each inner tip (commonly called inner lead) Bonding pads PAD of the integrated circuit CHI are connected by a so-called face-down bonding method. The outer tips (commonly referred to as outer leads) of the terminals TTB and TTM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively, and the anisotropic conductive film ACF is connected to the CRT / TFT conversion circuit / power supply circuit SUP by soldering or the like. Is connected to the liquid crystal display panel PNL. The package TCP is connected to the panel so that the tip thereof covers the protective film PSV1 exposing the connection terminal GTM on the panel PNL side. Therefore, the external connection terminal GTM (DTM) is at least the protective film PSV1 or the package TCP. On the other hand, since it is covered, it is strong against electric contact.

  BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that the solder does not stick to an extra portion during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX after cleaning, and a silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to multiplex the protection.

<< Drive circuit board PCB2 >>
The drive circuit board PCB2 is mounted with electronic components such as an IC, a capacitor, and a resistor. The drive circuit board PCB2 is provided with a power supply circuit for obtaining a plurality of stabilized voltage sources divided from one voltage source and information for a CRT (cathode ray tube) from a host (high-order processing unit). A circuit SUP including a circuit for converting into information for a TFT liquid crystal display device is mounted. CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected.
The drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a flat cable FC.

<Overall configuration of liquid crystal display module>
FIG. 19 is an exploded perspective view showing each component of the liquid crystal display module MDL.
SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW its display window, PNL is a liquid crystal display panel, SPB is a light diffusing plate, LCB is a light guide, RM is a reflector, BL is a backlight fluorescent tube LCA is a backlight case, and the modules MDL are assembled by stacking the members in a vertical arrangement relationship as shown in the figure.
The module MDL is fixed in its entirety by claws and hooks provided in the shield case SHD.
The backlight case LCA has a shape that accommodates the backlight fluorescent tube BL, the light diffusion plate SPB light diffusion plate, the light guide LCB, and the reflection plate RM, and is disposed on the side surface of the light guide LCB. The BL light is converted into a uniform backlight on the display surface by the light guide LCB, the reflection plate RM, and the light diffusion plate SPB, and emitted to the liquid crystal display panel PNL side.
An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL and serves as a power source for the backlight fluorescent tube BL. The effect of the liquid crystal display element configured as described above arises from the following three actions.

<Action 1>
Generated from the video signal line by forming the reference electrode on the organic insulating film in a state of being completely overlapped with the video signal line formed on one transparent substrate side in plan view. Almost all unnecessary lines of electric force terminate at the reference electrode. Therefore, crosstalk caused by a leakage electric field peculiar to a display method such as the display method of the present invention using a horizontal electric field is eliminated. Thus, in order to reduce crosstalk, the leakage electric field can be completely shielded from the shield electrodes that have been disposed on both sides of the video signal line or on the opposite substrate in the past. And can be occupied by the reference electrode and the opening. In addition, since it is not necessary to hide the gap between the video signal line and the reference electrode, there is no vertical light shielding film (black matrix). This can drastically improve the low aperture ratio, which is the greatest drawback of the display method using a lateral electric field, and can realize an aperture ratio exceeding 50%. That is, in the present invention, both high aperture ratio and low smear can be achieved.

<Action 2>
The organic insulating film has a relative dielectric constant of about half (relative dielectric constant εr is about 3) compared to the inorganic insulating film. In addition, since the organic film can be easily made thicker than the inorganic film, the distance between the video signal line and the reference electrode is increased. Even if the reference electrode is completely covered with the video signal line, the capacitance formed between the video signal line and the reference electrode can be considerably reduced. Therefore, since the load when viewed from the video signal line is lightened, the wiring propagation delay of the video signal is reduced, the signal voltage can be sufficiently charged to the display electrode, and the driving circuit for driving the video signal line is provided. Can be reduced.

<Action 3>
Since the organic film has very good flatness, the flatness of the substrate on which the organic film is formed can be improved by applying the organic film to the uppermost layer of the substrate on which the active element is formed. Thereby, variation in luminance (transmittance) -voltage characteristics due to variation in gap between substrates can be eliminated, and uniformity in luminance can be improved.
As is apparent from the above description, in the liquid crystal display device of this embodiment, it is possible to suppress so-called vertical smear, which is an essential problem in the liquid crystal display device using the horizontal electric field method. This can be achieved simultaneously with reduction of power and reduction of the peripheral circuit scale. Furthermore, the uniformity of brightness can be improved.

  This example is the same as Example 1 except for the following requirements. FIG. 20 is a plan view of the pixel, and FIG. 21 is a cross-sectional view of the comb electrode portion.

<< Pixel electrode PX >>
In this embodiment, the pixel electrode PX is composed of a conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2. Further, the pixel electrode PX is formed integrally with the source electrode SD1.
In this embodiment, in addition to the effects of the first embodiment, the transmittance is sacrificed, but contact failure with the pixel electrode PX can be avoided. Further, since the pixel electrode PX is covered with the insulating film (protective film PSV1), the possibility of direct current flowing through the liquid crystal when there is an alignment film defect is reduced, and the liquid crystal is not deteriorated. Further, the reliability is improved.

This example is the same as Example 1 except for the following requirements. FIG. 22 is a cross-sectional view of the pixel of this example.
<< Protective film PSV1, Organic protective film PSV2 >>
In this embodiment, the protective film PSV1 and the organic film PSV2 are collectively removed so that the external connection terminals DTM and GTM are exposed. Therefore, unlike the first embodiment, the protective film PSV1 is formed in most parts of the pixel. In the pixel portion, through holes TH2 and TH1 are used for electrical connection between the counter voltage signal line CL and a counter electrode CT (described later) and between the source electrode SD2 and the pixel electrode PX. In TH2, the organic film PSV2, the protective film PSV1, and the insulating film GI are collectively processed to have a hole up to the g3 layer. In the through hole TH1, the organic film PSV2 and the protective film PSV1 are collectively processed and blocked by d3. Therefore, there is a hole up to the d3 layer.

  In this embodiment, since a resist material is used for the organic film PSV2, first, the resist material is exposed by photolithography, and the resist material in the through-hole portion is removed to form a resist material pattern. Using the resist material pattern as a mask, the protective film PSV1 and the insulating film GI are collectively etched to form the pattern of the protective film PSV1 and the insulating film GI. This process is the same as that used to form the TFT of Example 1. Here, the resist material is usually removed, but in the present invention, the resist material is left as it is and used as the organic protective film PSV2.

  Furthermore, in this embodiment, the protective film PSV1 is made as thin as 0.1 μm, so that the etching time of the protective film PSV1 is prevented from becoming long and the throughput is improved. The protective film PSV1 is for protecting the back channel portion of the thin film transistor element TFT, that is, for stabilizing the threshold voltage Vth of the thin film transistor, and about 0.05 to 0.3 μm is sufficient.

As a result, in Example 1, the organic protective film PSV2, the protective film PSV1, and the insulating film GI were each produced by an individual photolithography process using an individual photomask. Since it can be processed in a lump with a mask, the throughput for manufacturing the TFT substrate is greatly improved as compared with Example 1, and as a result, the mass productivity is greatly improved.
Further, when the organic protective film PSV2 and the insulating film GI are processed at once, or when the organic protective film PSV2 and the protective film PSV1 are processed at once, it can be performed in the same manner as in the present embodiment. included.
Therefore, in this example, in addition to the effect of Example 1, mass productivity is greatly improved.

  This example is the same as Example 1 except for the following.

<< Planar structure of matrix part (pixel part) >>
FIG. 23 is a plan view showing one pixel of the active matrix type color liquid crystal display device of the present embodiment and its periphery.

<< Light shielding film BM >>
In the present embodiment, the stripe-shaped light shielding film BM is formed only in the horizontal direction of the pixel pattern. This eliminates a decrease in aperture ratio due to misalignment between the color filter substrate and the TFT substrate. When the pattern of the light shielding film in the vertical direction of the pixel pattern is shifted in the horizontal direction, the aperture ratio is greatly reduced. In this embodiment, the pattern of the light shielding film in the vertical direction is eliminated, so that the aperture ratio is hardly changed even when this misalignment occurs. This is because the counter electrode CT is completely covered with the video signal line DL, and when viewed from the liquid crystal layer, there is nothing other than the repeated pattern of the pixel electrode and the counter electrode in the horizontal direction of the pixel. It becomes possible.

Therefore, in this embodiment, only the light shielding portion on the TFT and the light leakage portion between the counter electrode and the scanning signal line need only be shielded by the striped light shielding film BM only in the horizontal direction.
Therefore, in this embodiment, in addition to the effects of the first embodiment, the aperture ratio can be greatly improved and the luminance can be improved.

  This example is the same as Example 2 except for the following requirements. FIG. 24 is a plan view of the pixel, and FIG. 25 is a cross-sectional view of the comb electrode portion.

<< Counter electrode CT >>
In the present embodiment, the counter electrode CT includes a protruding portion from the counter electrode signal line CL configured by the conductive film g3 of the same layer as the difference signal line GL, the gate electrode GT, and the counter electrode signal line CL, and the embodiment. 2, there is a portion formed of the conductive film i1 on the protective film PSV2. Also, parts constituted by the conductive film i1 from the counter electrode signal line CL which is constructed in the upper portion and the protective film PSV2 was protruding in the conductive film g3 are electrically connected by opening a through hole, the video signal lines It is configured to envelop.

  Thereby, in the present embodiment, the leakage electric field peculiar to the transverse electric field method can be further reduced as compared with the first and second embodiments, and the crosstalk is eliminated.

  As is apparent from the above description, in the liquid crystal display device of this embodiment, it is possible to suppress the so-called vertical smear, which is an essential problem in the super wide viewing angle liquid crystal display device using the horizontal electric field method. Improvement, reduction in power consumption, reduction in peripheral circuit scale, and improvement in luminance uniformity can be achieved at the same time.

1 is a plan view of a main part showing one pixel of a liquid crystal display unit and its periphery in an active matrix type color liquid crystal display device of Example 1 of the present invention. FIG. 6 is a cross-sectional view of a pixel taken along line 6-6 in FIG. It is sectional drawing of the thin-film transistor element TFT in the 7-7 cutting line of FIG. FIG. 8 is a cross-sectional view of the storage capacitor Cstg taken along the line 8-8 in FIG. 1. 4 is a plan view for explaining a configuration of a matrix peripheral portion of the display panel. FIG. It is sectional drawing which shows the panel edge part which does not have a scanning signal terminal on the left side, and an external connection terminal on the right side. It is the figure of the plane and cross section which show the connection part vicinity of the gate terminal GTM and the gate wiring GL. It is the figure of the plane and cross section which show the connection part vicinity of the drain terminal DTM and video signal line DL. It is the figure of the plane and cross section which show the connection part vicinity of common electrode terminal CTM1, common bus line CB1, and common voltage signal line CL. It is the figure of the plane and cross section which show the connection part vicinity of the common electrode terminal CTM2, the common bus line CB2, and the common voltage signal line CL. 1 is a circuit diagram including a matrix portion and its periphery of an active matrix color liquid crystal display device of the present invention. FIG. It is a figure which shows the drive waveform of Example 1 of the active matrix type color liquid crystal display device of this invention. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process AC of the board | substrate SUB1 side. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process D-E by the side of the board | substrate SUB1. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process FG by the side of the board | substrate SUB1. It is a top view which shows the state which mounted the peripheral drive circuit on the liquid crystal display panel. It is a figure which shows the cross-section of tape carrier package TCP in which the integrated circuit chip CHI which comprises a drive circuit was mounted in the flexible wiring board. It is principal part sectional drawing which shows the state which connected the tape carrier package TCP to the scanning signal circuit terminal GTM of liquid crystal display panel PNL. It is a disassembled perspective view of a liquid crystal display module. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 2 of this invention, and its periphery. It is sectional drawing of the comb-tooth electrode part of the active matrix type color liquid crystal display device of Example 2 of this invention. It is sectional drawing of the comb-tooth electrode part of the active matrix type color liquid crystal display device of Example 3 of this invention. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 4 of this invention, and its periphery. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 5 of this invention, and its periphery. It is sectional drawing of the comb-tooth electrode part of the active matrix type color liquid crystal display device of Example 5 of this invention.

Explanation of symbols

PSV1 ... Protective film

Claims (4)

A pair of substrates; and a liquid crystal composition layer sandwiched between the pair of substrates, wherein one of the pair of substrates includes a video signal line, a scanning signal line, a counter electrode signal line, a thin film transistor , In an active matrix liquid crystal display device having a pixel electrode connected to a thin film transistor and a counter electrode connected to the counter electrode signal line ,
The counter electrode includes a first counter electrode formed in the same layer as the counter electrode signal line, and a second counter electrode formed in a different layer through a protective film of the counter electrode signal line and the thin film transistor. Have
The first counter electrode is formed along the video signal line on both sides of the video signal line,
The second counter electrode is formed at a position overlapping the video signal line,
The liquid crystal display device, wherein the second counter electrode is electrically connected to the first counter electrode through a through hole formed in the protective film . The liquid crystal display device according to claim 1 , wherein the second counter electrode and the counter electrode signal line are electrically connected via a through hole . The cross section of the second counter electrode has a plane parallel to the substrate on which the video signal lines are formed and a plane inclined with respect to the substrate on which the video signal lines are formed. Item 2. A liquid crystal display device according to item 1 . The liquid crystal display device according to claim 1 , wherein the protective film is an organic film.

Images