JP2005189877A - Lateral electric field-type liquid crystal display device suitable for improving aperture ratio - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a bright and low power-consumption lateral electric field-type active matrix liquid crystal display device. <P>SOLUTION: A pixel is arranged in an intersection area of a scanning signal line GL, a counter voltage signal line CL and two adjacent image signal lines DL. Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX and a counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL are extended in the left and right directions in the figure and a plurality of them are disposed in the vertical direction. The image signal lines DL are extended in the vertical direction and a plurality of them are disposed in the left and right directions. The pixel electrode PX is connected to the thin film transistor TFT via a source electrode SD1 and the counter electrode CT and the counter voltage signal line CL are integrated with each other. Two pixels adjacent to each other in the vertical direction along the image signal line DL are configured in such a way that, when the substrate is folded at a line A in the figure, their plane structures are superimposed on each other. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an active matrix liquid crystal display device, and more particularly to a horizontal electric field liquid crystal display device having wide viewing angle characteristics suitable for improving an aperture ratio.

  Active matrix liquid crystal display devices using active elements typified by thin film transistors (TFTs) are becoming widespread as display terminals for OA devices and the like because of their thin and lightweight characteristics and high image quality comparable to that of a cathode ray tube. The display methods of this liquid crystal display device are roughly classified into the following two types.

  One is a method in which a liquid crystal is squeezed by two substrates on which transparent electrodes are formed, operated with a voltage applied to the transparent electrode, and light transmitted through the transparent electrode and incident on the liquid crystal is modulated and displayed. All currently popular products adopt this method.

The other is a method in which the liquid crystal is operated by an electric field substantially parallel to the substrate surface between two electrodes formed on the same substrate, and the light incident on the liquid crystal from the gap between the two electrodes is modulated and displayed. It has a feature that the viewing angle is remarkably wide, and it is called a lateral electric field method or an in-plane switching method as a promising technique for an active matrix liquid crystal display device. The features of the latter method are described in Patent Document 1, Patent Document 2, and Patent Document 3.
Japanese Patent Application Publication No. 5-505247 Japanese Examined Patent Publication No. 63-21907 JP-A-6-160878 Richard A. Soref (Richard A Solef), Proceedings of the IEEE (Proceeding of the Eye Triple E), December issue 1974, pp. 1710-1711 Mitsuji Okano and Keisuke Kobayashi, Liquid Crystals and Fundamentals, p216-220 (Baifukan, 1985)

  However, in the latter conventional method, since the opaque metal electrode is formed in a comb-teeth shape, the ratio of the opening area that transmits light (aperture ratio) is extremely low, and the active matrix type liquid crystal display of the latter conventional method. The apparatus has a problem that the power consumption of the apparatus increases because the display screen is dark or a bright backlight with high power consumption must be used to brighten the display screen.

  Another problem is that the latter conventional method uses a metal electrode, so that the reflectance at the electrode is high, and the face is reflected on the screen due to the reflection at the electrode, making it difficult to see.

  SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to provide an active matrix liquid crystal display device using the latter display method capable of realizing a viewing angle similar to that of a cathode ray tube. It is an object of the present invention to provide an active matrix liquid crystal display device that is easy to see with low power and low power.

  In order to achieve the above object, according to the present invention, as a first configuration, at least one of the pixel electrode and the counter electrode is a transparent electrode, and is in a normally black mode in which dark display is performed when no electric field is applied. The initial alignment state of the twistable liquid crystal layer is a homogeneous alignment state, and the liquid crystal molecules between the electrodes and on the electrodes when an electric field is applied rotate predominantly parallel to the substrate surface, and the light transmission of the liquid crystal display panel The maximum value of the ratio is 4.0% or more, and the viewing angle range with a contrast ratio of 10 to 1 or more is within the range of all directions inclined by 40 degrees or more from the vertical direction with respect to the display surface. .

As a second configuration, at least one of the pixel electrode or the counter electrode is a transparent electrode, is in a normally black mode in which dark display is performed when no electric field is applied, and the initial alignment state of the twistable liquid crystal layer when no electric field is applied Is a homogeneous alignment state, and the twist elastic constant is 10 × 10 ⁻¹² N (Newton) or less.

  As a third configuration, at least one of the pixel electrode or the counter electrode is a transparent electrode, is in a normally black mode in which dark display is performed when no electric field is applied, and the initial alignment state of the twistable liquid crystal layer when no electric field is applied Is a homogeneous alignment state, the initial pretilt angle of the liquid crystal molecules at the upper and lower interfaces of the liquid crystal layer is 10 degrees or less, and the initial tilt state of the liquid crystal molecules in the liquid crystal layer is a splay state.

  As a fourth configuration, at least one of the pixel electrode or the counter electrode is a transparent electrode, is in a normally black mode in which dark display is performed when no electric field is applied, and the initial alignment state of the twistable liquid crystal layer when no electric field is applied Is in a homogeneous alignment state, and the average tilt angle of the liquid crystal molecules in the liquid crystal layer on the transparent electrode is less than 45 degrees even when an electric field is applied.

  As a fifth configuration, in any of the first to fourth configurations, at least a double structure of a transparent electrode and an opaque metal electrode is used for the pixel electrode or the counter electrode.

  As a sixth configuration, in any of the first to fourth configurations, a structure in which adjacent counter voltage signal lines are connected to each other by a counter electrode in a pixel through a through hole is used.

  As a seventh configuration, in any one of the first to fourth configurations, a protective film that covers the active matrix element is further provided, and at least one of the pixel electrode or the counter electrode is formed on the protective film. It is formed and electrically connected to an active matrix element or a counter voltage signal line through a through hole formed in the protective film.

  As an eighth configuration, in any one of the first to fourth configurations, a structure in which the counter electrode is made of a transparent electrode and further has a light shielding pattern between the counter electrode and the video signal line is used.

  As a ninth configuration, in any of the first, second, third, fourth, and fifth configurations, the counter voltage signal line that electrically connects the counter electrodes is a metal.

  As a tenth configuration, in any of the first to fourth configurations, three or more counter electrodes are formed, and two of the counter electrodes are formed adjacent to the video signal line, The counter electrode formed adjacently is opaque.

  As an eleventh configuration, in any of the first to fourth configurations, the transparent conductive film used for the transparent electrode is indium-tin-oxide (ITO).

  As a twelfth configuration, in the ninth configuration, the counter voltage signal line is Cr, Ta, Ti, Mo, W, Al, or an alloy thereof, or a clad structure in which they are laminated.

  As a thirteenth configuration, in the ninth configuration, the counter voltage signal line is formed by laminating a transparent conductive film such as indium-tin-oxide (ITO) on Cr, Ta, Ti, Mo, W, Al or an alloy thereof. This is a clad structure.

  As a fourteenth configuration, in any one of the first to fourth configurations, if the initial twist angle of the liquid crystal layer is substantially zero and the initial alignment angle is a positive dielectric anisotropy Δε of the liquid crystal material, If it is 45 degrees or more and less than 90 degrees and the dielectric anisotropy Δε is negative, it is more than 0 degree and 45 degrees or less.

  As a first manufacturing method, at least one of the scanning signal line terminal portion, the video signal line terminal portion, or the uppermost conductive layer of the counter electrode terminal portion and at least one of the pixel electrode and the counter electrode is formed of a transparent conductive layer. It is characterized in that it is formed in the same process.

  The effect | action of this invention is shown below.

First, as an operation of the first configuration, since at least one of the pixel electrode and the counter electrode is made transparent, the maximum transmittance at the time of performing bright (white) display is improved by the transmitted light of the portion. Display can be brighter than when it is opaque, and the light transmittance of the liquid crystal display panel is 3.0 to 3.8% in the case of employing the latter opaque electrode of the conventional method. A transmittance value of 4.0% or more can be achieved. That is, when the luminance of the backlight incident light is 3000 cd / m ² , the maximum luminance value of the bright display luminance can be 120 cd / m ² or more.

  Furthermore, when no voltage is applied, since the liquid crystal molecules maintain the initial homogeneous alignment state, the arrangement of the polarizing plate is configured so as to display dark (black) in that state (to make a normally black mode), Even if the electrode is transparent, the light of that portion is not transmitted, so that a good dark display can be performed and the contrast is improved.

  On the other hand, in the normally white mode, a dark display must be performed when a voltage is applied, and the light on the electrode cannot completely block light when a voltage is applied. High quality dark display is not possible. Therefore, a sufficient contrast ratio cannot be achieved.

  Further, since the liquid crystal molecules between and on the electrodes when an electric field is applied rotate predominantly parallel to the substrate surface, a wide viewing angle characteristic can be obtained.

  Therefore, a viewing angle range with a contrast ratio of 10 to 1 or more is obtained in an omnidirectional range tilted by 40 degrees or more from the vertical direction with respect to the display surface and a wide viewing angle characteristic.

As a function of the second configuration, when a voltage is applied between the pixel electrode and the counter electrode, the twist elastic constant of the twistable liquid crystal layer is 10 × 10 ⁻¹² N (Newton) or less. On the film electrodes, the angle α rotating from the initial alignment direction increases, and the transmittance on the electrodes acts in a complementary manner to the transmittance between the electrodes, substantially improving the aperture ratio. The twist elastic constant K2 is preferably smaller.

  In addition, as an effect of the third configuration, since the initial pretilt angle of the liquid crystal molecules at the upper and lower interfaces of the liquid crystal layer is 10 degrees or less and the initial tilt state of the liquid crystal molecules in the liquid crystal layer is the splay state, The tilt angle of the liquid crystal molecules is almost zero, and the average tilt angle of the liquid crystal layer that contributes to the display can be lowered. Therefore, even when a voltage is applied, the tilt angle of the liquid crystal molecules between the electrodes and on the transparent electrode can be set low. Improve rate and wide viewing angle.

  Further, as an effect of the fourth configuration, since the average tilt angle of the liquid crystal molecules in the liquid crystal layer on the transparent electrode is less than 45 degrees even when an electric field is applied, an improvement in aperture ratio and a wide viewing angle can be realized.

  Further, as a function of the fifth configuration, by using a double structure of a transparent electrode and an opaque metal electrode for the pixel electrode or the counter electrode, a disconnection failure of this electrode can be largely prevented, which is advantageous for increasing the screen.

  Further, as an effect of the sixth configuration, by using a structure in which adjacent counter voltage signal lines are connected through a through hole by a counter electrode in a pixel, each counter voltage signal line is electrically connected in a mesh shape. Therefore, the resistance of the counter voltage signal line can be reduced, and even if a disconnection failure occurs, it does not become a serious defect.

  Furthermore, as an effect of the seventh configuration, the electric field acting on the liquid crystal molecules is suppressed from being reduced by the protective film, and the driving voltage can be reduced.

  Furthermore, as an action of the eighth configuration, the aperture ratio is improved by using a structure in which the counter electrode is made of a transparent electrode and has a light shielding pattern between the counter electrode and the video signal line.

  Further, as a function of the ninth configuration, by reducing the resistance of the counter voltage signal line, it is possible to smoothly transmit the voltage between the counter electrodes, and it is possible to suppress horizontal crosstalk by reducing voltage distortion. .

  Further, as an effect of the tenth configuration, crosstalk accompanying the video signal is suppressed by making the counter electrode adjacent to the video signal line opaque. The reason is shown below.

  By forming the transparent counter electrode adjacent to the video signal line, the electric field (electric force line) from the video signal line is absorbed by the counter electrode, and the electric field from the video signal line is between the pixel electrode and the counter electrode. Since the electric field is not affected, the occurrence of crosstalk accompanying the video signal, particularly the crosstalk in the vertical direction of the substrate, is remarkably suppressed. However, the behavior of the liquid crystal molecules on the counter electrode adjacent to the video signal line is unstable due to fluctuations in the video signal. When the counter electrode adjacent to the video signal line is made transparent, the transmitted light of the electrode part Crosstalk is observed. Therefore, by making the counter electrode adjacent to the video signal line opaque, crosstalk associated with the video signal can be suppressed.

  Furthermore, as an action of the eleventh configuration, the transparent conductive film is indium-tin-oxide (ITO), which is suitable for improving the transmittance.

  Furthermore, as an effect of the twelfth and thirteenth configurations, since the counter voltage signal line has a laminated clad structure, the resistance value is reduced, and disconnection failure can be reduced.

  Further, as an effect of the fourteenth configuration, if the initial twist angle of the liquid crystal layer is substantially zero and the initial alignment angle is 45 ° C. or higher and lower than 90 ° C. if the dielectric anisotropy Δε of the liquid crystal material is positive, the dielectric constant If the anisotropy Δε is negative, it is greater than 0 ° and less than or equal to 45 °. Therefore, the suppression of the domain and the range of the maximum applied voltage can be optimized to improve the contrast, and the response speed can be optimized.

  Further, as an effect of the first manufacturing method, the transparent conductive layer as the uppermost layer of the scanning signal line terminal portion, the video signal line terminal portion, or the counter electrode terminal portion and the transparent conductive film of the pixel electrode or the counter electrode are formed simultaneously. Thus, the pixel electrode and the counter electrode can be formed of a transparent conductive film without increasing the number of steps.

  In the liquid crystal display device of the present invention, at least one of the pixel electrode and the counter electrode is formed of a transparent conductive film. For example, the configuration of the liquid crystal display element described in Non-Patent Document 1 is as follows. It is different in point.

  In Non-Patent Document 1, comb electrodes corresponding to the pixel electrode and the counter electrode are formed of a transparent conductive film.

  However, when forming the initial alignment state of liquid crystal molecules, SiO (silicon monooxide) is obliquely deposited at about 85 degrees, and a fairly high pretilt angle is intentionally formed in the liquid crystal molecules at the interface between each electrode and the liquid crystal layer. I am letting. For this reason, FIG. As shown in FIG. 1 (b), by applying a voltage between the comb-shaped electrodes from the homogeneous alignment twisted 90 degrees in the initial alignment state, a realignment state is established, and the homogeneous alignment state between the electrodes is substantially parallel to the substrate surface. Then, a homeotropic alignment state perpendicular to the substrate surface is formed on the electrode.

  However, in this configuration, as the electric field is increased, the realignment states of the two types of liquid crystal molecules act complementarily and a brighter display is possible, but it is necessary to increase the tilt angle of the liquid crystal molecules on the average. Therefore, there is a drawback that the viewing angle characteristic becomes narrow.

  On the other hand, in the horizontal electric field type liquid crystal display device of the present invention, in order to obtain a wide viewing angle characteristic and a good aperture ratio, the liquid crystal that contributes to the display image even when a voltage is applied between the pixel electrode and the counter electrode. The reorientation part of the molecule keeps the homogeneous orientation state parallel to the substrate surface as much as possible, and on the transparent conductive film electrode, the transmittance on the electrode corresponds to the angle α rotating from the initial orientation direction, A structure that works complementarily with the transmittance between the electrodes to substantially improve the aperture ratio.

  In the present specification, the homogeneous alignment state is a state in which the liquid crystal molecules in the liquid crystal layer have a tilt (rise) angle parallel to the substrate surface or the interface of the liquid crystal layer as much as possible. The alignment state is such that the tilt angle from the surface or the interface of the liquid crystal layer is less than 45 degrees. Therefore, the homeotropic alignment state means a case where the tilt angle from the substrate surface or the interface of the liquid crystal layer exceeds 45 degrees.

  41A (FIG. 41A, the same applies hereinafter) shows an example of the potential distribution in the liquid crystal layer in an electrode configuration that generates an electric field in a direction substantially parallel to the substrate surface.

  A solid line in the figure is an equipotential line, and an electric field vector is given in a direction perpendicular to the equipotential line. The electric field vector E generates only a component Ey in the direction perpendicular to the substrate surface on the center of the electrode, but also generates a component Ex in the horizontal direction on the substrate surface except for the central portion. In the region where the horizontal component, that is, the horizontal electric field component Ex is generated, the liquid crystal molecules between the electrodes rotate by the rotation angle α from the initial alignment direction RDR in the horizontal electric field Ex direction, as shown in FIGS. 41B and 41C.

  On the other hand, the liquid crystal molecules on the electrodes are rotated by the rotation of the liquid crystal molecules between the electrodes due to the elastic field in the liquid crystal. Therefore, although the transverse electric field is not applied to the central liquid crystal molecule on the electrode, the liquid crystal molecule rotates in the same direction as the surrounding liquid crystal molecules due to the elastic field. That is, the rotation angle α is large between the electrodes, decreases on the electrodes, and becomes the minimum on the center portion of the electrodes.

  The result of simulating this situation is shown in FIGS.

  In the simulation of this example, the initial homogeneous orientation state of the liquid crystal molecules is such that the initial twist angle of the liquid crystal layer is almost zero, the initial orientation angle φLC = 75 degrees formed by the initial orientation direction RDR and the applied electric field Ex, and the liquid crystal layer The initial pretilt angle of liquid crystal molecules in the vicinity of the upper and lower interfaces of the polarizing plate is set to zero degree, and further, a crossed Nicol arrangement in which one transmission axis of the polarizing plate coincides with the initial alignment direction RDR and the transmission axis of the other polarizing plate is orthogonal to each other. In the configuration example, the display is performed in the birefringence mode.

The light transmittance T / T ₀ at this time is expressed by the following equation.

T / T ₀ = sin ² (2αeff) · sin ² (πdeff · Δn / λ) (1)
Here, αeff is an angle formed by the effective optical axis of the liquid crystal layer and the polarization transmission axis. In this example, αeff is an effective value of the rotation angle α of the liquid crystal molecules in the thickness direction of the liquid crystal layer. It is an apparent value that can be treated as an average value when assumed.

  Further, deff is the effective thickness of the liquid crystal layer having birefringence, Δn is the refractive index anisotropy, and λ is the wavelength of light.

  In the equation (1), when the applied electric field Ex is set, the value of αeff increases according to the intensity, and becomes maximum when the electric field is 45 degrees.

  Furthermore, in the simulation of this example, the retardation Δn · deff of the liquid crystal layer is selected to be half of the wavelength λ of the light to realize the birefringence zero-order mode, and the dielectric anisotropy Δε is set to be positive. .

  FIG. 42A is a characteristic diagram showing the state of equipotential lines when a voltage that gives a bright display near the maximum is applied to a transparent ITO electrode. The vertical axis indicates the thickness of the liquid crystal layer (thickness: 4.0 μm), The relative positional relationship of the electrodes is shown on the axis. In addition, the numerical value in a figure shows the normalized electric potential strength.

  42B and 42C show the rotation angle α and tilt (rise) angle of the liquid crystal molecules in the liquid crystal layer when the lateral electric field component Ex formed from the equipotential line state is applied.

  As shown in FIG. 42C, even when a voltage is applied, the liquid crystal molecules on the electrode hardly rise, and in this example, the tilt angle is 8 ° or less in all the thickness directions of the liquid crystal layer. Further, as shown in FIG. In addition, the liquid crystal molecules on the electrode are also rotated about 15 to 35 ° near the center of the liquid crystal layer.

  For convenience, the sign of the tilt angle shown in FIG. 42C is positive for rising right and negative for rising left in the drawing. Therefore, according to the method of the present invention, the rotation angle α of the liquid crystal molecules can be changed on the electrode to change the transmittance.

  The most related to this operation is the twist elastic constant K2 of the liquid crystal, and the twist elastic constant K2 is preferably as small as possible. The smaller the twist elastic constant K2, the more the liquid crystal molecules on the electrodes are affected by the liquid crystal molecules between the electrodes. It rotates so as to approach the rotation angle α of the liquid crystal molecules in between.

FIG. 41D schematically shows the transmittance distribution on and between the electrodes when the twist elastic constant K2 is about 10 × 10 ⁻¹² N (Newton).

  When the electrode is transparent, the re-orientation operation of the liquid crystal molecules on the electrode described above causes 5 to 30% of the average transmittance of the A portion between the electrodes to be the transmittance of the B portion on the electrode. Average transmittance is obtained.

As will be described later, when the twist elastic constant K2 is set to 2.0 × 10 ⁻¹² N (Newton) or less, 50% or more of the average transmittance of the transmittance of the A portion between the electrodes is increased on the electrodes. It turned out that it becomes the average value transmittance | permeability of the transmittance | permeability of B part. Therefore, the average transmittance of the entire portion becomes the average transmittance of the transmittance of the A + B portion, and is raised.

  In other words, the aperture ratio per pixel can be substantially improved as compared with a conventional metal layer that does not transmit light.

  In the simulation of this example, the calculation is performed with the initial pretilt angle set to zero degree. However, in actuality, the initial pretilt angle near the interface of the liquid crystal layer with the alignment film is about 10 degrees or less, preferably 6 degrees or less. It is necessary to set in. In the embodiment described later, it is set to about 5 degrees.

  By setting the initial pretilt angle in such a range, the liquid crystal molecules at the liquid crystal layer interface can be regulated in the in-plane direction of the substrate, and the average tilt angle of the liquid crystal layer on the electrode is less than 45 degrees even when an electric field is applied. Can be maintained. That is, even when an electric field is applied, the liquid crystal on the electrode can be prevented from becoming so-called homeotropic alignment.

  FIG. 44 is an example of a characteristic diagram of a simulation result showing a tilt angle of liquid crystal molecules in a liquid crystal layer and a viewing angle range in which the contrast ratio is 10 or more in all directions in a horizontal electric field type liquid crystal display device.

  That is, if the tilt angle is about 30 degrees, the contrast ratio becomes 10 or more in all directions within the viewing angle range tilted by about 40 degrees from the vertical direction with respect to the display surface. The same characteristics as the display device can be obtained. Further, as the tilt angle is reduced, the viewing angle range is expanded. If the tilt angle is about 10 degrees, the viewing angle range is tilted to about 80 degrees. Is obtained.

  In this embodiment, in order to always reduce the average tilt angle of the liquid crystal molecules between the electrodes when no electric field is applied and when an electric field is applied and in the liquid crystal layer on the transparent electrode, the rubbing direction of the alignment films ORI1 and ORI2 described later is 2 The initial alignment state is set so that the initial pretilt angle of the liquid crystal molecules at the interface between the liquid crystal layers on the side of the substrates SUB1 and SUB2 is in the splay state, and the liquid crystal molecules near the center of the liquid crystal layer are as parallel as possible to the interface. Like that.

  The present invention, other objects of the present invention, and other features of the present invention will be apparent from the following description with reference to the drawings.

<Active matrix liquid crystal display device>
Hereinafter, embodiments in which the present invention is applied to an active matrix color liquid crystal display device will be described. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
<< Planar structure of matrix part (pixel part) >>
FIG. 1 is a plan view showing one pixel of an active matrix color liquid crystal display device of the present invention and its periphery. (The hatched portion in the figure indicates the transparent conductive film g2.)
As shown in FIG. 1, each pixel includes a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode line) CL, and two adjacent video signal lines (drain signal line or line). The vertical signal line (DL) is arranged in a region intersecting with DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL and counter-voltage signal lines CL are arranged in the up-down direction. The video signal lines DL extend in the vertical direction, and a plurality of video signal lines DL are arranged in the horizontal direction. The pixel electrode PX is connected to the thin film transistor TFT via the source electrode SD1, and the counter electrode CT is integrated with the counter voltage signal line CL.

  Two pixels that are vertically adjacent to each other along the video signal line DL have a configuration in which the planar configurations overlap when bent along the A line in FIG. This is to reduce the resistance of the counter voltage signal line CL by making the counter voltage signal line CL common to two pixels vertically adjacent along the video signal line DL and expanding the electrode width of the counter voltage signal line CL. Because. Accordingly, it becomes easy to sufficiently supply the counter voltage from the external circuit to the counter electrode CT of each pixel in the left-right direction.

  The pixel electrode PX and the counter electrode CT face each other, and the optical state of the liquid crystal LC is controlled by the electric field between each pixel electrode PX and the counter electrode CT, thereby controlling display. The pixel electrode PX and the counter electrode CT are formed in a comb-teeth shape, and are each an elongated electrode in the vertical direction of the figure.

  The number O (number of comb teeth) of the counter electrode CT in one pixel is configured to have a relation of the number of pixel electrodes PX (number of comb teeth) P and O = P + 1 (in this embodiment, O). = 3, P = 2). This is because the counter electrodes CT and the pixel electrodes PX are alternately arranged, and the counter electrodes CT are necessarily adjacent to the video signal lines DL. Thus, the electric field lines from the video signal line DL can be shielded by the counter electrode CT so that the electric field between the counter electrode CT and the pixel electrode PX is not affected by the electric field generated from the video signal line DL. it can. Since the counter electrode CT is always supplied with a potential from the outside by a counter voltage signal line CL, which will be described later, the potential is stable. Therefore, there is almost no fluctuation in potential even when adjacent to the video signal line DL. In addition, since the geometric position of the pixel electrode PX from the video signal line DL becomes far away, the parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the video of the pixel electrode potential Vs. Variations due to signal voltage can also be suppressed. As a result, crosstalk (image quality failure called vertical smear) that occurs in the vertical direction can be suppressed.

  The electrode width of the pixel electrode PX and the counter electrode CT is 6 μm. In order to apply a sufficient electric field to the entire liquid crystal layer with respect to the thickness direction of the liquid crystal layer, the thickness is set to be sufficiently larger than a thickness of 3.9 μm of the liquid crystal layer described later and as much as possible to increase the aperture ratio. Make it thinner. Further, the electrode width of the video signal line DL is set to 8 μm that is slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection. Here, the electrode width of the video signal line DL is set to be not more than twice the electrode width of the adjacent counter electrode CT. Alternatively, when the electrode width of the video signal line DL is determined from the productivity of the yield, the electrode width of the counter electrode CT adjacent to the video signal line DL is set to ½ or more of the electrode width of the video signal line DL. . This is because the electric lines of force generated from the video signal line DL are absorbed by the counter electrodes CT on both sides, and in order to absorb the electric lines of force generated from a certain electrode width, an electrode width equal to or larger than that is used. An electrode with is required. Therefore, the counter electrode CT on both sides only needs to absorb the electric lines of force generated from half of the electrodes of the video signal line DL (4 μm each), so that the electrode width of the counter electrode CT adjacent to the video signal line DL is 1. / 2 or more. This prevents crosstalk, particularly in the vertical direction (vertical crosstalk), due to the influence of the video signal.

  The scanning signal line GL sets the electrode width so as to satisfy a resistance value sufficient to apply a scanning voltage to the gate electrode GT of the pixel on the terminal side (opposite side of a scanning electrode terminal GTM described later). In addition, the counter voltage signal line CL also sets the electrode width so as to satisfy a resistance value sufficient to apply the counter voltage to the counter electrode CT of the pixel on the terminal side (opposite side of the common bus line CB described later).

On the other hand, the electrode interval between the pixel electrode PX and the counter electrode CT varies depending on the liquid crystal material used. This is because the electric field strength that achieves the maximum transmittance differs depending on the liquid crystal material, so the electrode spacing is set according to the liquid crystal material, and the maximum amplitude of the signal voltage set by the withstand voltage of the video signal drive circuit (signal side driver) to be used This is because the maximum transmittance can be obtained within the above range. When a liquid crystal material described later is used, the electrode interval is 16 μm.
<< Cross-sectional structure of matrix part (pixel part) >>
2 is a cross-sectional view taken along the line 3-3 in FIG. 1, FIG. 3 is a cross-sectional view of the thin film transistor TFT taken along the line 4-4 in FIG. 1, and FIG. FIG. As shown in FIGS. 2 to 4, a thin film transistor TFT, a storage capacitor Cstg and an electrode group are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and a color filter FIL on the upper transparent glass substrate SUB2 side. A light blocking black matrix pattern BM is formed.

In addition, alignment films ORI1 and ORI2 for controlling the initial alignment of the liquid crystal are provided on the inner surfaces (liquid crystal LC side) of the transparent glass substrates SUB1 and SUB2, and the outer sides of the transparent glass substrates SUB1 and SUB2. Is provided with a polarizing plate in which the polarization axes are arranged orthogonally (crossed Nicols arrangement).
<< TFT substrate >>
First, the configuration of the lower transparent glass substrate SUB1 side (TFT substrate) will be described in detail.
<< Thin Film Transistor TFT >>
The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases.

As shown in FIG. 3, the thin film transistor TFT includes an i-type semiconductor layer made of a gate electrode GT, a gate insulating film GL, i-type (intrinsic, intrinsic, conductivity type-determining impurity is not doped) amorphous silicon (Si). It has AS, a pair of source electrode SD1, and drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so that the source and drain are interchanged during operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.
<< Gate electrode GT >>
The gate electrode GT is formed continuously with the scanning signal line GL, and a part of the scanning signal line GL is configured to be the gate electrode GT. The gate electrode GT is a portion that exceeds the active region of the thin film transistor TFT, and is formed larger than the i-type semiconductor layer AS (as viewed from below). Thus, in addition to the role of the gate electrode GT, the i-type semiconductor layer AS is devised so that external light and backlight light do not strike. In this example, the gate electrode GT is formed of a single-layer conductive film g1. As the conductive film g1, for example, an aluminum (Al) film formed by sputtering is used, and an Al anodic oxide film AOF is provided thereon.
<< Scanning signal line GL >>
The scanning signal line GL is composed of a conductive film g1. The conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as that of the conductive film g1 of the gate electrode GT and is integrally formed. Through this scanning signal line GL, a gate voltage Vg is supplied from an external circuit to the gate electrode GT. An Al anodic oxide film AOF is also provided on the scanning signal line GL. Note that a portion that intersects with the video signal line DL is thinned to reduce the probability of short circuit with the video signal line DL, and is also bifurcated so that it can be separated by laser trimming even if short-circuited.
<< Counter electrode CT >>
The counter electrode CT is composed of a conductive film g1 in the same layer as the gate electrode GT and the scanning signal line GL. An Al anodic oxide film AOF is also provided on the counter electrode CT. A counter voltage Vcom is applied to the counter electrode CT. In this embodiment, the counter voltage Vcom is a feed generated when the thin film transistor element TFT is turned off from an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL. Although the potential is set lower by the through voltage ΔVs, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal driving circuit to about half, an AC voltage may be applied.
<< Counter voltage signal line CL >>
The counter voltage signal line CL is composed of a conductive film g1. The conductive film g1 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, the scanning signal line GL, and the counter electrode CT, and is configured integrally with the counter electrode CT. The counter voltage signal line CL supplies the counter voltage Vcom from the external circuit to the counter electrode CT. An Al anodic oxide film AOF is also provided on the counter voltage signal line CL. It should be noted that the portion that intersects with the video signal line DL is made thin in order to reduce the probability of short circuit with the video signal line DL in the same manner as the scanning signal line GL, and can be separated by laser trimming even if short-circuited. You are bifurcated.
<Insulating film GI>
The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. For example, a silicon nitride film formed by plasma CVD is selected as the insulating film GI, and is formed to a thickness of 1200 to 2700 mm (in this embodiment, about 2400 mm). The gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM. The insulating film GI also contributes to electrical insulation between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL.
<< i-type semiconductor layer AS >>
The i-type semiconductor layer AS is made of amorphous silicon and has a thickness of 200 to 2200 mm (in this embodiment, a film thickness of about 2000 mm). Layer d0 is an N (+) type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, i-type semiconductor layer AS is present on the lower side, and conductive layer d1 (d2) is present on the upper side. It is left only in place.

The i-type semiconductor layer AS is also provided between both the scanning signal line GL and the intersection (crossover portion) of the counter voltage signal line CL and the video signal line DL. This crossing portion i-type semiconductor layer AS reduces a short circuit between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL at the crossing portion.
<< Source electrode SD1, drain electrode SD2 >>
Each of the source electrode SD1 and the drain electrode SD2 includes a conductive film d1 in contact with the N (+) type semiconductor layer d0 and a conductive film d2 formed thereon.

The conductive film d1 uses a chromium (Cr) film formed by sputtering, and is formed to a thickness of 500 to 1000 mm (in this embodiment, about 600 mm). The Cr film is formed in a range that does not exceed a thickness of about 2000 mm because stress increases as the film thickness increases. The Cr film is used for the purpose of improving the adhesion with the N (+) type semiconductor layer d0 and preventing Al of the conductive film d2 from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). The As the conductive film d1, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr film.

  The conductive film d2 is formed to a thickness of 3000 to 5000 mm (in this embodiment, about 4000 mm) by sputtering of Al. The Al film has less stress than the Cr film and can be formed to have a thick film thickness. The resistance value of the source electrode SD1, the drain electrode SD2 and the video signal line DL can be reduced, and the gate electrode GT or i-type semiconductor can be formed. There is a function to ensure overcoming of the level difference due to the layer AS (to improve step coverage).

After patterning the conductive film d1 and the conductive film d2 with the same mask pattern, the N (+) type semiconductor layer d0 is removed using the same mask or using the conductive film d1 and the conductive film d2 as a mask. That is, the N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS is removed by self-alignment except for the conductive film d1 and the conductive film d2. At this time, since the N (+) type semiconductor layer d0 is etched so that the entire thickness thereof is removed, the surface portion of the i type semiconductor layer AS is also slightly etched, but the degree is controlled by the etching time. do it.
<< Video signal line DL >>
The video signal line DL includes a second conductive film d2 and a third conductive film d3 that are the same layer as the source electrode SD1 and the drain electrode SD2. The video signal line DL is formed integrally with the drain electrode SD2.
<< Pixel electrode PX >>
The pixel electrode PX is formed of a transparent conductive layer g2. This transparent conductive film g2 is made of a transparent conductive film (Indium-Tin-Oxide .. ITO: Nesa film) formed by sputtering, and is formed to a thickness of 100 to 2000 mm (in this embodiment, a film thickness of about 1400 mm). Is done.

Since the pixel electrode becomes transparent as in this embodiment, the maximum transmittance at the time of white display is improved by the transmitted light of the portion, so that a brighter display is performed than when the pixel electrode is opaque. be able to. At this time, as will be described later, when no voltage is applied, the liquid crystal molecules maintain the initial alignment state, and the arrangement of the polarizing plates is configured so as to display black in that state (a normally black mode is set). Therefore, even if the pixel electrode is transparent, light of that portion is not transmitted, and high-quality black can be displayed. Thereby, the maximum transmittance can be improved and a sufficient contrast ratio can be achieved.
<< Storage capacity Cstg >>
The pixel electrode PX is formed so as to overlap the counter voltage signal line CL at the end opposite to the end connected to the thin film transistor TFT. As is apparent from FIG. 4, this superposition constitutes a storage capacitor (capacitance element) Cstg having the pixel electrode PX as one electrode PL2 and the counter voltage signal CL as the other electrode PL1. The dielectric film of the storage capacitor Cstg is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As shown in FIG. 1, in a plan view, the storage capacitor Cstg is formed in a portion where the width of the conductive film g1 of the counter voltage signal line CL is increased.
<< Protective film PSV1 >>
A protective film PSV1 is provided on the thin film transistor TFT. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and a film having high transparency and good moisture resistance is used. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and is formed with a film thickness of about 1 μm.

The protective film PSV1 is formed so as to surround the entire matrix part AR, and the peripheral part is removed so as to expose the external connection terminals DTM and GTM. Regarding the thickness relationship between the protective film PSV1 and the gate insulating film GI, the former is increased in consideration of the protective effect, and the latter is decreased in the mutual conductance gm of the transistor. Therefore, the protective film PSV1 having a high protective effect is formed larger than the gate insulating film GI so as to protect the peripheral portion over as wide a range as possible.
<Color filter substrate>
Next, returning to FIGS. 1 and 2, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.
<< Light shielding film BM >>
A light shielding film is provided on the upper transparent glass substrate SUB2 side so that transmitted light from an unnecessary gap (gap other than between the pixel electrode PX and the counter electrode CT) is emitted to the display surface side and the contrast ratio or the like is not lowered. A BM (so-called black matrix) is formed. The light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched by the upper and lower light shielding films BM and the large gate electrode GT, and is not exposed to external natural light or backlight light.

  A closed polygonal outline of the light shielding film BM shown in FIG. 1 indicates an opening inside which the light shielding film BM is not formed. This contour line pattern is an example, and when the opening is made larger, the dotted light shielding film BM1 in FIG. 1 may be used. In the enlarged region in FIG. 1, the electric field direction is disturbed, but the display of the portion corresponds to the video information in the pixel on a one-to-one basis, and in the case of black, the display is black, and in the case of white, the display is white. Therefore, it can be used as a part of the display. In addition, the vertical boundary line in the figure is determined by the alignment accuracy of the upper and lower substrates, and is set between the widths of the counter electrodes when the alignment accuracy is better than the electrode width of the counter electrode CT adjacent to the video signal line DL. Thus, the opening can be further enlarged.

  The light shielding film BM has a light shielding property and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT. Is mixed with a resist material to form a thickness of about 1.2 μm.

  The light shielding film BM is formed in a grid around each pixel, and an effective display area of one pixel is partitioned by this grid. Therefore, the contour of each pixel is clearly defined by the light shielding film BM. That is, the light shielding film BM has two functions of black matrix and light shielding for the i-type semiconductor layer AS.

The light shielding film BM is also formed in a frame shape in the peripheral portion, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. The light shielding film BM at the peripheral portion extends outside the seal portion SL, and prevents leakage light such as reflected light caused by a mounting machine such as a personal computer from entering the matrix portion. On the other hand, the light-shielding film BM is retained about 0.3 to 1.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cutting region of the substrate SUB2.
<Color filter FIL>
The color filter FIL is formed in stripes by repeating red, green, and blue at positions facing the pixels. The color filter FIL is formed so as to overlap the edge portion of the light shielding film BM.

The color filter FIL can be formed as follows. First, a dyeing base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. Thereafter, the dyeing substrate is dyed with a red dye, and a fixing process is performed to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing the same process.
<< Overcoat film OC >>
The overcoat film OC is provided for preventing leakage of the dye of the color filter FIL to the liquid crystal LC, and for flattening a step by the color filter FIL and the light shielding film BM. The overcoat film OC is formed of a transparent resin material such as an acrylic resin or an epoxy resin.
<Liquid crystal layer and deflection plate>
Next, a liquid crystal layer, an alignment film, a polarizing plate, etc. are demonstrated.
<Liquid crystal layer>
As the liquid crystal material LC, nematic liquid crystal having a positive dielectric anisotropy Δε, a value of 13.2, and a refractive index anisotropy Δn of 0.081 (589 nm, 20 ° C.) is used. The thickness (gap) of the liquid crystal layer is 3.9 μm, and the retardation Δn · d is 0.316. With this retardation Δn · d value, the maximum transmittance can be obtained when the liquid crystal molecules are rotated 45 ° from the rubbing direction to the electric field direction in combination with an alignment film and a polarizing plate, which will be described later. Transmitted light with almost no property can be obtained. The thickness (gap) of the liquid crystal layer is controlled by polymer beads.

  The liquid crystal material LC is not particularly limited, and the dielectric anisotropy Δε may be negative. Further, as the dielectric anisotropy Δε is larger, the driving voltage can be reduced. Further, when the refractive index anisotropy Δn is small, the thickness (gap) of the liquid crystal layer can be increased, the liquid crystal sealing time can be shortened, and the gap variation can be reduced.

  Further, when the relationship between the material properties of the liquid crystal material and the transmitted light intensity at the counter electrode portion or the pixel electrode portion of the transparent conductive film was examined, it was found that it greatly depends on the twist elastic constant K2 of the liquid crystal material. This is because the in-plane twist deformation due to the transverse electric field that causes light transmission in the opening between the electrodes is attenuated at the upper part of the electrode of the transparent conductive film with a specific curvature corresponding to the twist elastic constant K2 of the liquid crystal material. It is. Therefore, in order to increase the light transmission in the electrode portion of the transparent conductive film and improve the brightness of the entire opening including the electrode of the transparent conductive film, a liquid crystal material having a small twist elastic constant K2 is used. What is necessary is just to make said attenuation curvature small. The effect of the twist elastic constant K2 will be further described in Example 11.

In Example 1, 5.1 × 1O ^-12 N (Newton) is used as the twist elastic constant K2 at room temperature.

In addition, the measuring method of the twist elastic constant K2 is described in Non-Patent Document 2, for example, and can be obtained from the threshold voltage measurement of the twisted liquid crystal cell.
《Alignment film》
As the alignment film ORI, polyimide is used. The rubbing directions are parallel to each other between the upper and lower substrates, and the initial alignment angle φLC formed by the initial alignment direction RDR and the applied electric field direction EDR (Ex) is 75 °. FIG. 19 shows the relationship.

  The initial alignment angle φLC formed by the initial alignment direction RDR and the applied electric field direction EDR is 45 ° C. or more and less than 90 ° C. and the dielectric anisotropy Δε is negative if the dielectric anisotropy Δε of the liquid crystal material is positive. If it is, it must be over 00 and 45 degrees or less.

  Furthermore, in this embodiment, the rubbing directions are parallel to each other by the alignment films ORI1 and ORI2, so that the initial pretilt angles of the liquid crystal molecules at the upper and lower interfaces of the liquid crystal layer that contribute to the display between the electrodes and on the electrodes are in the splay state. The liquid crystal molecules have the effect of compensating the optical characteristics of each other, and a wide viewing angle characteristic can be obtained.

Further, by making the rubbing directions antiparallel to each other by the alignment films ORI1 and ORI2, the pretilt angles of the liquid crystal molecules at the upper and lower interfaces of the liquid crystal layer are in a parallel state, and the tilt angle in the average liquid crystal layer is further increased. By setting the pretilt angle to a degree or less, the same effect of the present invention can be obtained.
"Polarizer"
As the polarizing plate POL, G1220DU manufactured by Nitto Denko Corporation is used, the polarizing transmission axis MAX1 of the lower polarizing plate POL1 is made to coincide with the rubbing direction RDR, and the polarizing transmission axis MAX2 of the upper deflecting plate POL2 is made orthogonal thereto. FIG. 19 shows the relationship. As a result, a normally closed characteristic in which the transmittance increases as the voltage applied to the pixel of the present invention (the voltage between the pixel electrode PX and the counter electrode CT) increases can be obtained. When it is added, a good quality black display can be achieved.

In addition, a transparent conductive film is formed over the entire surface of the polarizing plate POL2 for the purpose of reducing the specific resistance value in order to prevent the influence of external static electricity. This transparent conductive film may be formed between the upper substrate SUB2 and the upper polarizing plate POL2.
<Configuration around the matrix>
FIG. 5 is a view showing a principal plane around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2. FIG. 6 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

  In the manufacture of this panel, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for improving throughput, standardized any breed for shared manufacturing facilities if large size After processing the glass substrate of the size, the glass substrate is reduced to a size suitable for each type, and in any case, the glass is cut after going through a single process. FIG. 5 and FIG. 6 show the latter example. Both of FIG. 5 and FIG. 6 show the upper and lower substrates SUB1 and SUB2 after cutting, and LN indicates the edge before cutting of both substrates. In any case, the size of the upper substrate SUB2 is lower so that the external connection terminal groups Tg, Td and the terminal COT (subscript omitted) are present in the completed state (the upper side and the left side in the drawing) are exposed. It is limited to the inner side than the substrate SUB1. The terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, which will be described later, and a lead carrier portion of a tape carrier package TCP (FIGS. 16 and 17) on which an integrated circuit chip CHI is mounted. Multiple units are named collectively. The lead-out wiring from the matrix portion of each group to the external connection terminal portion is inclined as it approaches both ends. This is because the terminals DTM and GTM of the display panel PNL are matched with the arrangement pitch of the package TCP and the connection terminal pitch in each package TCP. The counter electrode terminal CTM is a terminal for applying a counter voltage to the counter electrode CT from an external circuit. The counter voltage signal line CL of the matrix portion is drawn to the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the counter voltage signal lines are grouped together by a common bus line CB and connected to the counter electrode terminal CTM. .

  A seal pattern SL is formed between the transparent glass substrates SUB1 and LSUB2 so as to seal the liquid crystal LC along the edge except for the liquid crystal sealing inlet INJ. The sealing material is made of, for example, an epoxy resin.

  The layers of the alignment films ORI1 and ORI2 are formed inside the seal pattern SL. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively. The liquid crystal LC is sealed in a region partitioned by a seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 that set the direction of liquid crystal molecules. The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2 side, so that the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are formed. And the liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with an epoxy resin or the like, and the upper and lower substrates are cut.
<Gate terminal section>
FIG. 7A is a plan view showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, and FIG. 7B shows a cross section taken along the line BB of FIG. 7A. The figure corresponds to the vicinity of the right center of FIG. 5, and the diagonal wiring portion is represented by a straight line for convenience.

AO is a boundary line of direct photoresist writing, in other words, a selective anodizing photoresist pattern. Therefore, the photoresist is removed after anodic oxidation, and the pattern AO shown in the figure does not remain as a finished product. However, since the oxide film AOF is selectively formed on the gate wiring GL as shown in the cross-sectional view, the locus thereof is changed. Remain. In the plan view, on the basis of the boundary line AO of the photoresist, the left side is a region covered with resist and not anodized, and the right side is a region exposed from the resist and anodized. The anodized Al layer g1 is formed with the oxide Al ₂ O ₃ film AOF on the surface, and the volume of the lower conductive portion is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains.

  In the figure, the Al layer g1 is hatched for easy understanding, but the region that is not anodized is patterned in a comb shape. This is because whisker is generated on the surface when the width of the Al layer is wide, so that the width of each one is narrowed, and a configuration in which a plurality of them are bundled in parallel prevents disconnection of whiskers. The aim is to minimize the sacrifice of the probability and conductivity.

  The gate terminal GTM is composed of an Al layer g1 and a transparent conductive layer g2 for protecting the surface of the Al layer g1 and improving the reliability of connection with TCP (Tape Carrier Package). This transparent conductive film g2 uses a transparent conductive film ITO formed in the same process as the pixel electrode PX. In addition, the conductive layers d1 and d2 formed on the Al layer g1 and on the side surfaces thereof have good connectivity to both the Al layer and the transparent conductive layer g2 in order to compensate for poor connection between the Al layer and the transparent conductive layer g2. The Cr layer d1 is connected to reduce the connection resistance, and the conductive layer d2 remains because the same mask is formed as the conductive layer d1.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line, and the protective film PSV1 is formed on the right side of the boundary line. The terminal portion GTM located at the left end is exposed from them and is electrically connected to the external circuit. Contact is made. In the figure, only one pair of the gate line GL and the gate terminal is shown, but actually, a plurality of such pairs are arranged vertically as shown in FIGS. 7A and 7B to form a terminal group Tg (FIG. 5). In the manufacturing process, the left end of the gate terminal extends beyond the cutting area of the substrate and is short-circuited by the wiring SHg (not shown). Such a short-circuit line SHg in the manufacturing process is useful for feeding power during anodization and preventing electrostatic breakdown during rubbing of the alignment film ORI1.
<< Drain terminal DTM >>
FIG. 8A is a plan view showing the connection from the video signal line DL to the external connection terminal DTM, and FIG. 8B shows a cross section taken along the line BB of FIG. 8A. This figure corresponds to the vicinity of the upper right of FIG. 5 and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end of the substrate SUB1.

  TSTd is an inspection terminal, to which no external circuit is connected, but is wider than the wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal DTM is also wider than the wiring portion so that it can be connected to an external circuit. The external connection drain terminals DTM are arranged in the vertical direction, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and are further extended beyond the cutting line of the substrate SUB1. All of them are short-circuited to each other by wiring SHd (not shown) in order to prevent electric breakdown. The inspection terminals TSTd are formed on every other video signal line DL as shown in FIG. 8A.

  The drain connection terminal DTM is formed of a single layer of the transparent conductive layer g2, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The transparent conductive film g2 is made of the transparent conductive film ITO formed in the same process as the pixel electrode PX as in the case of the gate terminal GTM. The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. Needless to say, the protective film PSV1 is removed on the drain terminal DTM in order to connect to an external circuit.

In the lead-out wiring from the matrix portion to the drain terminal portion DTM, the layers d1 and d2 at the same level as the video signal line DL are formed partway through the protective film PSV1, and are connected to the transparent conductive film g2 in the protective film PSV1. ing. This is intended to protect the Al layer d2 that is easily contacted as much as possible with the protective film PSV1 and the seal pattern SL.
<< Counter electrode terminal CTM >>
FIG. 9A shows a plan view showing the connection from the counter voltage signal line CL to its external connection terminal CTM, and FIG. 9B shows a cross section taken along the line BB of FIG. 9A. This figure corresponds to the vicinity of the upper left of FIG.

  Each counter voltage signal line CL is brought together by a common bus line CB and drawn to the counter electrode terminal CTM. The common bus line CB has a structure in which a conductive layer d1 and a conductive layer d2 are stacked on the conductive layer g1. This is to reduce the resistance of the common bus line CB so that the counter voltage is sufficiently supplied from the external circuit to each counter voltage signal line CL. This structure is characterized in that the resistance of the common bus line can be lowered without particularly loading a conductive layer. The conductive layer g1 of the common bus line CB is not anodized so as to be electrically connected to the conductive layer d1 and the conductive layer d2. The gate insulating film GI is also exposed.

The counter electrode terminal CTM has a structure in which a transparent conductive layer g2 is laminated on a conductive layer g1. This transparent conductive film g2 uses the transparent conductive film ITO formed in the same process as the pixel electrode PX as in the case of the other terminals. The transparent conductive layer g2 covers the conductive layer g1 with a transparent conductive layer g2 having good durability in order to protect the surface and prevent electrolytic corrosion and the like.
<< Equivalent circuit for the entire display device >>
FIG. 10 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.

  In the figure, X means a video signal line DL, and subscripts G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means the scanning signal line GL, and subscripts 1, 2, 3,..., End are added according to the order of scanning timing.

  The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.

SUP uses CRT (cathode ray tube) information from a power supply circuit or host (high-order processing unit) to obtain a plurality of stabilized voltage sources divided from one voltage source, and information for TFT liquid crystal display devices. This is a circuit including a circuit to be replaced.
<Driving method>
FIG. 11 shows a driving waveform of the liquid crystal display device of the present invention.

  In the first embodiment, since the counter voltage signal line CL is formed from the conductive film g1 made of low resistance metal such as aluminum, the load impedance is small and the waveform deformation of the counter voltage is small. For this reason, there is an advantage that the counter voltage can be changed to AC and the signal line voltage can be reduced.

  That is, the counter voltage is changed to a binary AC rectangular wave of Vch and Vcl, and the non-selection voltages of the scanning signals Vg (i-1) and Vg (i) are set to Vgl and Vgll for each scanning period in synchronization therewith. Change in binary. The amplitude value of the counter voltage and the amplitude value of the non-selection voltage are the same. The video signal voltage is a voltage obtained by subtracting 1/2 of the amplitude of the counter voltage from the voltage to be applied to the liquid crystal layer.

The counter voltage may be a direct current, but by making it an alternating current, the maximum amplitude of the video signal voltage can be reduced, and a video signal drive circuit (signal side driver) having a low withstand voltage can be used. In Examples 2 and 3 to be described later, since the counter voltage signal line CL is formed of the transparent conductive film g2, the resistance is relatively high, and the counter voltage is preferably a direct current system.
<Function of storage capacity Cstg>
The storage capacitor Cstg is provided to store video information written in the pixel (after the thin film transistor TFT is turned off) for a long time. The method of applying the electric field used in the present invention in parallel to the substrate surface differs from the method of applying the electric field perpendicular to the substrate surface because there is almost no capacitance (so-called liquid crystal capacitance) composed of the pixel electrode and the counter electrode. The storage capacitor Cstg cannot store the video information in the pixel. Therefore, the storage capacitor Cstg is an indispensable component in the method in which the electric field is applied parallel to the substrate surface.

  The storage capacitor Cstg also works to reduce the influence of the gate potential change ΔVg on the pixel electrode potential Vs when the thin film transistor TFT is switched. This situation can be expressed as follows.

ΔVs = [Cgs / (Cgs + Cstg + Cpix)] × ΔVg
Here, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT, Cpix is a capacitance formed between the pixel electrode PX and the counter electrode CT, and ΔVs is a pixel electrode potential by ΔVg. This represents a so-called feedthrough voltage. This change ΔVs causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the storage capacitor Cstg is increased. Reduction of the direct current component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is enlarged so as to completely cover the i-type semiconductor layer AS, an overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and accordingly, the parasitic capacitance Cgs is increased. The potential Vs has the adverse effect of being easily affected by the gate (scanning) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cstg.
"Production method"
Next, a manufacturing method on the substrate SUB1 side of the liquid crystal display device described above will be described with reference to FIGS. In the figure, the central letter is an abbreviation of the process name, the left side shows the thin film transistor TFT portion shown in FIG. 3, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal shown in FIG. Processes A to I, excluding process B and process D, are divided corresponding to each photographic process, and any cross-sectional view of each process shows a stage where the processing after the photographic process is finished and the photoresist is removed. In this description, photographic processing refers to a series of operations from photoresist application to selective exposure using a mask and development, and repeated description is avoided. The following explanation is based on the divided steps.

Process A, FIG.
On a lower transparent glass substrate SUB1 made of AN635 glass (trade name), a conductive film g1 made of Al—Pd, Al—Si, A1-Ta, Al—Ti—Ta or the like having a thickness of 3000 μm is provided by sputtering. After the photographic processing, the conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acetic acid. Thereby, the gate electrode GT, the scanning signal line GL, the counter electrode CT, the counter voltage signal line CL, the electrode PL1, the gate terminal GTM, the first conductive layer of the common bus line CB, the first conductive layer of the counter electrode terminal CTM, the gate An anodized bus line SHg (not shown) for connecting the terminal GTM and an anodized pad (not shown) connected to the anodized bus line SHg are formed.

Process B, FIG.
After the formation of the anodic oxidation mask AO by direct drawing, the substrate SUB1 was placed in an anodic oxidation solution consisting of a solution prepared by diluting 3% tartaric acid to pH 6.25 ± 0.05 with ammonia in an ethylene glycol solution 1: 9. It is immersed and adjusted so that the formation current density is 0.5 mA / cm ² (constant current formation). Next, anodic oxidation is performed until the formation voltage of 125 V necessary for obtaining a predetermined Al ₂ O ₃ film thickness is reached. Thereafter, it is desirable to maintain this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g1 is anodized, and an anodic oxide film AOF having a thickness of 1800 mm is formed on the gate electrode GT, the scanning signal line GL, the counter electrode CT, the counter voltage signal line CL, and the electrode PL1.

Process C, FIG.
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a Si nitride film having a thickness of 2200 mm, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form an i-type amorphous film with a thickness of 2000 mm. After providing the Si film, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to provide an N (+) type amorphous Si film having a thickness of 300 mm.

Process D, FIG. 13
After the photographic processing, the N (+) type amorphous Si film and the i type amorphous Si film are selectively etched using SF ₆ and CCl ₄ as dry etching gases, thereby forming the i type semiconductor layer AS. Form an island.

Process E, FIG. 13
After the photographic processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Process F, FIG. 13
A transparent conductive film g2 made of an ITO film having a thickness of 1400 mm is provided by sputtering. After the photo processing, the transparent conductive film g2 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, thereby forming the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the second conductive layer of the counter electrode terminal CTM. To do.

Process G, FIG.
A conductive film d1 made of Cr having a thickness of 600 に よ り is provided by sputtering, and a conductive film d2 made of Al-Pd, Al-Si, Al-Ta, Al-Ti-Ta, etc. having a thickness of 4000 に よ り is provided by sputtering. After the photographic processing, the conductive film d2 is etched with the same liquid as in the process B, the conductive film d1 is etched with the same liquid as in the process A, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the pixel electrode PX, the electrode A bus line SHd (not shown) that short-circuits PL2, the second conductive layer of the common bus line CB, the third conductive layer, and the drain terminal DTM is formed. Next, by introducing CCl ₄ and SF ₆ into a dry etching apparatus and etching the N (+) type amorphous Si film, the N (+) type semiconductor layer d0 between the source and the drain is selectively formed. Remove.

Process H, FIG. 14
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 1 μm-thick Si nitride film. After the photographic processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photolithography technique using SF ₆ as a dry etching gas.
<< Display Panel PNL and Drive Circuit Board PCB1 >>
FIG. 15 is a top view showing a state in which the video signal driving circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.

CHI is a driving IC chip for driving the display panel PNL (the lower five are driving IC chips on the vertical scanning circuit side, and the left ten are driving IC chips on the video signal driving circuit side). As will be described later with reference to FIGS. 16 and 17, TCP is a tape carrier package in which a driving IC chip CHI is mounted by a tape automated bonding method (TAB), and PCB1 is a driving circuit in which the above TCP, capacitor, and the like are mounted. The substrate is divided into two for a video signal driving circuit and for a scanning signal driving circuit. FGP is a frame ground pad, and a spring-shaped piece cut into the shield case SHD is soldered. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1. As shown in the figure, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material Sn plated) are sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer.
<< TCP connection structure >>
FIG. 16 is a diagram showing a cross-sectional structure of a tape carrier package TCP that constitutes the scanning signal driving circuit V and the video signal driving circuit H and in which an integrated circuit chip CHI is mounted on a flexible wiring board. FIG. It is principal part sectional drawing which shows the state connected to the terminal GTM for scanning signal circuits in this example of the panel.

  In the figure, TTB is an input terminal / wiring part of the integrated circuit CHI, and TTM is an output terminal / wiring part of the integrated circuit CHI, which is made of, for example, Cu, and each inner tip (commonly called inner lead) Bonding pads PAD of the integrated circuit CHI are connected by a so-called face-down bonding method. The outer tips (commonly referred to as outer leads) of the terminals TTB and TTM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively, and the anisotropic conductive film ACF is connected to the CRT / TFT conversion circuit / power supply circuit SUP by soldering or the like. Is connected to the liquid crystal display panel PNL. The package TCP is connected to the panel so that the tip thereof covers the protective film PSV1 exposing the connection terminal GTM on the panel PNL side. Therefore, the external connection terminal GTM (DTM) is at least the protective film PSV1 or the package TCP. On the other hand, since it is covered, it is strong against electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that the solder does not stick to an extra portion during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX after cleaning, and a silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to multiplex the protection.
<< Drive circuit board PCB2 >>
The drive circuit board PCB2 is mounted with electronic components such as an IC, a capacitor, and a resistor. The drive circuit board PCB2 is provided with a power supply circuit for obtaining a plurality of stabilized voltage sources divided from one voltage source and information for a CRT (cathode ray tube) from a host (high-order processing unit). A circuit SUP including a circuit for converting into information for a TFT liquid crystal display device is mounted. CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected.

The drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a flat cable FC.
<Overall configuration of liquid crystal display module>
FIG. 18 is an exploded perspective view showing each component of the liquid crystal display module MDL.

  SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW its display window, PNL is a liquid crystal display panel, SPB is a light diffusing plate, LCB is a light guide, RM is a reflector, BL is a backlight fluorescent tube LCA is a backlight case, and the modules MDL are assembled by stacking the members in a vertical arrangement relationship as shown in the figure.

  The module MDL is fixed in its entirety by claws and hooks provided in the shield case SHD.

  The backlight case LCA has a shape that accommodates the backlight fluorescent tube BL, the light diffusion plate SPB light diffusion plate, the light guide LCB, and the reflection plate RM, and is disposed on the side surface of the light guide LCB. The BL light is converted into a uniform backlight on the display surface by the light guide LCB, the reflection plate RM, and the light diffusion plate SPB, and emitted to the liquid crystal display panel PNL side.

  An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL and serves as a power source for the backlight fluorescent tube BL.

  As described above, in this embodiment, by making the pixel electrode transparent, the maximum transmittance when performing white display can be improved by about 30% (31.8% in this embodiment).

  Specifically, in this example, the transmittance improved from about 3.8% when an opaque pixel electrode was used to about 5.0% when a transparent pixel electrode was used.

  In addition, an ITO film for improving the reliability of the terminal can be formed at the same time, so that both reliability and productivity can be achieved.

This example is the same as Example 1 except for the following requirements. FIG. 20 shows a plan view of the pixel. The hatched portion in the figure indicates the transparent conductive film g2.
<< Pixel electrode PX >>
In the present embodiment, the pixel electrode PX includes a second conductive film d2 and a third conductive film d3 that are in the same layer as the source electrode SD1 and the drain electrode SD2. Further, the pixel electrode PX is formed integrally with the source electrode SD1.
<< Counter electrode CT >>
In this embodiment, the counter electrode CT is composed of a transparent conductive film g2. This transparent conductive film g2 is made of a transparent conductive film (Indium-Tin-Oxide.ITO: Nesa film) formed by sputtering, as in Example 1, and has a thickness of 100 to 2000 mm (in this example, 1400 mm). About a film thickness).
<< Counter voltage signal line CL >>
The counter voltage signal line CL is composed of the transparent conductive film g2 and is configured integrally with the counter electrode CT.
<Gate terminal section>
In this embodiment, the transparent conductive layer g2 for protecting the surface of the A1 layer g1 of the gate terminal GTM and improving the reliability of connection with the TCP (Tape Carrier Package) is formed in the same process as the counter electrode CT. To do. The configuration is the same as that of the first embodiment and is as shown in FIGS. 7A and 7B.
<< Drain terminal DTM >>
In this embodiment, the transparent conductive layer ITO formed in the same process as the counter electrode CT is used for the transparent conductive layer g2 of the drain connection terminal DTM as in the case of the gate terminal GTM. Although the structure is slightly different from that of the first embodiment in terms of the layer relationship, the figure is omitted because it is not essential.
<< Counter electrode terminal CTM >>
The transparent conductive layer g2 on the conductive layer g1 of the counter electrode terminal CTM uses the transparent conductive film ITO formed in the same process as the counter electrode CT as in the case of the other terminals. The configuration is the same as that of the first embodiment and is as shown in FIGS. 9A and 9B.
"Production method"
In this embodiment, the order of the process F enters between the process B and the process C of the first embodiment. As the process order, the process order shown in FIGS. 12 to 15 is in the order of A → B → F → C → D → E → G → H. As for the mask pattern, the scanning signal line GL, the scanning electrode GT, and the counter voltage signal line CL are separated, and the pattern of the transparent conductive layer g2 of each terminal and the counter voltage signal line CL is formed in the same mask.

  As described above, by making the counter electrode transparent, the maximum transmittance can be improved by about 16% (15.9% in this embodiment), and the transmittance of the liquid crystal display panel PNL is about 4.4%. .

This example is the same as Example 1 and Example 2 except for the following requirements. FIG. 21 shows a plan view of the pixel. The hatched portion in the figure shows the transparent conductive film g2.
<< Counter electrode CT >>
In this embodiment, the counter electrode CT is composed of a transparent conductive film g2. This transparent conductive film g2 is made of a transparent conductive film (Indium-T1N-Oxide.ITO: Nesa film) formed by sputtering in the same manner as in Example 1, and has a thickness of 100 to 2000 mm (in this example, 1400 mm). About a film thickness).
<< Counter voltage signal line CL >>
The counter voltage signal line CL is composed of the transparent conductive film g2 and is configured integrally with the counter electrode CT.
"Production method"
In the present embodiment, the order in which the process F is added between the process B and the process C in the first embodiment is the order. The order of the processes shown in FIGS. 12 to 15 is in the order of A → B → F → C → D → E → F → G → H. The mask pattern is formed in a mask in which the pattern of the scanning signal line GL, the scanning electrode GT, and the counter voltage signal line CL is independent.

  In this embodiment, by making both the pixel electrode and the counter electrode transparent, the maximum transmittance when performing white display is about 50% (47.7 in this embodiment) as compared with Embodiment 1 or Embodiment 2. %), And the transmittance of the liquid crystal display panel PNL is about 5.6%.

This example is the same as Example 1 and Example 3 except for the following requirements. FIG. 22 shows a plan view of the pixel. The hatched portion in the figure indicates the transparent conductive film g2.
<< Counter voltage signal line CL >>
The counter voltage signal line CL is composed of the conductive film g1. In this embodiment, Cr is used for the conductive film g1. Further, anodization is not performed in order to connect the counter voltage signal line CL and the counter electrode CT. Further, a through hole PH is formed in the gate insulating film GI. In addition to Cr, the conductive film g1 may be formed of Ta, Ti, Mo, W, Al, an alloy thereof, or a clad structure in which they are laminated.
"Production method"
In the present embodiment, the process B of the first embodiment is deleted. Further, the through hole PH is formed during the process E, and the pixel electrode PX and the counter electrode CT are simultaneously formed using the same mask during the process F.

  In the present embodiment, in addition to the effects of the first embodiment and the third embodiment, by reducing the resistance of the counter voltage signal line CL, the transmission of the voltage between the counter electrodes is made smooth, and the distortion of the voltage is reduced. Crosstalk (lateral smear) that occurs in the horizontal direction can be reduced.

  Further, by simultaneously forming the pixel electrode PX and the counter electrode CT with the same mask, the process F performed twice in Example 4 is performed once, and the productivity is improved.

This example is the same as Example 1 and Example 4 except for the following requirements. FIG. 23 shows a plan view of the pixel. The hatched portion in the figure indicates the transparent conductive film g2.
<< Counter electrode CT >>
In this embodiment, only the central counter electrode CT is constituted by the transparent conductive film g2. The counter electrode adjacent to the video signal line is formed of a metal film integrally with the counter voltage signal line.

  In the present embodiment, in addition to the effects of the first to fourth embodiments, crosstalk associated with the video signal can be suppressed by making the counter electrode adjacent to the video signal line opaque. The reason is as shown in the section of action.

  In both of the above-described Examples 2 and 3, the counter electrode signal line CL is formed of the transparent conductive layer g2 together with the counter electrode CT.

  In this case, in the present embodiment, the resistance value of the counter electrode signal line CL is greatly reduced by the configuration shown in FIGS.

  24A is a plan view showing a portion of the counter electrode signal line CL of FIG. 20, and FIG. 24B is a cross-sectional view taken along the line bb of FIG. 24A.

  In FIG. 20, the difference from FIG. 20 is that the counter electrode signal line CL has a two-layer structure, and an Al layer 10 having a small resistance value is formed as a lower layer, and the Al layer 10 is completely formed on the upper surface of the Al layer 10. An ITO film 11 is formed so as to cover the surface. The counter electrode CT is constituted by an extended portion in which a part of the ITO film 11 is extended.

  In this case, the resistance of the counter electrode signal line CL can be reduced, and another conductive layer (for example, an image) via an interlayer insulating film formed by whisker-like projections called so-called whiskers generated in the Al layer 10 can be used. It is possible to prevent an electrical short circuit of the signal line DL).

  That is, the Al layer 10 is known to cause whiskers when the interlayer insulating film for the video signal line DL is formed on the Al layer 10 to cause the above-mentioned problems. However, the Al layer 10 should be completely covered. Thus, it has been confirmed that the whisker is not generated by forming the ITO film.

  Further, FIG. 24C shows a configuration in which the counter electrode CT is constituted by a double wiring. In this example, the wiring of the ITO film 11 is formed so as to cover the wiring of the Al layer 10. In the vicinity of the center line of the wiring, even when a voltage is applied between the electrodes, the transmittance is low. Therefore, even if an opaque metal wiring is arranged as in this example, the aperture ratio is hardly reduced.

  By adopting double wiring for the counter electrode or the pixel electrode, it is possible to greatly reduce the disconnection failure of the electrode, which is a problem on a large screen.

<Active matrix liquid crystal display device>
Hereinafter, embodiments in which the present invention is applied to an active matrix color liquid crystal display device will be described. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
<< Planar structure of matrix part (pixel part) >>
FIG. 25 is a plan view showing one pixel of the active matrix color liquid crystal display device of the present invention and its periphery. (The hatched portion in the figure indicates the transparent conductive film i1.)
As shown in FIG. 25, each pixel includes a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring) CL, and two adjacent video signal lines (drain signal lines). Or, it is arranged in a region intersecting with the vertical signal line (DL) (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL and counter-voltage signal lines CL are arranged in the up-down direction. The video signal lines DL extend in the vertical direction, and a plurality of video signal lines DL are arranged in the horizontal direction. The pixel electrode PX is formed of a transparent conductive film i1, and is electrically connected to the thin film transistor TFT via the source electrode SD1, and the counter electrode CT is also formed of the transparent conductive film i1 and is electrically connected to the counter voltage signal line CL. ing.

  The pixel electrode PX and the counter electrode CT face each other, and the optical state of the liquid crystal LC is controlled by the electric field between each pixel electrode PX and the counter electrode CT, thereby controlling display. The pixel electrode PX and the counter electrode CT are formed in a comb-teeth shape, and are each an elongated electrode in the vertical direction of the figure.

  The number O (number of comb teeth) of the counter electrode CT in one pixel is configured to have a relation of the number of pixel electrodes PX (number of comb teeth) P and O = P + 1 (in this embodiment, O). = 3, P = 2). This is because the counter electrodes CT and the pixel electrodes PX are alternately arranged, and the counter electrodes CT are necessarily adjacent to the video signal lines DL. Thus, the electric field lines from the video signal line DL can be shielded by the counter electrode CT so that the electric field between the counter electrode CT and the pixel electrode PX is not affected by the electric field generated from the video signal line DL. it can. Since the counter electrode CT is always supplied with a potential from the outside by a counter voltage signal line CL, which will be described later, the potential is stable. Therefore, there is almost no fluctuation in potential even when adjacent to the video signal line DL. In addition, since the geometric position of the pixel electrode PX from the video signal line DL becomes far away, the parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the video of the pixel electrode potential Vs. Variations due to signal voltage can also be suppressed. As a result, crosstalk (image quality failure called vertical smear) that occurs in the vertical direction can be suppressed.

  The electrode width of the pixel electrode PX and the counter electrode CT is 6 μm. In order to apply a sufficient electric field to the entire liquid crystal layer with respect to the thickness direction of the liquid crystal layer, the thickness is set to be sufficiently larger than the thickness 3.9 μm of the liquid crystal layer, which will be described later, and as much as possible to increase the aperture ratio. Make it thinner. Further, the electrode width of the video signal line DL is set to 8 μm that is slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection. Here, the electrode width of the video signal line DL is set to be not more than twice the electrode width of the adjacent counter electrode CT. Alternatively, when the electrode width of the video signal line DL is determined from the productivity of the yield, the electrode width of the counter electrode CT adjacent to the video signal line DL is set to ½ or more of the electrode width of the video signal line DL. . This is because the electric lines of force generated from the video signal line DL are absorbed by the counter electrodes CT on both sides, and in order to absorb the electric lines of force generated from a certain electrode width, an electrode width equal to or larger than that is used. An electrode with is required. Therefore, the counter electrode CT on both sides only needs to absorb the electric lines of force generated from half of the electrodes of the video signal line DL (4 μm each), so that the electrode width of the counter electrode CT adjacent to the video signal line DL is 1. / 2 or more. This prevents crosstalk, particularly in the vertical direction (vertical crosstalk), due to the influence of the video signal.

  The scanning signal line GL sets the electrode width so as to satisfy a resistance value sufficient to apply a scanning voltage to the gate electrode GT of the pixel on the terminal side (opposite side of a scanning electrode terminal GTM described later). Further, the counter voltage signal line CL also has a resistance value sufficient to apply a counter voltage to the counter electrode CT of the pixel on the end side (the pixel farthest from common bus lines CB1 and CB2, which will be described later, that is, a pixel intermediate between CB1 and CB2). The electrode width is set so as to satisfy.

On the other hand, the electrode interval between the pixel electrode PX and the counter electrode CT varies depending on the liquid crystal material used. This is because the electric field strength that achieves the maximum transmittance differs depending on the liquid crystal material, so the electrode spacing is set according to the liquid crystal material, and the maximum amplitude of the signal voltage set by the withstand voltage of the video signal drive circuit (signal side driver) to be used This is because the maximum transmittance can be obtained within the above range. When a liquid crystal material described later is used, the electrode interval is 16 μm.
<< Cross-sectional structure of matrix part (pixel part) >>
26 is a cross-sectional view taken along line 6-6 in FIG. 25, FIG. 27 is a cross-sectional view taken along line 7-7 in FIG. 25, and FIG. 28 is a cross-sectional view taken along line 8-8 in FIG. FIG.

  As shown in FIGS. 26 to 28, a thin film transistor TFT, a storage capacitor Cstg, and an electrode group are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and a color filter FIL on the upper transparent glass substrate SUB2 side. A light blocking black matrix pattern BM is formed.

In addition, alignment films ORI and ORI2 for controlling the initial alignment of the liquid crystal are provided on the inner surfaces (liquid crystal LC side) of the transparent glass substrates SUB1 and SUB2, and the outer surfaces of the transparent glass substrates SUB1 and SUB2. Is provided with a polarizing plate in which the polarization axes are arranged orthogonally (crossed Nicols arrangement).
<< TFT substrate >>
First, the configuration of the lower transparent glass substrate SUB1 side (TFT substrate) will be described in detail.
<< Thin Film Transistor TFT >>
The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases.

As shown in FIG. 27, the thin film transistor TFT includes an i-type semiconductor layer AS made of a gate electrode GT, an insulating film GI, i-type (intrinsic, intrinsic, conductivity-type determining impurities are not doped) amorphous silicon (Si). And a pair of source electrode SD1 and drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so that the source and drain are interchanged during operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.
<< Gate electrode GT >>
The gate electrode GT is formed continuously with the scanning signal line GL, and a part of the scanning signal line GL is configured to be the gate electrode GT. The gate electrode GT is a portion exceeding the active region of the thin film transistor TFT. In this example, the gate electrode GT is formed of a single-layer conductive film g3. For example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used as the conductive film g3, but the conductive film g3 is not limited thereto.
<< Scanning signal line GL >>
The scanning signal line GL is composed of a conductive film g3. The conductive film g3 of the scanning signal line GL is formed in the same manufacturing process as that of the conductive film g3 of the gate electrode GT and is integrally formed. Through this scanning signal line GL, a gate voltage Vg is supplied from an external circuit to the gate electrode GT. In this example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering, for example, is used as the conductive film g3. Further, the scanning signal line GL and the gate electrode GT are not limited to the chromium-molybdenum alloy, but may be a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum to reduce resistance, for example. Good. Further, the portion intersecting with the video signal line DL may be narrowed to reduce the probability of short circuit with the video signal line DL, or it may be bifurcated so that it can be separated by laser trimming even if shorted.
<< Counter voltage signal line CL >>
The counter voltage signal line CL is composed of a conductive film g3. The conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, the scanning signal line GL, and the counter electrode CT, and is configured to be electrically connected to the counter electrode CT. Yes. The counter voltage signal line CL supplies the counter voltage Vcom from the external circuit to the counter electrode CT.

  Further, the counter voltage signal line CL is not limited to the chromium-molybdenum alloy, and may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum, for example, to reduce resistance.

Further, the portion intersecting with the video signal line DL may be narrowed to reduce the probability of short circuit with the video signal line DL, or it may be bifurcated so that it can be separated by laser-trimming even if short-circuited.
<Insulating film GI>
The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected and formed to a thickness of 2500 to 4500 mm (about 3500 mm in this embodiment). The insulating film GI also functions as an interlayer insulating film between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL, and contributes to their electrical insulation. The insulating film GI is patterned with the same photomask as a protective film PSV1 described later, and is processed in a lump.
<< i-type semiconductor layer AS >>
The i-type semiconductor layer AS is made of amorphous silicon and has a thickness of 200 to 2500 mm (in this embodiment, a film thickness of about 1200 mm).

  The layer d0 is an N (+) type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, only where the i type semiconductor layer AS is present on the lower side and the conductive layer d3 is present on the upper side. Is left behind.

The i-type semiconductor layer AS and the layer d0 are also provided between the scanning signal line GL and the crossing portion (crossover portion) between the counter voltage signal line CL and the video signal line DL. This crossing portion i-type semiconductor layer AS reduces a short circuit between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL at the crossing portion.
<< Source electrode SD1, drain electrode SD2 >>
Each of the source electrode SD1 and the drain electrode SD2 includes a conductive film d3 that is in contact with the N (+) type semiconductor layer d0.

The conductive film d3 is made of a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering and is formed to a thickness of 500 to 3000 mm (in this embodiment, about 2500 mm). Since the Cr—Mo film has low stress, it can be formed with a relatively large film thickness, which contributes to reducing the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr—Mo film, Alternatively, a laminated structure with aluminum or the like may be used.

After patterning the conductive film d3 with a mask pattern, the N (+) type semiconductor layer d0 is removed using the conductive film d3 as a mask. That is, the N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS is removed by self-alignment except for the conductive film d1 and the conductive film d2. At this time, since the N (+) type semiconductor layer d0 is etched so that the entire thickness thereof is removed, the surface portion of the i type semiconductor layer AS is also slightly etched, but the degree is controlled by the etching time. do it.
<< Video signal line DL >>
The video signal line DL is composed of a conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2. The video signal line DL is formed integrally with the drain electrode SD2. In this example, the conductive film d3 is made of a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering, and is formed to a thickness of 500 to 3000 mm (in this embodiment, about 2500 mm). Since the Cr—Mo film has low stress, it can be formed with a relatively large film thickness, which contributes to reducing the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr—Mo film, Alternatively, a laminated structure with aluminum or the like may be used.
<< Storage capacity Cstg >>
The conductive film d3 is formed so as to overlap with the counter voltage signal line CL in the source electrode SD2 portion of the thin film transistor TFT. As is apparent from FIG. 28, this superposition forms a storage capacitor (capacitance element) Cstg having the source electrode SD2 (d3) as one electrode and the counter voltage signal CL as the other electrode. The dielectric film of the storage capacitor Cstg is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT.

As shown in FIG. 25, the storage capacitor Cstg is formed in a part of the counter voltage signal line CL in plan view.
<< Protective film PSV1 >>
A protective film PSV1 is provided on the thin film transistor TFT. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and a film having high transparency and good moisture resistance is used. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and is formed with a film thickness of about 0.3 to 1 μm.

The protective film PSV1 is removed so as to expose the external connection terminals DTM and GTM. Regarding the thickness relationship between the protective film PSV1 and the insulating film GI, the former is thickened in consideration of the protective effect, and the latter is thinned in the mutual conductance gm of the transistor. Further, the protective film PSV1 is patterned with the same photomask as the insulating film GI and is processed at once. Further, in the pixel portion, through holes TH2 and TH1 are provided for electrical connection between the counter voltage signal line CL and a counter electrode CT described later and for electrical connection between the source electrode SD2 and the pixel electrode PX. . In the through hole TH2, since the protective film PSV1 and the insulating film GI are processed at once, there is a hole up to the g3 layer, and in the through hole TH1, a hole up to the d3 layer is formed because it is blocked by d3.
<< Pixel electrode PX >>
The pixel electrode PX is formed of a transparent conductive layer i1. This transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-Oxide .. ITO: Nesa film) formed by sputtering, and is formed to a thickness of 100 to 2000 mm (in this embodiment, a film thickness of about 1400 mm). Is done. The pixel electrode PX is connected to the source electrode SD2 through the through hole TH1.

Since the pixel electrode becomes transparent as in this embodiment, the maximum transmittance at the time of white display is improved by the transmitted light of the portion, so that a brighter display is performed than when the pixel electrode is opaque. be able to. At this time, as will be described later, when no voltage is applied, the liquid crystal molecules maintain the initial alignment state, and the arrangement of the polarizing plates is configured so as to display black in that state (a normally black mode is set). Therefore, even if the pixel electrode is transparent, light of that portion is not transmitted, and high-quality black can be displayed. Thereby, the maximum transmittance can be improved and a sufficient contrast ratio can be achieved.
<< Counter electrode CT >>
The counter electrode CT is formed of a transparent conductive layer i1. This transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-0xide .. ITO: Nesa film) formed by sputtering, and is formed to a thickness of 100 to 2000 mm (in this embodiment, a film thickness of about 1400 mm). Is done. The counter electrode CT is connected to the counter voltage signal line CL through the through hole TH2.

A counter voltage Vcom is applied to the counter electrode CT. In this embodiment, the counter voltage Vcom is a feed generated when the thin film transistor element TFT is turned off from an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL. Although the potential is set lower by the through voltage ΔVs, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal driving circuit to about half, an AC voltage may be applied.
<Color filter substrate>
Next, returning to FIGS. 25 and 26, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.
<< Light shielding film BM >>
A light shielding film is provided on the upper transparent glass substrate SUB2 side so that transmitted light from an unnecessary gap (gap other than between the pixel electrode PX and the counter electrode CT) is emitted to the display surface side and the contrast ratio or the like is not lowered. A BM (so-called black matrix) is formed. The light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched by the upper and lower light shielding films BM and the large gate electrode GT, and is not exposed to external natural light or backlight light.

  The light shielding film BM shown in FIG. 25 has a configuration extending linearly in the left-right direction above the thin film transistor element TFT. This pattern is an example, and it can also be in the form of a matrix with openings formed in holes. In a portion where the electric field direction is disturbed, such as at the end of the comb electrode, the display of the portion corresponds to the video information in the pixel on a one-to-one basis, and in black, it is black, and in white, it is white. Therefore, it can be used as a part of the display. Further, the gap between the counter electrode CT and the video signal line DL in the vertical direction in the drawing is shielded by the light shielding layer SH formed in the same process as the gate electrode GT. As a result, since the light shielding in the vertical direction in the horizontal direction can be shielded with high accuracy by the alignment accuracy of the TFT process, the boundary of the light shielding layer SH can be set between the electrodes of the counter electrode CT adjacent to the video signal line DL. The opening can be enlarged more than the light shielding by the light shielding film BM depending on the alignment accuracy.

  The light shielding film BM has a light shielding property and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT. Is mixed with a resist material to form a thickness of about 1.2 μm.

  The light shielding film BM is formed in a line in the left-right direction on the pixels of each row, and the effective display area of each row is partitioned by this line. Therefore, the contour of the pixels in each row is made clear by the light shielding film BM. That is, the light shielding film BM has two functions of black matrix and light shielding for the i-type semiconductor layer AS.

The light shielding film BM is also formed in a frame shape in the peripheral portion, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. The peripheral light shielding film BM is extended to the outside of the seal portion SL to prevent leakage light such as reflected light from a mounting device such as a personal computer from entering the matrix portion, and light such as a backlight is out of the display area. It also prevents leaks. On the other hand, the light-shielding film BM is retained about 0.3 to 1.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cutting region of the substrate SUB2.
<Color filter FIL>
Same as Example 1.
<< Overcoat film OC >>
Same as Example 1.
<< Liquid crystal layer, alignment film and deflector >>
Same as Example 1.
<Configuration around the matrix>
Same as Example 1.

<Gate terminal section>
FIG. 29A is a plan view showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, and FIG. 29B is a cross-sectional view taken along the line BB of FIG. 29A. The figure corresponds to the vicinity of the right center of FIG. 5, and the diagonal wiring portion is shown in a straight line for convenience.

  In the drawing, the Cr—Mo layer g3 is hatched for easy understanding.

  The gate terminal GTM is composed of a Cr—Mo layer g3 and a transparent conductive layer i1 for further protecting the surface of the Cr—Mo layer g3 and improving the reliability of connection with TCP (Tape Carrier Package). The transparent conductive layer i1 uses a transparent conductive film ITO formed in the same process as the pixel electrode PX.

In the plan view, the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located at the left end is exposed from them so as to be able to make electrical contact with an external circuit. . In the figure, only one pair of the gate line GL and the gate terminal is shown, but actually, a plurality of such pairs are arranged vertically as shown in FIG. 29A to form the terminal group Tg (FIG. 5). In the manufacturing process, the left end of the gate terminal extends beyond the cutting region of the substrate and is short-circuited by the wiring SHg (not shown). This is useful for preventing electrostatic breakdown during rubbing of the alignment film ORI1 during the manufacturing process.
<< Drain terminal DTM >>
FIG. 30A is a plan view showing the connection from the video signal line DL to its external connection terminal DTM, and FIG. 30B is a cross-sectional view taken along the line BB in FIG. 30A. This figure corresponds to the vicinity of the upper right of FIG. 5 and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end of the substrate SUB1.

  TSTd is an inspection terminal, to which no external circuit is connected, but is wider than the wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal DTM is also wider than the wiring portion so that it can be connected to an external circuit. The external connection drain terminals DTM are arranged in the vertical direction, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and are further extended beyond the cutting line of the substrate SUB1. All of them are short-circuited to each other by wiring SHd (not shown) in order to prevent electric breakdown. The inspection terminals TSTd are formed on every other video signal line DL as shown in FIG.

  The drain connection terminal DTM is formed of the transparent conductive layer i1, and is connected to the video signal line DL at a portion where the protective film PSV1 is removed. The transparent conductive film i1 is made of the transparent conductive film ITO formed in the same process as the pixel electrode PX as in the case of the gate terminal GTM.

A layer d3 having the same level as that of the video signal line DL is formed in the lead-out wiring from the matrix portion to the drain terminal portion DTM.
<< Counter electrode terminal CTM >>
FIG. 31A is a plan view showing the connection from the counter voltage signal line CL to the external connection terminal CTM, and FIG. 31B is a cross-sectional view taken along the line BB in FIG. 31A. This figure corresponds to the vicinity of the upper left of FIG.

  The counter voltage signal lines CL are gathered together by a common bus line CB1 and led out to the counter electrode terminal CTM. The common bus line CB has a structure in which the conductive layer 3 is stacked on the conductive layer g3 and these are electrically connected by the transparent conductive layer i1. This is to reduce the resistance of the common bus line CB so that the counter voltage is sufficiently supplied from the external circuit to each counter voltage signal line CL. This structure is characterized in that the resistance of the common bus line can be lowered without particularly loading a conductive layer.

  The counter electrode terminal CTM has a structure in which a transparent conductive layer i1 is laminated on a conductive layer g3. This transparent conductive film i1 uses the transparent conductive film ITO formed in the same process as the pixel electrode PX as in the case of the other terminals. The conductive layer g3 is covered with the transparent conductive layer i1 having good durability in order to protect the surface by the transparent conductive layer i1 and prevent electrolytic corrosion and the like. The transparent conductive layer i1, the conductive layer g3, and the conductive layer d3 are electrically connected by forming a through hole in the protective film PSV1 and the insulating film GI.

On the other hand, FIG. 32A shows a plan view showing the connection from the other end of the counter voltage signal line CL to the external connection terminal CTM2, and FIG. 32B shows a cross-sectional view taken along the line BB of FIG. 32A. The figure corresponds to the vicinity of the upper right of FIG. Here, in the common bus line CB2, the other end (gate terminal GTM side) of each counter voltage signal line CL is gathered and led to the counter electrode terminal CTM2. The difference from the common bus line CB1 is that the conductive layer d3 and the transparent conductive layer i1 are formed so as to be insulated from the scanning signal line GL. Insulation with the scanning signal line GL is performed by the insulating film GI.
<< Equivalent circuit for the entire display device >>
FIG. 33 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.

  In the figure, X means a video signal line DL, and subscripts G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means the scanning signal line GL, and subscripts 1, 2, 3,..., End are added according to the order of scanning timing.

  The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.

SUP uses CRT (cathode ray tube) information from a power supply circuit or host (high-order processing unit) to obtain a plurality of stabilized voltage sources divided from one voltage source, and information for TFT liquid crystal display devices. This is a circuit including a circuit to be replaced.
<Driving method>
FIG. 34 shows drive waveforms of the liquid crystal display device of this example. The counter voltage Vc is a constant voltage. The scanning signal Vg takes an on level every scanning period, and the other takes an off level. The video signal voltage is applied so that the positive and negative electrodes are inverted every frame and transmitted to one pixel with an amplitude twice that of the voltage to be applied to the liquid crystal layer. Here, the polarity of the video signal voltage Vd is inverted every column, and the polarity is inverted every row. Accordingly, the pixels whose polarities are reversed are arranged vertically and horizontally, and flicker and crosstalk (smear) can be made difficult to occur. Further, the counter voltage Vc is set to a voltage that is a certain amount less than the center voltage of the polarity inversion of the video signal voltage. This is to correct a feedthrough voltage generated when the thin film transistor element changes from on to off, and is applied to apply an alternating voltage having a small direct current component to the liquid crystal. This is because the residual image, deterioration, and the like become severe when a direct current is applied to the liquid crystal.

In addition, the maximum amplitude of the video signal voltage can be reduced by turning the counter voltage into an alternating current, and a video signal drive circuit (signal side driver) having a low withstand voltage can be used.
<Function of storage capacity Cstg>
Same as Example 1.
"Production method"
Next, a manufacturing method on the substrate SUB1 side of the liquid crystal display device described above will be described with reference to FIGS. In the figure, the central letter is an abbreviation of the process name, the left side shows the thin film transistor TFT portion shown in FIG. 27, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal shown in FIG. Processes A to I, excluding process B and process D, are divided corresponding to each photographic process, and any cross-sectional view of each process shows a stage where the processing after the photographic process is finished and the photoresist is removed. In this description, photographic processing refers to a series of operations from photoresist application to selective exposure using a mask and development, and repeated description is avoided. This will be described in accordance with the divided steps.

Process A, FIG. 35
On the lower transparent glass substrate SUB1 made of AN635 glass (trade name), a conductive film g3 made of Cr—Mo or the like having a film thickness of 2000 mm is provided by sputtering. After the photographic processing, the conductive film g3 is selectively etched with ceric ammonium nitrate. Thereby, the bus line SHg connecting the gate electrode GT, the scanning signal line GL, the counter voltage signal line CL gate terminal GTM, the first conductive layer of the common bus line CB1, the first conductive layer of the counter electrode terminal CTM1, and the gate terminal GTM. (Not shown).

Process B, FIG. 35
Introducing ammonia gas, silane gas, and nitrogen gas into the plasma CVD apparatus to provide a Si nitride film with a thickness of 3500 mm, introducing silane gas and hydrogen gas into the plasma CVD apparatus, and an i-type amorphous film with a thickness of 1200 mm After providing the Si film, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to provide an N (+) type amorphous Si film having a thickness of 300 mm.

Process C, FIG.
After photographic processing, by selectively etched using SF6, CCl ₄ as a dry etching gas N (+) type amorphous Si film, the i-type amorphous Si film, the island of the i-type semiconductor layer AS Form.

Process D, FIG. 36
A conductive film d3 made of Cr having a thickness of 300 mm is provided by sputtering. After the photo processing, the conductive film d3 is etched with the same liquid as in step A, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the first conductive layer of the common bus line CB2, and the bus line that short-circuits the drain terminal DTM. SHd (not shown) is formed. Next, CCl4 and SF6 are introduced into a dry etching apparatus to etch the N (+) type amorphous Si film, thereby selectively removing the N (+) type semiconductor layer d0 between the source and drain. .

Process E, FIG. 36
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 0.4 μm-thick Si nitride film. After the photographic process, the protective film PSV1 and the insulating film GI are patterned by selectively etching the Si nitride film using SF6 as a dry etching gas.

Process F, FIG.
A transparent conductive film i1 made of an ITO film having a thickness of 1400 mm is provided by sputtering. After the photographic processing, the transparent conductive film i1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the second conductive layers of the counter electrode terminals CTM1 and CTM2 Form.
<< Display Panel PNL and Drive Circuit Board PCB1 >>
Same as Example 1.
<< TCP connection structure >>
Same as Example 1.
<< Drive circuit board PCB2 >>
Same as Example 1.
<Overall configuration of liquid crystal display module>
Same as Example 1.

  As described above, in the present embodiment, by making the comb electrodes transparent as in the third embodiment, the maximum transmittance when performing white display can be improved by about 50%, and the transmittance of the liquid crystal display panel PNL is about It becomes 5.7%.

  In addition, an ITO film for improving the reliability of the terminal can be formed at the same time, so that both reliability and productivity can be achieved.

  Also, in this embodiment, unlike the first to sixth embodiments, the process of forming ITO on the upper layer of the protective film PSV is used, so that the counter electrode can be brought to the uppermost layer, and from the video signal line. The shielding efficiency of the leakage electric field is also good, and crosstalk can be reduced.

  Further, since the protective film PSV is not interposed in the path of the electric lines of force for driving the liquid crystal between the electrodes, there is no voltage reduction in the protective film PSV, and the maximum driving voltage value for driving the liquid crystal is set to 7. In this example, the voltage could be reduced from 5 Volt to 5.0 Volt.

  In the method of driving the liquid crystal by applying a substantially parallel electric field to the substrate surface as in this method, the protective film is inserted twice in the path of the electric lines of force between the electrodes, and the process can be simplified. , Productivity is also improved.

This example is the same as Example 7 except for the following requirements. FIG. 38 is a plan view of the pixel. The hatched portion in the figure indicates the transparent conductive film i1.
<< Pixel electrode PX >>
In this embodiment, the pixel electrode PX is composed of a conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2. Further, the pixel electrode PX is formed integrally with the source electrode SD1.

  In the present embodiment, in addition to the effects of the first embodiment, the transmittance is sacrificed, but contact failure between the pixel electrode PX and the source electrode SD1 can be avoided. In addition, since one of the electrodes is covered with the insulating film (protective film PSV1), the possibility of a direct current flowing through the liquid crystal when there is an alignment film defect is reduced, liquid crystal deterioration or the like is eliminated, and reliability is improved.

This example is the same as Example 7 except for the following requirements. FIG. 39 is a plan view of the pixel. The hatched portion in the figure indicates the transparent conductive film i1.
<< Counter electrode CT >>
In this embodiment, the counter electrode CT is integrally formed with the counter voltage signal line CL by the conductive film g3.

  In this embodiment, in addition to the effects of the first embodiment, the transmittance is sacrificed, but contact failure between the counter electrode CT and the counter voltage signal line CL can be avoided. In addition, since one of the electrodes is covered with the insulating film (protective film PSV1), the possibility of a direct current flowing through the liquid crystal when there is an alignment film defect is reduced, liquid crystal deterioration or the like is eliminated, and reliability is improved.

This example is the same as Example 7 except for the following requirements. FIG. 40 is a plan view of the pixel. The hatched portion in the figure indicates the transparent conductive film i1.
<< Light shielding film BM >>
A light shielding film is provided on the upper transparent glass substrate SUB2 side so that transmitted light from an unnecessary gap (gap other than between the pixel electrode PX and the counter electrode CT) is emitted to the display surface side and the contrast ratio or the like is not lowered. A BM (so-called black matrix) is formed. The light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched by the upper and lower light shielding films BM and the large gate electrode GT, and is not exposed to external natural light or backlight light.

  The light shielding film BM shown in FIG. 40 has a configuration extending in the vertical and horizontal directions above the thin film transistor element TFT, and has a matrix shape with holes in the openings. In a portion where the electric field direction is disturbed, such as at the end of the comb electrode, the display of the portion corresponds to the video information in the pixel on a one-to-one basis, and in black, it is black, and in white, it is white. Therefore, it can be used as a part of the display.

  In the present embodiment, unlike the seventh embodiment, the light shielding film BM has a light shielding property, and the electric field from the video signal line DL does not affect the electric field between the pixel electrode PX and the counter electrode CT. In this embodiment, the three-layer structure of chromium oxide (CrOx), chromium nitride (CrNx), and chromium (Cr) is about 0.2 μm from the surface of the counter substrate SUB1. It is formed with a thickness. At this time, chromium oxide (CrOx) is used to suppress reflection on the display surface. Chromium (Cr) is provided on the uppermost layer of the light shielding layer BM so that a voltage can be applied to the light shielding film BM from the outside.

  The light shielding film BM is formed in a line in the left-right direction on the pixels of each row, and the effective display area of each row is partitioned by this line. Therefore, the outline of the pixels in each row is clarified by the light shielding film BM. That is, the light shielding film BM has two functions of black matrix and light shielding for the i-type semiconductor layer AS.

The light shielding film BM is also formed in a frame shape in the peripheral portion, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. The peripheral light shielding film BM is extended to the outside of the seal portion SL to prevent leakage light such as reflected light from a mounting device such as a personal computer from entering the matrix portion, and light such as a backlight is out of the display area. It also prevents leaks. On the other hand, the light-shielding film BM is retained about 0.3 to 1.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cutting region of the substrate SUB2.
<< Overcoat film OC >>
Same as Example 1. However, a through hole may be formed so that a potential is applied to the light shielding film BM. The potential is preferably connected to the counter voltage Vc.

  In the present embodiment, in addition to the effects of the seventh embodiment, the light shielding film BM shields the influence of the electric field from the video signal line DL, so that the electric field between the pixel electrode PX and the counter electrode CT is not affected thereby. . Therefore, there is no crosstalk with the video signal line DL, and image quality defects (smear) that draw lines on the screen can be eliminated. In addition, a region where the transparent counter electrode CT disposed on both sides of the video signal line DL is shielded by the light shielding layer SH can be reduced, and higher transmittance can be achieved.

  FIG. 43 is a diagram showing the principle of improving the aperture ratio of the active matrix type color liquid crystal display device of this example, and FIG. 43A is a characteristic diagram showing the potential distribution in the liquid crystal layer when a voltage is applied to the electrodes. 43B is a plan view showing the realignment state of the liquid crystal molecules near the center of the liquid crystal layer, FIG. 43C is a characteristic diagram showing the rotation angle α of the liquid crystal molecules shown in FIG. 43B, and FIG. It is an example of the characteristic view which shows the transmittance | permeability distribution of the light which permeate | transmits a liquid crystal layer on a board | substrate, an electrode, and between electrodes.

  Here, it is the same as Example 7 except the following requirements.

In this embodiment, about 2 × 10 ⁻¹² N (Newton) is used as the twist elastic constant K2 of the liquid crystal layer.

For example, when a relatively large value of about 10 × 10 ⁻¹² N (Newton) is used as the twist elastic constant K2, as shown in FIG. 41B, the rotation angle α of the liquid crystal molecules at the center on the electrode is almost zero. As a result, the transmittance at the central part on the electrode is almost dark.

  On the other hand, in this embodiment, even the liquid crystal molecules in the central portion on the electrode rotate, and the average transmittance of the transmittance of the A portion between the electrodes is 50% or more of the average transmittance of the transmittance of the B portion on the electrode. It turns out that it becomes rate.

  Therefore, the average transmittance of the entire portion becomes an average transmittance of the transmittance of the A + B portion, and is greatly increased.

  As described above, the present invention is applied to a liquid crystal or the like, and may be practically used in the liquid crystal manufacturing industry.

1 is a plan view of a main part showing one pixel of a liquid crystal display unit and its periphery in an active matrix color liquid crystal display device according to Example 1 of the present invention; It is sectional drawing of the pixel in the 3-3 cutting line of FIG. FIG. 4 is a cross-sectional view of the thin film transistor element TFT taken along line 4-4 in FIG. 1. FIG. 5 is a cross-sectional view of the storage capacitor Cstg taken along the line 5-5 in FIG. 4 is a plan view for explaining a configuration of a matrix peripheral portion of the display panel. FIG. It is sectional drawing which shows the panel edge part which does not have a scanning signal terminal on the left side, and an external connection terminal on the right side. FIG. 7B is a plan view (FIG. 7A) and a cross-sectional view (FIG. 7B) showing the vicinity of a connection portion between the gate terminal GTM and the gate wiring GL. FIG. 8 is a plan view (FIG. 8A) and a cross-sectional view (FIG. 8B) showing the vicinity of a connection portion between the drain terminal DTM and the video signal line DL. FIG. 9B is a plan view (FIG. 9A) and a cross-sectional view (FIG. 9B) showing the vicinity of a connection portion between the common electrode terminal CTM, the common bus line CB, and the common voltage signal line CL. 1 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device of the present invention. It is a figure which shows the drive waveform of the active matrix type color liquid crystal display device of this invention. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process AC of the board | substrate SUB1 side. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process DF by the side of the board | substrate SUB1. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process GH by the side of the board | substrate SUB1. It is a top view which shows the state which mounted the peripheral drive circuit on the liquid crystal display panel. It is a figure which shows the cross-section of tape carrier package TCP in which the integrated circuit chip CHI which comprises a drive circuit was mounted in the flexible wiring board. It is principal part sectional drawing which shows the state which connected the tape carrier package TCP to the scanning signal circuit terminal GTM of liquid crystal display panel PNL. It is a disassembled perspective view of a liquid crystal display module. It is a figure which shows the relationship between an applied electric field direction, a rubbing direction, and a polarizing plate transmission axis. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 2 of this invention, and its periphery. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 3 of this invention, and its periphery. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 4 of this invention, and its periphery. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 5 of this invention, and its periphery. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 6 of this invention, and its periphery. It is principal part sectional drawing which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 6 of this invention, and its periphery. It is a top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 6 of this invention, and its periphery. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 7 of this invention, and its periphery. FIG. 6 is a sectional view taken along line 6-6 of FIG. It is sectional drawing of the thin-film transistor element TFT in the 7-7 cutting line of FIG. FIG. 26 is a cross-sectional view of the storage capacitor Cstg taken along the line 8-8 in FIG. 25. FIG. 29A is a plan view (FIG. 29A) showing a vicinity of a connection portion between the gate terminal GTM and the gate wiring GL and its sectional view (FIG. 29B). FIG. 30A is a plan view showing the vicinity of a connection portion between the drain terminal DTM and the video signal line DL (FIG. 30A) and its sectional view (FIG. 30B). FIG. 31B is a plan view (FIG. 31A) and a cross-sectional view (FIG. 31B) showing the vicinity of a connection portion between the common electrode terminal CTM1, the common bus line CB1, and the common voltage signal line CL. FIG. 32A is a plan view (FIG. 32A) showing the vicinity of a connection portion between the common electrode terminal CTM2, the common bus line CB2, and the common voltage signal line CL, and a cross-sectional view thereof (FIG. 32B). 1 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device of the present invention. It is a figure which shows the drive waveform of the active matrix type color liquid crystal display device of this invention. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process AC of the board | substrate SUB1 side. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process D-E by the side of the board | substrate SUB1. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of the process F by the side of the board | substrate SUB1. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 8 of this invention, and its periphery. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 9 of this invention, and its periphery. It is a principal part top view which shows one pixel of the liquid crystal display part of the active matrix type color liquid crystal display device of Example 10 of this invention, and its periphery. The figure which shows the principle of this invention, The characteristic view (FIG. 41A) which shows the electric potential distribution in a liquid crystal layer when a voltage is applied to an electrode, and the top view which shows the realignment state of the liquid crystal molecule near the center part of a liquid crystal layer (FIG. 41B), a characteristic diagram showing the rotation angle α of liquid crystal molecules (FIG. 41C), and a characteristic diagram showing the transmittance distribution of light transmitted through the upper and lower polarizing plates, the upper and lower substrates, the electrodes and the liquid crystal layer between the electrodes ( FIG. 41D) is an example. It is a figure which shows the principle of this invention, and is a characteristic view which shows the state of an equipotential line at the time of applying a voltage to a transparent electrode. It is a figure which shows the principle of this invention, and is an example of the figure which shows the rotation angle (alpha) of the liquid crystal molecule in a liquid-crystal layer when the electric field which shows the state of an equipotential line when a voltage is applied to a transparent electrode is applied. It is a figure which shows the principle of this invention, and is an example of the figure which shows the tilt (rise) angle | corner of the liquid crystal molecule in a liquid crystal layer when an electric field is applied. FIG. 43 is a diagram showing the principle of improving the aperture ratio of the active matrix type color liquid crystal display device of Example 11 of the present invention, and is a characteristic diagram (FIG. 43A) showing the potential distribution in the liquid crystal layer when a voltage is applied to the electrodes; Plan view (FIG. 43B) showing the reorientation state of the liquid crystal molecules near the center of the layer, characteristic diagram showing the rotation angle α of the liquid crystal molecules (FIG. 43C), upper and lower polarizing plates, upper and lower substrates, on the electrodes and between the electrodes FIG. 43D is an example of a characteristic diagram (FIG. 43D) showing a transmittance distribution of light transmitted through the liquid crystal layer. FIG. 11 is an example of a characteristic diagram of a simulation result showing a viewing angle range in which a contrast ratio is 10 or more in all directions in a tilt angle and all directions of liquid crystal molecules in a liquid crystal layer in a horizontal electric field type liquid crystal display device.

Explanation of symbols

GL: scanning signal line, DL: video signal line, CL: counter voltage signal line, PX: pixel electrode, CT: counter electrode.

Claims (5)

In an active matrix liquid crystal display device having a pixel electrode and a counter electrode, and controlling and displaying liquid crystal molecules in a liquid crystal layer by an electric field component substantially parallel to the substrate surface between the pixel electrode and the counter electrode,
An active matrix liquid crystal display having a counter voltage signal line for electrically connecting the counter electrodes, wherein two adjacent counter voltage signal lines are connected through a through hole by the counter electrode apparatus.   2. The active matrix type liquid crystal display device according to claim 1, wherein the counter voltage signal line is made of metal.   3. The active matrix liquid crystal display device according to claim 1, wherein at least one of the pixel electrode and the counter electrode is a transparent electrode.   4. The active matrix liquid crystal display device according to claim 3, wherein the transparent conductive film of the transparent electrode is indium-tin-oxide (ITO). 3. The active matrix type according to claim 2, wherein the counter voltage signal line is formed of Cr, Ta, Ti, Mo, W, Al or an alloy thereof, or a clad structure in which they are laminated. Liquid crystal display device.

Images