JPH10186351A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a wide visual field angle comparable with a cathode-ray tube and a high-speed response capable of coping with moving picture, and to maintain satisfactory picture quality, by providing orientation control films, electrode structures, specific polarizing plates, and modulating the transmissivity of the light beam passing a liquid crystal composition with an electric field. SOLUTION: This liquid crystal display device is provided with one pair of substrates, a liquid crystal composition having positive dielectric constant anisotropy, orientation control films orienting optical axes of liquid crystal molecules being in the liquid crystal composition roughly vertically with respect to the substrates, one pair of electrode structure generating an electric field roughly parallel with surfaces of the one pair of the substrates and one pair of polarizing plates in which the angle between an electric field component parallel with the surfaces of the substrates and the light transmission axis of one side is roughly 45 degrees and the light transmission axis of other side is positioned in crossed Nicols at roughly 90 degrees with the light transmission axis of one side and then the transmissivity of the light transmitting the liquid crystal composition is modulated with the electric field. That is, the transmissivity is controlled by controlling the refractive index anisotropy of the liquid crystal layer with the impressing of a voltage. A double refraction phase difference is not generated at the time of a voltage non-impression. Since optical axes of liquid crystal molecules become parallel with the surfaces of the substrates at the time of a voltage impression, the liquid crystal layer presents the maximum refractive index anisotropy with respect to an incident light.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device used for a display device of a system which displays moving images and requires high-quality images.

[0002]

2. Description of the Related Art A liquid crystal display device is widely used as a display device of a portable device typified by a notebook computer because of its thinness and light weight. In particular, the thin film transistor element (TF
An active matrix type liquid crystal display device using an active element represented by T) has recently begun to be widely used as a monitor of a desktop personal computer and a display terminal of an OA device or the like because of its high image quality comparable to a cathode ray tube. However, liquid crystal display devices have a narrow viewing angle,
There is a specific disadvantage that the response speed is slow. As means for solving these problems, for example, a display mode called an in-plane switching mode has been proposed as a method for improving a viewing angle, and the viewing angle is drastically improved. As a method of improving the response speed, for example, there are an optically compensated bending (OCB) mode and a vertical alignment (VA) mode. Regarding these, regarding the in-plane switching mode, for example, “R. Kiefer, B. Webe
r, F.R. Windcheidand G. Baur,
Proceedings of the Twelf
the International Display
Research Conference (Japan
n Display '92) pp. 547-55
0 ”and optically compensated bending mode (OCB), for example,“ T.Uchid
a and T.A. Miyashita, Proceed
ings of The 2nd International
onlineDisplay Workshops (ID
W '95) pp. 39-42 "and the vertical alignment mode, for example, see" Nikkei Microdevice, 1996
October issue, p147 ".

[0003]

However, in the liquid crystal display device using the above-described in-plane switching mode, even if the response speed is high, the response time is less than about 100 ms, and the liquid crystal display device requires 40 to 20 ms for displaying a moving image.
The response speed is far below, and there is a problem that when displaying a moving image, an afterimage of the moving image occurs, and the image appears to flow like a comet with a tail.

On the other hand, in the optical compensated bending mode, it is extremely difficult to realize the bend alignment of the liquid crystal, and it has not been put to practical use.

In the vertical alignment mode, the viewing angle in the vertical direction is poor, so that the alignment division technique cannot be used. In order to perform the alignment division, it is necessary to perform a process of setting the pretilt of the liquid crystal molecules in two directions. In addition, it is difficult to stably maintain a pretilt state in two directions in a state of vertical alignment, and it is not possible to maintain luminance uniformity for a long time.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a wide viewing angle comparable to that of a cathode ray tube, a high-speed response capable of responding to moving images, and stable image quality for a long time. It is an object of the present invention to provide a highly reliable active matrix type liquid crystal display device which can be maintained at a high level.

[0007]

In order to achieve the above object, according to the present invention, as a first configuration, a pair of substrates and a liquid crystal having a positive dielectric anisotropy sandwiched between the pair of substrates are provided. A composition, an alignment control film capable of aligning an optical axis of liquid crystal molecules in the liquid crystal composition layer substantially perpendicular to a substrate surface when no voltage is applied, and a liquid crystal composition layer on the substrate surface of the pair of substrates. A pair of electrode structures for generating a parallel electric field, and an angle between the electric field component parallel to the substrate surface and one of the light transmission axes is about 45 °.
And the other light transmission axis has a pair of polarizing plates positioned at a crossed Nicol position at about 90 degrees with the one light transmission axis, and modulates the transmittance of light transmitted through the liquid crystal composition layer by the electric field. It is characterized by doing.

The second configuration includes the first configuration, and includes a large number of scanning lines, a large number of signal lines, and an active element formed at a substantially intersection of each of the large number of scanning lines and the large number of signal latitude lines. And a pair of electrodes capable of generating an electric field substantially parallel to the substrate surfaces of the pair of substrates.

The third structure includes the first structure, and includes a plurality of scanning wirings, a plurality of signal wirings, and a thin film transistor element formed at a substantially intersection of each of the plurality of scanning wirings and the plurality of signal latitude lines. And a pair of electrodes capable of generating an electric field substantially parallel to the substrate surfaces of the pair of substrates.

A fourth configuration includes the first configuration and has a black matrix having an insulating property by shielding unnecessary light leakage portions.

A fifth configuration includes the first configuration, wherein a transparent conductive film is provided on at least one substrate surface of the pair of substrates opposite to the holding surface of the liquid crystal composition. .

FIGS. 1 and 2 show the principle of the present invention.

FIG. 1 is a view of a cross section of a display portion of one pixel of a liquid crystal display device of the present invention, as viewed from a direction parallel to a substrate surface, and FIG. 2 is a view as viewed from a direction perpendicular to the substrate surface. is there. Note that elements such as TFTs are omitted for simplification of the description of FIGS.

As shown in FIGS. 1 (a) and 2 (a), in the present invention, the major axis (optical axis) of most of the liquid crystal molecules in the liquid crystal composition layer is perpendicular to the substrate surface when no electric field is applied. The initial state is controlled by the orientation control film (orientation film) so that the orientations are arranged in different directions. In this initial state, no birefringent phase difference occurs for the incident light.

By applying an electric field parallel to the substrate surface to the liquid crystal composition layer by a comb electrode formed on the substrate,
As shown in FIGS. 1B and 2B, the major axes of the liquid crystal molecules are arranged in a direction parallel to the substrate surface. Thereby, a birefringent phase difference is generated with respect to light passing through the liquid crystal composition, and the light is modulated. Here, due to the arrangement of the polarizing plate shown in FIG. 3, the transmittance T / T ₀ of light passing through the display of the liquid crystal display device of the present invention is:
It looks like this:

T / T ₀ = sin ² (2χ) sin ² (πΔn · d / λ) (Equation 1) where T is the output light intensity, T ₀ is the incident light intensity, and χ is the liquid crystal molecule and the optical axis. The angle between the (effective optical axis of the liquid crystal layer) and the polarization transmission axis of the polarizing plate, Δn is the refractive index anisotropy of the liquid crystal layer, λ is the wavelength of the incident light, and d is the distance between the substrates (the effective liquid crystal layer). Target thickness),
π represents pi.

Here, in the present invention, as shown in FIG. 3, when the angle χ between the polarizing plate and the liquid crystal molecules and the optical axis is 45 degrees,
Since the first term of Equation 1 is 1, the transmittance T /
T ₀ is determined.

Therefore, in the present invention, Δn of the liquid crystal layer is controlled by applying a voltage, the second term of the equation (1) is changed, the transmittance is controlled, and a desired display is obtained. Returning to FIGS. 1 and 2, when no voltage is applied, no birefringence phase difference occurs, that is, the refractive index anisotropy Δn is 0, and the transmittance is 0. At this time, even if the viewing angle direction is changed, a birefringent phase difference does not occur in a vertically oriented state as in the present invention, so that a good black level can be obtained in all viewing angle directions.

On the other hand, when a voltage is applied, the optical axis of the liquid crystal molecules is parallel to the substrate surface, and exhibits the maximum refractive index anisotropy with respect to incident light. At this time, if the product (retardation) of the refractive index anisotropy Δn of the liquid crystal and the thickness d of the liquid crystal layer is set to の of the incident light λ, the transmittance becomes maximum and a white display can be obtained.

Here, the present invention is different from the conventional vertical alignment mode in that, in the present invention, an electric force is applied to the liquid crystal composition layer by an electrode configuration for applying an electric field substantially parallel to the substrate surfaces of the pair of substrates. Since the lines are curved in a semicircle, the operation of the liquid crystal molecules is inevitably divided into two directions. Therefore, the conventional vertical alignment is used to perform the alignment division performed to expand the viewing angle characteristics of white display. Is unnecessary, and the alignment stability, which has been a problem, is improved, and high reliability for maintaining high image quality for a long time can be obtained.

Therefore, a high contrast ratio can be obtained,
In addition, a wide viewing angle characteristic can be obtained, and high reliability for maintaining high image quality can be achieved.

The second effect is that since the force (anchoring) for fixing the liquid crystal molecules at the interface between the alignment film and the liquid crystal is small, the liquid crystal molecules easily move in the liquid crystal layer, and the response speed is reduced. Extremely fast.

Further, as a third effect, in the conventional vertical alignment mode, in order to obtain a high transmittance state (white display), the optical axis of the liquid crystal molecules is moved in a direction parallel to the substrate surface. Although it is necessary to use a liquid crystal composition having a negative dielectric anisotropy (Δε <0) having a property of aligning the optical axes in the vertical direction, in the present invention, the liquid crystal composition layer is substantially parallel to the substrate surfaces of the pair of substrates. By applying a strong electric field, a high dielectric anisotropy can be obtained and a positive dielectric anisotropy (Δε>
0) (a liquid crystal having a positive dielectric anisotropy aligns the optical axis in the same direction as the electric field direction).

As a fourth action, the direction of the applied electric field determines the direction of the optical axis of the liquid crystal molecules in a plane parallel to the substrate surface. Therefore, the rubbing treatment performed in the conventional vertical alignment mode is performed. It is not necessary to control the orientation direction in the above method. Thereby, the movement of the liquid crystal molecules due to the alignment regulating force can be improved, and the response speed can be further improved.

By these actions, it is possible to solve both the high-speed response which cannot be realized in the in-plane switching mode and the wide viewing angle and high reliability which cannot be practically used in the vertical alignment mode. It is possible to realize an ideal liquid crystal display device that can surpass.

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS The invention, further objects of the invention and further features of the invention will become apparent from the following description of embodiments with reference to the drawings, in which: FIG.

<< Active matrix liquid crystal display device >>
An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

<< Planar Configuration of Matrix Section (Pixel Section) >> FIG. 4 is a plan view showing one pixel of the active matrix type color liquid crystal display device of the present invention and its periphery.

As shown in FIG. 4, each pixel has a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring) CL, and two adjacent video signal lines (drain). The signal line or the vertical signal line) is arranged in an intersecting region with the DL (in a region surrounded by four signal lines). Each pixel is a thin film transistor TFT, a storage capacitor Cst
g, the pixel electrode PX and the counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in FIG. Video signal line DL
Extend in the up-down direction and are arranged in a plurality in the left-right direction. The pixel electrode PX is electrically connected to the thin film transistor TFT via the source electrode SD1, and the counter electrode CT is also electrically connected to the counter voltage signal line CL.

The pixel electrode PX and the counter electrode CT face each other, and the optical state of the liquid crystal composition LC is controlled by an electric field generated between each pixel electrode PX and the counter electrode CT and substantially parallel to the substrate surface. Control the display. The pixel electrode PX and the counter electrode CT are formed in a comb shape, and each is an electrode that is elongated in the vertical direction in the figure.

The number O (number of comb teeth) of the counter electrodes CT in one pixel is equal to the number P (number of comb teeth) of the pixel electrode PX and O =
It is configured to have a relationship of P + 1 (in this embodiment, O
= 3, P = 2). This is because the counter electrode CT and the pixel electrode PX
Are alternately arranged, and the counter electrode CT is connected to the video signal line DL.
In order to be adjacent to. Thereby, unnecessary lines of electric force from the video signal line DL are shielded by the counter electrode CT so that the electric field between the counter electrode CT and the pixel electrode PX is not affected by the electric field generated from the video signal line DL. be able to. The counter electrode CT is different from the pixel electrode in that the potential is constantly supplied from the outside through a counter voltage signal line CL described later, so that the potential is stable, and the potential hardly changes even adjacent to the video signal line DL. . Therefore, unnecessary lines of electric force from the video signal lines DL can be shielded. Further, since the geometric position of the pixel electrode PX from the video signal line DL is far, the pixel electrode PX and the video signal line D
The parasitic capacitance during L is greatly reduced, and the fluctuation of the pixel electrode potential Vs due to the video signal voltage can be suppressed. By these,
Crosstalk (improper image quality called vertical smear) occurring in the vertical direction can be suppressed.

The electrode width of each of the pixel electrode PX and the counter electrode CT is 6 μm. In order to apply a sufficient electric field to the entire liquid crystal layer in the thickness direction of the liquid crystal layer, the thickness is set to be sufficiently larger than 3.9 μm of a liquid crystal composition layer described later. Desirably, it is set to 1.5 times or more of the liquid crystal composition layer. In addition, it is made as thin as possible to increase the aperture ratio. The video signal line DL is also 6 μm. The electrode width of the video signal line DL may be slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection. However, the electrode width of the video signal line DL is set to be equal to or less than twice the electrode width of the adjacent counter electrode CT. When the electrode width of the video signal line DL is determined from the productivity of the yield, the electrode width of the counter electrode CT adjacent to the video signal line DL is set to １ ／ or more of the electrode width of the video signal line DL. This is because the unnecessary lines of electric force generated from the video signal line DL are absorbed by the counter electrodes CT on both sides, respectively. In order to absorb the lines of electric force generated from a certain electrode width, the lines of the same width or more must be used. An electrode having an electrode width of is required. Therefore, since the lines of electric force generated from half (4 μm each) of the electrodes of the video signal lines DL need only be absorbed by the counter electrodes CT on both sides, respectively.
The electrode width of the counter electrode CT adjacent to the video signal line DL is 1 /
2 or more. This prevents crosstalk due to the influence of the video signal, and particularly prevents crosstalk in the vertical direction (vertical direction).

The width of the scanning signal line GL is set so as to satisfy a resistance value enough to transmit a scanning voltage sufficiently to the gate electrode GT of the terminal pixel (opposite to a scanning electrode terminal GTM described later). . Further, the counter voltage signal line CL also has a resistance value that allows a sufficient counter voltage to be applied to the counter electrode CT of the terminal pixel (the pixel farthest from the later-described common bus lines CB1 and CB2, that is, the pixel between CB1 and CB2). Set the electrode width to satisfy.

On the other hand, the electrode interval between the pixel electrode PX and the counter electrode CT changes depending on the liquid crystal material used. this is,
Since the electric field strength that achieves the maximum transmittance varies depending on the liquid crystal material, the electrode spacing is set according to the liquid crystal material, and within the range of the maximum amplitude of the signal voltage set by the withstand voltage of the video signal driving circuit (signal side driver) used. , So that the maximum transmittance can be obtained. When a liquid crystal material described later is used, the electrode interval is 16 μm.

<< Cross-Sectional Structure of Matrix (Pixel) >> FIG. 5 is a cross-sectional view taken along the line 6-6 in FIG. 4, and FIG. 6 is a cross-sectional view of the thin film transistor TFT taken along the line 7-7 in FIG. 7 is the storage capacitance C at the 8-8 section line in FIG.
It is a figure showing the section of stg. As shown in FIGS.
The lower transparent glass substrate SU based on the liquid crystal composition layer LC
A thin film transistor TFT, a storage capacitor Cstg, and an electrode group are formed on the B1 side, and a color filter FIL and a light shielding black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side.

Further, the transparent glass substrates SUB1, SUB2
Alignment films AF1 and AF2 for controlling the initial alignment of the liquid crystal are provided on the inner surface (on the liquid crystal LC side) of each of the above, and a polarizing plate is provided on each outer surface of the transparent glass substrates SUB1 and SUB2. Is provided.

<< TFT Substrate >> First, the structure of the lower transparent glass substrate SUB1 (TFT substrate) will be described in detail.

<< Thin Film Transistor TFT >> The thin film transistor TFT operates so that the channel resistance between the source and the drain decreases when a positive bias is applied to the gate electrode GT, and the channel resistance increases when the bias is zero.

As shown in FIG. 6, the thin film transistor TFT has a gate electrode GT, an insulating film GI, an i-type (intrinsic, intr
It has an insic, i-type semiconductor layer AS made of amorphous silicon (Si not doped with a conductivity type determining impurity), a pair of source electrode SD1, and a drain electrode SD2. In addition,
It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are switched during the operation. However, in the following description, one is fixed and the other is fixed as a drain for convenience.

<< Gate Electrode GT >> The gate electrode GT is formed continuously with the scanning signal line GL.
Is configured to be a gate electrode GT. The gate electrode GT is a portion beyond the active area of the thin film transistor TFT. In this example, the gate electrode GT
Is formed of a single-layer conductive film g3. As the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used, but not limited thereto.

<< Scanning Signal Line GL >> The scanning signal line GL is formed of a conductive film g3. The conductive film g3 of the scanning signal line GL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, and is integrally formed. This scanning signal line G
By L, a gate voltage (scanning voltage) Vg is supplied from an external circuit to the gate electrode GT. In this example, as the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used. Also, the scanning signal line G
The L and the gate electrode GT are not limited to the chromium-molybdenum alloy, but may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum for low resistance.

Further, the portion that intersects with the video signal line DL is made thinner to reduce the probability of short-circuit with the video signal line DL, and is made bifurcated so that even if it is short-circuited, it can be separated by laser trimming. good.

<< Counter Voltage Signal Line CL >> Counter Voltage Signal Line C
L is composed of a conductive film g3. The conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, the scanning signal line GL, and the counter electrode CT, and is configured to be electrically connected to the counter electrode CT. I have. The counter voltage Vcom is supplied from the external circuit to the counter electrode CT through the counter voltage signal line CL. Further, the counter voltage signal line CL is not limited to the chromium-molybdenum alloy, but may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum for lowering the resistance. Further, the portion that intersects with the video signal line DL may be narrowed in order to reduce the probability of a short circuit with the video signal line DL, or may be bifurcated so that even if a short circuit occurs, it can be separated by laser trimming.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI includes the gate electrode GT and the scanning signal line GL.
Is formed in the upper layer. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected.
000-4500 mm (in this embodiment, 3500
Å) formed. Further, the insulating film GI is provided with the scanning signal line G.
It also functions as an interlayer insulating film between the L and counter voltage signal lines CL and the video signal lines DL, and contributes to their electrical insulation.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
Is amorphous silicon and is formed to a thickness of 150 to 2500 ° (about 1200 ° in this embodiment). The layer d0 is an N (+)-type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, and is provided only in a region where the i-type semiconductor layer AS is present on the lower side and the conductive layer d3 is present on the upper side. Has been left.

The i-type semiconductor layer AS and the layer d0 are also provided between the scanning signal line GL and the intersection (crossover portion) between the counter voltage signal line CL and the video signal line DL. The i-type semiconductor layer AS at the intersection is provided with the scanning signal line GL, the counter voltage signal line CL, and the video signal line D at the intersection.
Short circuit with L is reduced.

<< Source electrode SD1, Drain electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is formed of a conductive film d3 which is in contact with the N (+) type semiconductor layer d0.

The conductive film d3 is made of chromium-
Using a molybdenum alloy (Cr-Mo) film,
It is formed to a thickness of 00 ° (about 2500 ° in this embodiment). Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, a high melting point metal (Mo, Ti, Ta, W) film, a high melting point metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , W) in addition to the Cr—Mo film.
An Si ₂ ) film may be used, or a laminated structure with aluminum or the like may be used.

<< Video Signal Line DL >> The video signal line DL is a conductive film d3 of the same layer as the source electrode SD1 and the drain electrode SD2.
It is composed of The video signal line DL is formed integrally with the drain electrode SD2. In this example, the conductive film d
3 is a chromium-molybdenum alloy (Cr
-Mo) The film is formed to a thickness of 500 to 3000 ° (about 2500 ° in this embodiment) using a film. Cr-Mo
Since the film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, a refractory metal (Mo,
Ti, Ta, W) film, refractory metal silicide (MoSi)
₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film or a laminated structure with aluminum or the like.

<< Storage Capacitor Cstg >> The conductive film d3 is formed so as to overlap the counter voltage signal line CL in the source electrode SD2 of the thin film transistor TFT. This superposition constitutes a storage capacitor (capacitance element) Cstg in which the source electrode SD2 (d3) is used as one electrode and the counter voltage signal CL is used as the other electrode, as is clear from FIG. The dielectric film of the storage capacitor Cstg is an insulating film G used as a gate insulating film of the thin film transistor TFT.
I.

As shown in FIG. 4, the storage capacitance Cst
g is formed in a part of the counter voltage signal line CL.

<< Protective Film PSV1 >> Thin Film Transistor TF
On T, a protective film PSV1 is provided. Protective film PS
V1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a material having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of about 0.1 to 1 μm.

The protective film PSV1 is connected to an external connection terminal DTM,
Removed to expose GTM. Protective film PSV1
And the thickness of the insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner in the transconductance gm of the transistor.

In the pixel portion, through holes TH2 and TH1 are provided for electrical connection between the counter voltage signal line CL and a counter electrode CT described later and for electrical connection between the source electrode SD2 and the pixel electrode PX. Provided. In the through hole TH2, since the protective film PSV1 and the insulating film GI are processed at a time, a hole up to the g3 layer is formed, and the through hole TH2 is formed.
In the case of 1, since blocking is performed at d3, holes are formed up to the d3 layer.

The protective film PSV1 may have a laminated structure with a thick organic film such as polyimide.

<< Pixel Electrode PX >> The pixel electrode PX is formed of the transparent conductive layer i1. This transparent conductive film i1 is a transparent conductive film (Indium-Tin-Oxide) formed by sputtering.
It is made of ITO (a Nesa film) and is formed to a thickness of 100 to 2000 （(in this embodiment, about 1400 、 １). The pixel electrode PX is connected to the source electrode SD2 via the through hole TH1.

When the pixel electrode is transparent as in the present embodiment, the maximum transmittance in white display is improved by the transmitted light in that portion, so that the pixel electrode is brighter than when the pixel electrode is opaque. Display can be performed. At this time, as described later, when no voltage is applied, the liquid crystal molecules maintain the initial alignment state, and the polarizing plate is arranged so as to perform black display in that state (normally black mode). Therefore, even if the pixel electrode is made transparent, it is possible to display high-quality black without transmitting light in that portion. Thereby, the maximum transmittance can be improved and a sufficient contrast ratio can be achieved.

<< Counter Electrode CT >> The counter electrode CT is formed of the transparent conductive layer i1. This transparent conductive film i1 is a transparent conductive film (Indium-Tin-Oxide) formed by sputtering.
It is made of ITO (a Nesa film) and is formed to a thickness of 100 to 2000 （(in this embodiment, about 1400 、 １). The counter electrode CT is connected to the counter voltage signal line CL via the through hole TH2. Pixel electrode P
Similarly to X, by making the opposing electrode transparent, the maximum transmittance when white display is performed is improved.

The counter electrode CT is configured to apply a counter voltage Vcom. In this embodiment, the counter voltage V
com is a potential lower than the intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL by a feedthrough voltage ΔVs generated when the thin film transistor element TFT is turned off. However, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal driving circuit to about half, an AC voltage may be applied.

<< Color Filter Substrate >> Next, FIGS.
Returning to, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail. << Light-Shielding Film BM >> On the upper transparent glass substrate SUB2 side, transmitted light from an unnecessary gap (a gap other than between the pixel electrode PX and the counter electrode CT) is emitted to the display surface side to lower the contrast ratio and the like. A light-shielding film BM (a so-called black matrix) is formed so as not to cause the light-blocking. The light-shielding film BM also plays a role of preventing external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is formed by the upper and lower light shielding films B.
Sandwiched by the M and large gate electrodes GT prevents external natural light and backlight light from shining.

The light shielding film BM shown in FIG. 4 has a configuration extending linearly in the left-right direction above the thin film transistor element TFT. This pattern is merely an example, and the pattern may be a matrix with openings formed in holes. In a portion where the direction of the electric field is disturbed, such as a comb-teeth electrode end, the display of the portion corresponds to the video information in the pixel on a one-to-one basis, and is black in black and white in white. Therefore, it can be used as a part of the display. In addition, the gap between the counter electrode CT and the video signal line DL in the vertical direction in the drawing is shielded from light by the second light shielding layer SH formed in the same step as the gate electrode GT. As a result, light shielding in the vertical direction in the horizontal direction
Since the light can be shielded with high precision by the alignment accuracy of the process, the boundary of the second light shielding layer SH can be set between the electrodes of the counter electrode CT adjacent to the video signal line DL, and the light is shielded by the light shielding film BM depending on the alignment accuracy of the upper and lower substrates. The opening can be enlarged more than that.

Further, the light shielding film BM can be formed on the thin film transistor substrate SUB1. Thereby, the second
Like the light-shielding layer SH, the opening can be further enlarged as compared with the light-shielding by the light-shielding film BM on the substrate SUB2 which depends on the alignment accuracy of the upper and lower substrates.

However, the light-shielding film BM has a light-shielding property and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT.
In this embodiment, a black organic pigment is mixed into the resist material,
It is formed with a thickness of about 1.2 μm. Further, in order to improve the light shielding property, carbon, titanium oxide (T
The i x _{O y),} insulation within the range that can maintain a more 108Ωcm which does not affect the electric field of the liquid crystal composition layer may be mixed. Further, it is preferable that the second light-shielding layer SH has conductivity so as to easily absorb electric power from the video signal line.

The light-shielding film BM is linearly formed in the pixels in each row in the left-right direction, and the lines partition the effective display area of each row. Therefore, the outline of the pixels in each row is made clear by the light shielding film BM. That is, the light-shielding film BM has two functions of black matrix and light-shielding for the i-type semiconductor layer AS.

The light-shielding film BM is also formed in a peripheral part in a frame shape, and its pattern is formed continuously with the pattern of the matrix part shown in FIG. The light-shielding film BM at the peripheral portion is extended outside the seal portion SL to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion, and light from the backlight or the like to the display area. It also prevents it from leaking outside. On the other hand, this light shielding film BM is
It is held about 0.3 to 1.0 mm inside the edge of B2, and is formed avoiding the cutting area of the substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed in a stripe shape by repeating red, green, and blue at a position facing the pixel. The color filter FIL is formed so as to overlap the edge portion of the double light-shielding film SH.

The color filter FIL can be formed as follows. First, a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red pigment and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process. Note that a dye may be used for dyeing.

<< Overcoat Film OC >> The overcoat film OC is a liquid crystal composition layer L of a dye of a color filter FIL.
C is provided to prevent leakage to C and to flatten a step due to the color filter FIL and the light shielding film BM.
The overcoat film OC is formed of a transparent resin material such as an acrylic resin and an epoxy resin. Further, as the overcoat film C, an organic film such as polyimide having good fluidity may be used.

<< Liquid Crystal Layer and Polarizing Plate >> Next, the liquid crystal layer, the alignment film, the polarizing plate and the like will be described.

<< Liquid Crystal Layer >> The liquid crystal composition LC has a positive dielectric anisotropy Δε of 13.2 and a refractive index anisotropy Δε of 13.2.
A nematic liquid crystal in which n is 0.081 (589 nm, 20 ° C.) is used. The thickness (gap) of the liquid crystal composition layer is
3.8 μm, retardation Δn · d is 0.31 μm
m. The value of the retardation Δn · d is 0.2
Between 5 μm or more and 0.35 μm, preferably 0.2
When set between 8 μm or more and 0.32 μm, the maximum transmittance can be obtained when the optical axes of the liquid crystal molecules are arranged in the direction of the electric field by combining with a polarizing plate described later. So that it is possible to obtain transmitted light with almost no light.

The thickness (gap) of the liquid crystal composition layer
Is controlled by polymer beads subjected to a vertical alignment treatment. This stabilizes the alignment of liquid crystal molecules around the beads during black display, obtains a good black level, and improves the contrast ratio.

The liquid crystal material LC is not particularly limited. The larger the value of the dielectric anisotropy Δε, the lower the driving voltage can be. The smaller the dielectric anisotropy Δn, the smaller the dielectric anisotropy Δn. The thickness (gap) can be increased, the liquid crystal sealing time can be shortened, and the gap variation can be reduced.

The specific resistance of the liquid crystal composition is 10
⁹ [Omega] cm or more ^{10 1 4} [Omega] cm or less, preferably ^{10 1 1}
[Omega] cm or more ^{10 1 3} [Omega] cm using the following things. In this method, even at low resistance of the liquid crystal composition, the voltage charged between the pixel electrode and the counter electrode can be sufficiently held, the lower limit of 10 ⁹ [Omega] cm, preferably 10 ^{1 1} [Omega] cm. This is because the pixel electrode and the counter electrode are formed on the same substrate. Further, when the resistance is too high, the hard alleviate static electricity entering the production process, 10 ^{1 4} .omega.c
m or less, preferably ^{10 1 3} [Omega] cm or less.

<< Orientation Film >> As the orientation film AF, polyimide (JALS203) manufactured by Japan Synthetic Rubber Co., Ltd. is used. This alignment film has a hydrophobic group (for example, CH3) on the surface, and the major axis (optical axis) of the liquid crystal molecules is arranged in a direction perpendicular to the substrate surface. Thereby, a good black level is displayed by a combination with a polarizing plate described later when no electric field is applied. In the present invention, no rubbing treatment is performed. For this reason,
It is possible to eliminate defects such as a decrease in contrast ratio due to the occurrence of a defective display area due to the formation of a non-rubbed portion related to the rubbing process, and the occurrence of unevenness due to a variation in the rubbing angle.

<< Polarizing Plate >> A polarizing plate having conductivity is used as the polarizing plate POL, and the polarization transmission axis MAX1 of the lower polarizing plate POL1 is set in the electric field application direction (the direction orthogonal to the longitudinal direction of the comb electrode). The angle is set to about 45 degrees, and the polarization transmission axis MAX2 of the upper deflecting plate POL2 is perpendicular to it. FIG. 3 shows the relationship. As a result, a display as shown in the operation can be performed, and a normally closed characteristic in which the transmittance increases as the applied voltage (the voltage between the pixel electrode PX and the counter electrode CT) increases is obtained. be able to.

In the present embodiment, by providing the polarizing plate with conductivity, measures against display failure and EMI due to external static electricity are taken. Regarding the conductivity, the sheet resistance is desirably set to 10 ⁸ Ω / b or less if only to take measures against the influence of static electricity, and is set to 10 ⁴ Ω / b or less if EMI is also taken. Further, a conductive layer may be provided on the back surface (the surface on which the polarizing plate is adhered) of the sandwiching surface of the liquid crystal composition of the glass substrate.

<< Structure around the Matrix >> FIG. 8 is a diagram showing a main part plane around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2. FIG. 9 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

[0078] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared A glass substrate of a standardized size is processed even in a variety, and the size is reduced to a size suitable for each type. In each case, the glass is cut after passing through one process. 8 and 9 show an example of the latter. Both FIGS. 8 and 9 show the upper and lower substrates SUB1 and SUB.
2 shows the state after cutting, and LN indicates the edge of both substrates before cutting. In any case, in the completed state, the external connection terminal group T
The size of the upper substrate SUB2 is limited to the inside of the lower substrate SUB1 so that g, Td, and the terminal COT (subscripts omitted) (the upper side and the left side in the figure) are exposed so that they are exposed. The terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM described later.
A tape carrier package TCP on which an integrated circuit chip CHI is mounted (see FIGS. 19 and 2)
A plurality of units are collectively named in the unit of 0). The lead wiring from the matrix section of each group to the external connection terminal section is inclined as approaching both ends. This is because the terminals DTM of the display panel PNL are arranged at the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP.
This is for matching GTM. Also, the counter electrode terminal CO
T is a terminal for applying a counter voltage to the counter electrode CT from an external circuit. Counter voltage signal line CL in matrix section
Are drawn out on the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the common voltage signal lines are grouped together by a common bus line CB and connected to the common electrode terminal COT.

Along the edge between the transparent glass substrates SUB1 and SUB2, except for the liquid crystal filling opening INJ, the liquid crystal LC
The seal pattern SL is formed so as to seal.
The sealing material is made of, for example, an epoxy resin.

The layers of the alignment films ORI1 and ORI2 are formed inside the seal pattern SL. Polarizing plates POL1, P
OL2 is formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
The liquid crystal LC is a lower alignment film ORI for setting the direction of liquid crystal molecules.
1 and the upper alignment film ORI2 are sealed in a region partitioned by a seal pattern SL. Lower alignment film ORI1
Is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and the seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are sealed. Assembled by cutting.

<< Gate Terminal Portion >> FIGS. 10A and 10B are diagrams showing a connection structure from the scanning signal line GL of the display matrix to the external connection terminal GTM, where FIG. 10A is a plane view and FIG. 10B is a view B of FIG. 4 shows a cross section taken along section line -B. This figure corresponds to the vicinity of the lower part of FIG. 8, and the diagonal wiring portion is represented by a straight line for convenience.

In the figure, the Cr—Mo layer g3 is hatched for easy understanding.

The gate terminal GTM includes a Cr—Mo layer g3,
Further, the surface is protected and TCP (Tape Ca
(rear package) and a transparent conductive layer i1 for improving the reliability of connection. This transparent conductive layer i1 uses a transparent conductive film ITO formed in the same step as the pixel electrode PX.

In the plan view, the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located on the left end is exposed therefrom so that electrical contact with an external circuit can be made. Has become. In the figure, only one pair of the gate line GL and the gate terminal is shown. However, in practice, a plurality of such pairs are arranged vertically as shown in FIG. 8 to form a terminal group Tg (FIG. 8). In the manufacturing process, the left end of the gate terminal extends beyond the cutting region of the substrate and is short-circuited by a wiring SHg (not shown). This is useful for preventing electrostatic breakdown at the time of rubbing of the alignment film ORI1 in the manufacturing process.

<< Drain Terminal DTM >> FIGS. 11A and 11B are diagrams showing the connection from the video signal line DL to the external connection terminal DTM. FIG. 11A shows the plane, and FIG.
4 shows a cross section taken along section line -B. 8 corresponds to the vicinity of the upper right of FIG. 8 and the direction of the drawing is changed for convenience, but the right end direction corresponds to the upper end of the substrate SUB1.

TSTd is an inspection terminal to which an external circuit is not connected, but is wider than a wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal D
The TM is also wider than the wiring part so that it can be connected to an external circuit. The external connection drain terminals DTM are arranged in the vertical direction, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and are further extended beyond the cutting line of the substrate SUB1. All of them are short-circuited to each other by a wiring SHd (not shown) to prevent electrostatic breakdown. The inspection terminal TSTd is formed on every other video signal line DL as shown in FIG.

The drain connection terminal DTM is connected to the transparent conductive layer i1.
The portion where the protective film PSV1 is removed is connected to the video signal line DL. This transparent conductive film i1 uses a transparent conductive film ITO formed in the same step as the pixel electrode PX, as in the case of the gate terminal GTM.

The lead wiring from the matrix part to the drain terminal part DTM is connected to the layer d3 of the same level as the video signal line DL.
Is configured.

<< Counter Electrode Terminal CTM >> FIGS. 12A and 12B are diagrams showing the connection from the counter voltage signal line CL to the external connection terminal CTM. FIG. 12A shows the plane, and FIG. 12B shows the plane.
2 shows a cross section taken along line BB of FIG. FIG. 8 shows FIG.
Corresponds to near the upper left.

Each counter voltage signal line CL is connected to a common bus line C
B1 collectively leads to the counter electrode terminal CTM. The common bus line CB has a structure in which the conductive layer 3 is stacked on the conductive layer g3, and they are electrically connected by the transparent conductive layer i1. This reduces the resistance of the common bus line CB, and the opposing voltage is supplied from an external circuit to each opposing voltage signal line CL.
In order to be supplied sufficiently. This structure is characterized in that the resistance of the common bus line can be reduced without particularly adding a new conductive layer.

The counter electrode terminal CTM has a structure in which a transparent conductive layer i1 is laminated on a conductive layer g3. This transparent conductive film i1 uses a transparent conductive film ITO formed in the same step as the pixel electrode PX, as in the case of the other terminals. The conductive layer g3 is covered with the transparent conductive layer i1 having good durability in order to protect the surface with the transparent conductive layer i1 and prevent electrolytic corrosion and the like. The connection between the transparent conductive layer i1 and the conductive layers g3 and d3 is made conductive by forming through holes in the protective film PSV1 and the insulating film GI.

On the other hand, FIG. 13 is a diagram showing the connection from the other end of the counter voltage signal line CL to its external connection terminal CTM2, (A) showing its plane, and (B) showing (A).
2 shows a cross section taken along line BB of FIG. Note that FIG.
Corresponds to near the upper right. Here, in the common bus line CB2, the other end of each counter voltage signal line CL (gate terminal G)
(TM side) are led together to the counter electrode terminal CTM2. The difference from the common bus line CB1 is that the common bus line CB1 is formed of a conductive layer d3 and a transparent conductive layer i1 so as to be insulated from the scanning signal line GL. Further, insulation with the scanning signal line GL is performed by the insulating film GI.

<< Equivalent Circuit of Entire Display Device >> FIG. 14 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X indicates a video signal line DL, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively. Y means the scanning signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.

The SUP uses a TFT liquid crystal display device to output information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a plurality of divided and stabilized voltage sources from one voltage source. This is a circuit that includes a circuit that exchanges information for use.

<< Driving Method >> FIG. 15 shows a driving waveform of the liquid crystal display device of this embodiment. The counter voltage Vc is a constant voltage. The scanning signal Vg takes the on level every scanning period, and takes the off level in the others. The video signal voltage is applied so that the positive and negative polarities are inverted every frame and transmitted to one pixel with twice the amplitude of the voltage to be applied to the liquid crystal layer.
Here, the polarity of the video signal voltage Vd is inverted for each column,
The polarity is also inverted for each row. As a result, pixels having inverted polarities are arranged vertically and horizontally, so that flicker and crosstalk (smear) can be suppressed. In addition, the counter voltage Vc is set to a voltage that is reduced by a fixed amount from the center voltage of the polarity inversion of the video signal voltage. This is to correct the feedthrough voltage generated when the thin film transistor element changes from on to off,
This is performed to apply an AC voltage having a small DC component to the liquid crystal. When a direct current is applied to the liquid crystal, afterimages, deterioration, and the like become severe.

Besides, the maximum amplitude of the video signal voltage can be reduced by converting the counter voltage into an alternating current, and a video signal driving circuit (signal side driver) having a low withstand voltage can be used.

<< Function of Storage Capacitance Cstg >> Storage Capacitance Cstg
Is provided in order to accumulate video information (after the thin film transistor TFT is turned off) written in the pixel for a long time.
In the method of applying an electric field parallel to the substrate surface used in the present invention, unlike the method of applying the electric field perpendicular to the substrate surface, there is almost no capacitance (so-called liquid crystal capacitance) formed by the pixel electrode and the counter electrode. However, the storage capacity Cstg cannot store video information in the pixel. Therefore, in a system in which an electric field is applied in parallel with the substrate surface, the storage capacitor Cstg is an essential component.

The storage capacitor Cstg also works to reduce the effect of the gate potential change ΔVg on the pixel electrode potential Vs when the thin film transistor TFT switches. This situation is represented by the following equation.

ΔVs = {Cgs / (Cgs + Cstg + Cpix)} × ΔVg where Cgs is the gate electrode G of the thin film transistor TFT.
Parasitic capacitance formed between T and the source electrode SD1, C
pix represents a capacitance formed between the pixel electrode PX and the counter electrode CT, and ΔVs represents a so-called feed-through voltage corresponding to a change in pixel electrode potential due to ΔVg. This change ΔVs causes a DC component applied to the liquid crystal LC, but the storage capacitance Cst
The larger the value of g, the smaller the value. The reduction of the DC component applied to the liquid crystal LC
The life of C can be improved, and so-called burn-in in which the previous image remains when the liquid crystal display screen is switched can be reduced.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. The pixel electrode potential Vs is susceptible to the gate (scanning) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cstg.

<< Manufacturing Method >> Next, a method of manufacturing the liquid crystal display device on the substrate SUB1 side will be described with reference to FIGS.
This will be described with reference to FIG. In the same figure, the letters at the center are abbreviations of the process names, and the left side shows the processing flow as viewed from the cross-sectional shape near the gate terminal shown in FIG. Except for Step B and Step D, Step A to Step I are classified according to each photographic process, and any cross-sectional view of each process shows a stage where the processing after the photographic process is completed and the photoresist is removed. . In the present description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 16 On a lower transparent glass substrate SUB1 made of AN635 glass (trade name), a conductive film g3 made of Cr—Mo or the like having a thickness of 2000 ° is provided by sputtering. After the photographic processing, the conductive film g3 is selectively etched with ceric ammonium nitrate. Thereby, the gate electrode GT, the scanning signal line GL, the counter voltage signal line CL, the gate terminal GTM,
First conductive layer of common bus line CB1, counter electrode terminal CT
A bus line SHg (not shown) connecting the first conductive layer of M1 and the gate terminal GTM is formed.

Step B, FIG. 16 An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to provide a Si nitride film having a thickness of 3500 °, and a silane gas and a hydrogen gas are introduced into the plasma CVD apparatus. After providing an i-type amorphous Si film having a thickness of 1200 °, a hydrogen gas and a phosphine gas are introduced into a plasma CVD apparatus to form an N (+)-type amorphous Si film having a thickness of 300 °.

Step C, FIG. 16 After photographic processing, SF6 and CC were used as dry etching gases.
N @ + type amorphous Si film using i @ 4, i type amorphous Si
By selectively etching the film, islands of the i-type semiconductor layer AS are formed.

Step D, FIG. 17 A conductive film d3 made of Cr having a thickness of 300 ° is provided by sputtering. After the photographic processing, the conductive film d3 is etched with the same liquid as in step A, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the first conductive layer of the common bus line CB2, and the bus line for short-circuiting the drain terminal DTM. SHd (not shown) is formed. Next, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed by introducing CCl4 and SF6 into the dry etching apparatus and etching the N (+) type amorphous Si film. .
After patterning the conductive film d3 with a mask pattern, the N (+) type semiconductor layer d0 is removed using the conductive film d3 as a mask. That is, the N remaining on the i-type semiconductor layer AS
In the (+) type semiconductor layer d0, portions other than the conductive films d1 and d2 are removed by self-alignment. At this time, since the N (+)-type semiconductor layer d0 is etched so as to entirely remove the thickness thereof, the surface of the i-type semiconductor layer AS is also slightly etched, but the degree is controlled by the etching time. do it.

Step E, FIG. 17 An ammonia gas, a silane gas, and a nitrogen gas are introduced into the plasma CVD apparatus to form a 0.4 μm-thick Si nitride film. After photo processing, SF6 is used as dry etching gas.
Then, the protective film PSV1 and the insulating film GI are patterned by selectively etching the Si nitride film using the method described above. Here, the protective film PSV1 and the insulating film GI are patterned with the same photomask and are processed collectively.

Step F, FIG. 18 A transparent conductive film i1 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photographic processing, the transparent conductive film i1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the counter electrode terminal CTM1.
And a second conductive layer of CTM2 is formed.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 19 is a top view showing a state where the video signal driving circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG. 8 and the like.

CHI is a driving IC chip for driving the display panel PNL (the lower five are driving ICs on the vertical scanning circuit side)
The left and right chips are the driving I on the video signal driving circuit side.
C chip). TCP is a tape carrier package in which a driving IC chip CHI is mounted by a tape automated bonding method (TAB), as will be described later with reference to FIGS. 16 and 17, and PCB1 is a driving circuit in which the above-described TCP, capacitors and the like are mounted. The substrate is divided into two, one for a video signal drive circuit and one for a scan signal drive circuit. FG
P is a frame ground pad, and a shield case S
A spring-shaped fragment provided by cutting into the HD is soldered. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1. As shown in the drawing, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material plated with Sn) are sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer.

<< Connection Structure of TCP >> FIG. 20 is a diagram showing a cross-sectional structure of a tape carrier package TCP constituting the scanning signal drive circuit V and the video signal drive circuit H and having the integrated circuit chip CHI mounted on a flexible wiring board. Yes,
FIG. 21 is a cross-sectional view of a main part of the liquid crystal display panel, showing a state where it is connected to a scanning signal circuit terminal GTM in this example.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu. ) Is the integrated circuit C
The HI bonding pads PAD are connected by a so-called face-down bonding method. Terminal TTB, T
The outer ends (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
CRT / TFT conversion circuit / power supply circuit S by soldering
A liquid crystal display panel P is formed on the UP by using an anisotropic conductive film ACF.
NL. The package TCP has a protective film PS whose leading end exposes the connection terminal GTM on the panel PNL side.
Since the external connection terminal GTM (DTM) is covered with at least one of the protection film PSV1 and the package TCP, the external connection terminal GTM (DTM) is covered with the panel so as to cover V1.

Reference numeral BF1 denotes a base film made of polyimide or the like, and SRS denotes a solder resist film for masking so that solder does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by an epoxy resin EPX or the like, and the space between the package TCP and the upper substrate SUB2 is further filled with a silicone resin SIL to multiplex protection.

<< Drive Circuit Board PCB2 >> Drive Circuit Board P
The CB2 has electronic components such as an IC, a capacitor, and a resistor mounted thereon. The drive circuit board PCB2 includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CR (Crystal Control Unit) from a host (upper processing unit).
A circuit SUP including a circuit for converting information for T (cathode ray tube) into information for a TFT liquid crystal display device is mounted. C
J is a connector connection portion to which a connector (not shown) connected to the outside is connected.

Driving circuit board PCB1 and driving circuit board PC
B2 is electrically connected by a flat cable FC.

<< Overall Configuration of Liquid Crystal Display Module >> FIG.
FIG. 3 is an exploded perspective view showing each component of the liquid crystal display module MDL.

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW and its display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide,
RM is a reflection plate, BL is a backlight fluorescent tube, LCA is a backlight case, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble a module MDL.

The module MDL is a shield case SH
The entirety is fixed by claws and hooks provided on D.

The backlight case LCA includes a backlight fluorescent tube BL, a light diffusion plate SPB, a light diffusion plate, a light guide LCB,
The light guide LCB has a shape to accommodate the reflection plate RM.
The light of the backlight fluorescent tube BL arranged on the side surface is made uniform on the display surface by the light guide LCB, the reflection plate RM, and the light diffusion plate SPB, and emitted to the liquid crystal display panel PNL side.

An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL, and serves as a power supply for the backlight fluorescent tube BL.

[0123]

As described in detail above, according to the present invention,
It is possible to obtain a liquid crystal display device that achieves a high contrast ratio, a wide viewing angle characteristic, and a high reliability that can maintain high image quality.

At the same time, it is possible to obtain a liquid crystal display device which has a very high response speed and can be driven at a low voltage.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the principle of the present invention.

FIG. 2 is a plan view showing the principle of the present invention.

FIG. 3 is a diagram showing the relationship between the direction of an applied electric field and the transmission axis of a polarizing plate according to the present invention.

FIG. 4 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix type color liquid crystal display device according to an embodiment of the present invention.

FIG. 5 is a sectional view of a pixel taken along section line 6-6 in FIG. 4;

FIG. 6 is a cross-sectional view of the thin film transistor element TFT taken along section line 7-7 in FIG.

FIG. 7 is a cross-sectional view of the storage capacitor Cstg taken along section line 8-8 in FIG. 4;

FIG. 8 is a plan view for explaining a configuration of a matrix peripheral portion of the display panel.

FIG. 9 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 10 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 11 is a plan view and a sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 12 shows a common electrode terminal CTM1 and a common bus line CB.
FIG. 2 is a plan view and a cross-sectional view showing the vicinity of a connection portion between the first and common voltage signal lines CL.

FIG. 13 shows a common electrode terminal CTM2 and a common bus line CB.
2A and 2B are a plan view and a cross-sectional view showing the vicinity of a connection portion between the second and common voltage signal lines CL.

FIG. 14 is a circuit diagram including a matrix portion and its periphery of the active matrix type color liquid crystal display device of the present invention.

FIG. 15 is a diagram showing driving waveforms of the active matrix type color liquid crystal display device of the present invention.

FIG. 16 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 17 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes D to F on the substrate SUB1 side.

FIG. 18 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes G to H on the substrate SUB1 side.

FIG. 19 is a top view showing a state where peripheral driving circuits are mounted on a liquid crystal display panel.

FIG. 20 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.

FIG. 21 is a cross-sectional view of a main part showing a state where the tape carrier package TCP is connected to a scanning signal circuit terminal GTM of the liquid crystal display panel PNL.

FIG. 22 is an exploded perspective view of the liquid crystal display module.

[Explanation of symbols]

SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line, CL: counter voltage signal line, PX: pixel electrode, C
T: counter electrode, GI: insulating film, GT: gate electrode, AS
... i-type semiconductor layer, SD: source or drain electrode, PSV: protective film, BM: light shielding film, LC: liquid crystal, TF
T: thin film transistor, PH: through hole, g, d ...
Conductive film, Cstg: storage capacitance, AOF: anodic oxide film, AO
... anodization mask, GTM ... gate terminal, DTM ... drain terminal, CB ... common bus line, DTM ... common electrode terminal, SHD ... shield case, PNL ... liquid crystal display panel, SPB ... light diffusion plate, LCB ... light guide, BL: Backlight fluorescent tube; LCA: Backlight case; RM: Reflector (abbreviated above).

Claims (5)

[Claims] 1. A pair of substrates, a liquid crystal composition having a positive dielectric anisotropy sandwiched between the pair of substrates, and an optical axis of liquid crystal molecules in the liquid crystal composition layer when no voltage is applied. An alignment control film that can be oriented substantially perpendicular to the surface, a pair of electrode structures that generate an electric field in the liquid crystal composition layer that is substantially parallel to the substrate surfaces of the pair of substrates, and one of an electric field component parallel to the substrate surface. And a pair of polarizers, the angle of which is about 45 degrees with respect to the light transmission axis, and the other light transmission axis is crossed at about 90 degrees with one of the light transmission axes. A liquid crystal display device which modulates the transmittance of light transmitted through a composition layer. A plurality of scanning lines, a plurality of signal lines, an active element formed at a substantially intersection of each of the plurality of scanning lines and the plurality of signal latitude lines, and a plurality of active lines formed on a substrate surface of the pair of substrates. 2. The liquid crystal display device according to claim 1, comprising a pair of electrodes capable of generating a parallel electric field. 3. A plurality of scanning wirings, a plurality of signal wirings, a thin film transistor element formed at a substantially intersection of each of the plurality of scanning wirings and the plurality of signal latitude lines, and a plurality of thin film transistors formed substantially on the substrate surfaces of the pair of substrates. 2. The liquid crystal display device according to claim 1, comprising a pair of electrodes capable of generating a parallel electric field. 4. A black matrix having an insulating property by shielding unnecessary light leakage portions.
The liquid crystal display device as described in the above. 5. The liquid crystal display device according to claim 1, wherein a transparent conductive film is provided on at least one substrate surface of the pair of substrates opposite to the holding surface of the liquid crystal composition.