JP3340894B2 - Active matrix type liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, the present invention relates to a technique which is effective when applied to an active matrix type liquid crystal display device of a horizontal electric field system.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device using an active element represented by a thin film transistor (TFT) is widely used as a display terminal device for OA equipment and the like because of its thinness and light weight and high image quality comparable to a cathode ray tube. It is beginning to spread.

The following two display methods are known as display methods of the active matrix type liquid crystal display device.

One is to enclose a liquid crystal layer between a pair of substrates on which two transparent electrodes are formed, and to apply a driving voltage to the two transparent electrodes, so that an electric field in a direction substantially perpendicular to the interface between the substrates is used. This is a method of driving the layer and modulating the light transmitted through the transparent electrode and entering the liquid crystal layer for display (hereinafter, referred to as a vertical electric field method). I have.

However, in the active matrix type liquid crystal display device employing the above-mentioned vertical electric field system, the luminance changes significantly when the viewing angle direction is changed. In particular, when halftone display is performed, the gradation level depends on the viewing angle direction. Has a practical problem, for example, is inverted.

The other is to enclose a liquid crystal layer between a pair of substrates and apply a driving voltage to two electrodes formed on the same substrate or on both substrates, so that a liquid crystal layer is applied in a direction substantially parallel to the substrate interface. The liquid crystal layer is driven by the electric field of the liquid crystal, and the light incident on the liquid crystal layer from the gap between the two electrodes is modulated and displayed (hereinafter referred to as a horizontal electric field method). Liquid crystal display devices have not yet been put to practical use.

However, the active matrix type liquid crystal display device adopting the in-plane switching mode has characteristics such as a wide viewing angle and a low load capacity. The in-plane switching mode is promising for an active matrix type liquid crystal display device. Technology.

For the characteristics of the active matrix type liquid crystal display device employing the horizontal electric field method, see Japanese Patent Application Laid-Open Nos. 5-505247, 63-21907 and JP-A-6-160878. .

[0009]

However, unlike the active matrix type liquid crystal display device employing the vertical electric field type, the active matrix type liquid crystal display device employing the horizontal electric field type shields the comb-shaped elongated electrodes from light. Since it is formed in an effective pixel area that cannot be covered with a film (black matrix), a step occurs in the alignment film depending on the thickness of the electrode.

[0010] Therefore, when rubbing the alignment film, the buffing cloth hardly hits the portion beside the electrode, so that it is difficult to rub the portion, resulting in poor alignment. In this case, light leakage occurs and black display does not sink, so that there is a problem that the contrast ratio is reduced or luminance unevenness is likely to occur due to distribution of rubbing intensity.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to improve the contrast in an active matrix type liquid crystal display device employing a horizontal electric field system, Another object of the present invention is to provide a technique capable of preventing the occurrence of uneven brightness.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a plurality of active elements formed in a matrix on the one substrate, and connected to the plurality of active elements, respectively. A plurality of pixel electrodes, and a plurality of opposed electrodes formed on one of the pair of substrates and applying an electric field substantially parallel to the substrate surface to the liquid crystal layer between the pixel electrodes, In the active matrix type liquid crystal display device having at least the counter electrode,
Is integrated with a counter voltage signal line extending in the first direction.
The pixel electrode, the counter electrode, and the counter voltage signal.
A line and the one substrate on which the active element is formed
The pixel electrode and the counter electrode formed in the same layer
Wherein the angle between the side surface and the substrate surface of the electrodes of less than 90 degrees than 0 degrees.

(2) In the means (1), an angle formed between a side surface of at least one of the pixel electrode and the counter electrode and a substrate surface is 45 degrees.

[0016]

[0017]

[0018]

[0019]

SUMMARY OF] According to each of the units, in an active matrix type liquid crystal display device employing a horizontal electric field method, the electrodes of the pixel electrode and the counter electrode is formed by a taper etching, the side surface of the electrodes of the pixel electrode and the counter electrode since the angle of the substrate surface was made to be 90 degrees or less acute angle greater than 0 °, when rubbing the alignment film, against smooth hair buffing cloth portion of the conductive Gokuwaki pixel electrode and a counter electrode can and Do Ri, since rubbing treatment in the vicinity of the end face of the electrode is carried out smoothly and reliably, it is possible to improve the orientation of the liquid crystal molecules of the liquid crystal layer of the electrode side portions.

As a result, there is no defective alignment region, the contrast ratio is improved, and the uneven brightness due to the distribution of the rubbing intensity can be eliminated.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[Embodiment 1] In this embodiment 1, a rubbing defect is suppressed by forming a taper angle on an end face of only a pixel electrode.
This is an embodiment in which the contrast is improved.

First, an outline of a lateral electric field type active matrix type color liquid crystal display device constructed in this embodiment will be described.

<< Planar Configuration of Display Matrix Section (Pixel Section) >> FIG. 1 is a plan view showing one pixel of an active matrix type color liquid crystal display device according to an embodiment (embodiment 1) of the present invention and its periphery. It is.

As shown in FIG. 1, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) (G
L) and two adjacent video signal lines (drain signal lines or vertical signal lines) (DL) in an intersection region (in a region surrounded by four signal lines).

Each pixel has a thin film transistor (TFT),
Storage capacitance (Cstg), pixel electrode (PX), counter electrode (CT) and counter voltage signal line (common signal line) (C
L).

Here, in FIG. 1, a plurality of scanning signal lines (GL) and counter voltage signal lines (CL) extend in the left-right direction and are arranged in a vertical direction.

The video signal lines (DL) extend in the up-down direction and are arranged in a plurality in the left-right direction.

The pixel electrode (PX) is connected to the source electrode (SD1) of the thin film transistor (TFT), and the counter electrode (CT) is formed integrally with the counter voltage signal line (CL).

The pixel electrode (PX) and the counter electrode (CT) face each other, and each pixel electrode (PX) and the counter electrode (CT)
The optical state of the liquid crystal layer (LC) is controlled by the electric field between the liquid crystal and the liquid crystal layer (LC) to control the display.

The pixel electrode (PX) and the counter electrode (CT) are formed in a comb-like shape, and each of them is a vertically elongated electrode in FIG.

In this embodiment, the pixel electrode (PX) has a downward open U-shape and the counter electrode (CT) has a counter voltage signal line (C).
L), it has a comb shape protruding downward, and the region between the pixel electrode (PX) and the counter electrode (CT) is divided into four within one pixel.

<< Cross-Sectional Structure of Display Matrix Part (Pixel Part) >> FIG. 2 is a cross-sectional view showing a cross section taken along line 3-3 shown in FIG. 1, and FIG. 3 is a thin film transistor taken along line 4-4 shown in FIG. FIG. 4 is a sectional view showing a section of (TFT).
Represents the storage capacity (Cst) at the section line 5-5 shown in FIG.
It is sectional drawing which shows the cross section of g).

As shown in FIGS. 2 to 4, the liquid crystal layer (LC)
On the lower transparent glass substrate (SUB1) side with reference to
A thin film transistor (TFT), a storage capacitor (Cstg) and an electrode group are formed, and an upper transparent glass substrate (SUB) is formed.
On the 2) side, a color filter (FIL) and a light-shielding black matrix pattern (BM) are formed.

Further, transparent glass substrates (SUB1, SUB)
An alignment film (ORI1, OR1) for controlling the initial alignment of the liquid crystal is provided on the inner surface (the liquid crystal layer (LC) side) of each of 2).
I2), and a transparent glass substrate (SUB1,
Polarizing plates (POL1, POL2) are provided on the outer surfaces of each of the SUB2).

Here, as shown in FIG. 2, the pixel electrode (P
The end face of X) is provided with a taper angle.

In this embodiment, the angle formed between the end face of the pixel electrode (PX) and the substrate surface is 45 °.

As a result, an orientation film (ORI1) to be described later is formed.
When rubbing is performed, rubbing is performed smoothly and reliably in the vicinity of the end face of the pixel electrode (PX), and it becomes possible to eliminate the poor alignment region.

Hereinafter, a more detailed configuration will be described.

<< TFT Substrate >> First, the structure of the lower transparent glass substrate (SUB1) side (TFT substrate) will be described in detail.

<< Thin Film Transistor (TFT) >> In a thin film transistor (TFT), when a positive bias is applied to the gate electrode (GT), the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases. Works like that.

As shown in FIG. 3, a thin film transistor (TFT) has a gate electrode (GT), a gate insulating film (G
I), an i-type (intrinsic, intrinsic, and undoped conductivity type determining impurity) amorphous silicon (Si) i-type semiconductor layer (AS), a pair of source electrodes (SD)
1) It has a drain electrode (SD2).

Note that the source electrode (SD1) and the drain electrode (SD2) are originally determined by the bias polarity between them. In the circuit of this liquid crystal display device, the polarities are inverted during operation. It should be understood that the electrode (SD2) is switched during operation.

However, in the following description, one is fixedly represented as the source electrode (SD1) and the other is represented as the drain electrode (SD2) for convenience.

In this embodiment, an amorphous silicon thin film transistor is used as the thin film transistor (TFT). However, the present invention is not limited to this. For example, a polysilicon thin film transistor, a MOS transistor on a silicon wafer, or an organic thin film transistor may be used. TFT or MIM
It is also possible to use a two-terminal element such as a (Metal-Insulator-Metal) diode (strictly not an active element, but an active element in the present invention).

<< Gate electrode (GT) >> Gate electrode (G)
T) is formed continuously with the scanning signal line (GL), and a partial region of the scanning signal line (GL) is partially formed with the gate electrode (G).
T).

The gate electrode (GT) is a portion exceeding the active region of the thin film transistor (TFT) and is formed larger than the active region so as to completely cover the i-type semiconductor layer (AS) (as viewed from below). .

Thus, in addition to the role of the gate electrode (GT), the device is designed so that external light and backlight do not hit the i-type semiconductor layer (AS).

In this embodiment, the gate electrode (GT) is formed of a single-layer conductive film (g1).
For example, an aluminum (Al) -based conductive film formed by sputtering is used, and an aluminum (Al) anodic oxide film (AOF) is provided thereon.

<< Scanning Signal Line (GL) >>
L) is composed of a conductive film (g1), and the conductive film (g1) of this scanning signal line (GL) is a gate electrode (GT).
Is formed in the same manufacturing process as that of the conductive film (g1), and is integrally formed.

The gate voltage (VG) is supplied from an external circuit to the gate electrode (GT) by the scanning signal line (GL).

An anodic oxide film (AOF) of aluminum (Al) is provided on the scanning signal line (GL).

The portion that intersects with the video signal line (DL) is thinned in order to reduce the probability of short-circuit with the video signal line (DL), and even if short-circuited, it can be separated by laser trimming. Has been bifurcated.

<< Counter electrode (CT) >> Counter electrode (CT)
Is formed of a conductive film (g1) in the same layer as the gate electrode (GT) and the scanning signal line (GL).

Also, an anodic oxide film (AOF) of aluminum (Al) is provided on the counter electrode (CT).

A counter voltage (Vco) is applied to the counter electrode (CT).
m) is applied.

In this embodiment, the counter voltage (Vcom) is
From the intermediate DC potential between the minimum level drive voltage (VDmin) and the maximum level drive voltage (VDmax) applied to the video signal line (DL), a thin film transistor element (TFT)
Is set to a potential lower by a feed-through voltage (for ΔVs) generated when the power supply is turned off. However, if it is desired to reduce the power supply voltage of the integrated circuit used in the video signal driving circuit to about half, the AC voltage is reduced. What is necessary is just to apply.

<< Counter Voltage Signal Line (CL) >> The counter voltage signal line (CL) is made of a conductive film (g1).

The conductive film (g) of this counter voltage signal line (CL)
1) is formed in the same manufacturing process as the conductive film (g1) of the gate electrode (GT), the scanning signal line (GL), and the counter electrode (CT), and is formed integrally with the counter electrode (CT).

The counter voltage (Vcom) is supplied from an external circuit to the counter electrode (CT) through the counter voltage signal line (CL).

An anodic oxide film (AOF) of aluminum (Al) is also provided on the counter voltage signal line (CL).

The portion that intersects with the video signal line (DL) is made thinner to reduce the probability of short-circuiting with the video signal line (DL) as with the scanning signal line (GL). It is bifurcated so that it can be separated by laser trimming.

The counter electrode (CT) and the counter voltage signal line (CL) may be formed on the upper transparent glass substrate (SUB2) (color filter substrate).

<< Insulating Film (GI) >> In a thin film transistor (TFT), the insulating film (GI) serves as a gate electrode (G).
T) is used together with T) as a gate insulating film for applying an electric field to the semiconductor layer (AS).

The insulating film (GI) is formed above the gate electrode (GT) and the scanning signal line (GL). As the insulating film (GI), for example, a silicon nitride film formed by plasma CVD is used. And is formed to a thickness of 1200 to 2700 angstroms (about 2400 angstroms in this embodiment).

The gate insulating film (GI) is formed so as to surround the entire display matrix portion (AR), and the peripheral portion is removed so that the external connection terminals (DTM, GTM) are exposed.

The insulating film (GI) also contributes to electrical insulation between the scanning signal line (GL) and the counter voltage signal line (CL) and the video signal line (DL).

<< i-Type Semiconductor Layer (AS) >> The i-type semiconductor layer (AS) is made of amorphous silicon and has a thickness of 200 to 2200 angstroms (in this embodiment, a thickness of about 2000 angstroms). You.

The layer (d0) is an N (+)-type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, and has an i-type semiconductor layer (AS) on the lower side and an upper side on the upper side. It is left only where the conductive films (d1, d2) are present.

The i-type semiconductor layer (AS) has a scanning signal line (G
L) and the counter voltage signal line (CL) and the video signal line (D
L) and between the two of the intersections (crossover parts).

The i-type semiconductor layer (AS) at the intersection reduces a short circuit between the scanning signal line (GL) and the counter voltage signal line (CL) and the video signal line (DL) at the intersection.

<< Source electrode (SD1), drain electrode (SD2) >> Source electrode (SD1), drain electrode (S
D2) are a conductive film (d1) in contact with the N (+) type semiconductor layer (d0) and a conductive film (d
2).

The conductive film (d1) is formed using a chromium (Cr) film formed by sputtering to a thickness of 500 to 1000 Å (about 600 Å in this embodiment).

The chromium (Cr) film is formed within a range not exceeding a thickness of about 2,000 angstroms, since the stress increases when the thickness is increased.

The chromium (Cr) film improves the adhesiveness to the N (+) type semiconductor layer (d0) and makes the aluminum (Al)
(Al) in the system-based conductive film (d2) is N
It is used for the purpose of preventing diffusion to the (+) type semiconductor layer (d0) (so-called barrier layer).

As the conductive film (d1), in addition to the chromium (Cr) film, high melting point metals (molybdenum (Mo), titanium (T
i), tantalum (Ta), tungsten (W)) film, refractory metal silicide (MoSi2, TiSi2, TaS)
i2, WSi2) film may be used.

As the conductive film (d2), an aluminum (Al) -based conductive film is formed by sputtering at 3000 to 50%.
00 angstroms (400 in this example)
(About 0 Å).

The aluminum (Al) -based conductive film has a smaller stress than the chromium (Cr) film and can be formed to have a large film thickness. The source electrode (SD1), the drain electrode (SD2) and the video signal The resistance of the line (DL), the gate electrode (GT) and the i-type semiconductor layer (AS)
Has the function of ensuring that the vehicle gets over a step (improves step coverage).

Here, the end faces of the source electrode (SD1) and the drain electrode (SD2) are given a taper angle,
In this embodiment, the angle between the end face and the substrate surface is 45 °.

This is because, when rubbing the orientation film (ORI1) described later, rubbing treatment is performed smoothly and reliably in the vicinity of the end face of the pixel electrode (PX), and the defective alignment region is eliminated.

In this embodiment, the pixel electrodes (PX),
A video signal line (DL), a source electrode (SD1), and
Since the drain electrode (SD2) is formed in the same layer in the same step, the video signal line (DL) and the source electrode (SD
1) The end face of the drain electrode (SD2) also has a similar taper angle.

After patterning the conductive film (d1) and the conductive film (d2) with the same mask pattern, using the same mask, or using the conductive film (d1) and the conductive film (d2)
Is used as a mask to remove the N (+) type semiconductor layer (d0).

That is, in the N (+) type semiconductor layer (d0) remaining on the i type semiconductor layer (AS), portions other than the conductive film (d1) and the conductive film (d2) are removed by self-alignment.

At this time, since the N (+)-type semiconductor layer (d0) is etched so as to remove the entire thickness, the i-type semiconductor layer (AS) is also slightly etched at its surface. The degree may be controlled by the etching time.

<< Video Signal Line (DL) >> Video Signal Line (D
L) is a source electrode (SD1) and a drain electrode (SD
2) and a conductive film (d1) and a conductive film (d2) formed thereon.

The video signal line (DL) is formed on the same layer as the source electrode (SD1) and the drain electrode (SD2), and the image signal line (DL) is formed on the drain electrode (SD).
It is configured integrally with 2).

As described above, the source electrode (SD1),
Similarly to the drain electrode (SD2), the end face of the video signal line (DL) has a taper angle of 45 °.

<< Pixel Electrode (PX) >> Pixel Electrode (PX)
Indicates a source electrode (SD1) and a drain electrode (SD2)
And a conductive film (d1) and a conductive film (d2) formed thereon.

The pixel electrode (PX) is formed in the same layer as the source electrode (SD1) and the drain electrode (SD2). Further, the pixel electrode (PX) is connected to the source electrode (SD).
It is configured integrally with 1).

As described above, the end surface of the pixel electrode (PX) has a taper angle of 45 °.

This is because when the alignment film (ORI1) is rubbed, the rubbing treatment near the end face of the pixel electrode (PX) is performed smoothly and surely, and the defective alignment region is eliminated.

As a result, light leakage near the pixel electrode (PX) electrode is eliminated, and the contrast ratio can be greatly improved.

<< Storage Capacitance (Cstg) >> Pixel Electrode (P
X) is configured to overlap the counter voltage signal line (CL) at an end opposite to the end connected to the thin film transistor (TFT).

As is apparent from FIG. 4, this superposition is performed by using the pixel electrode (PX) as one electrode (PL2).
A storage capacitor (capacitance element) (Cstg) that uses the opposite voltage signal (CL) as the other electrode (PL1) is configured.

The dielectric film of this storage capacitor (Cstg)
It is composed of an insulating film (GI) used as a gate insulating film of a thin film transistor (TFT) and an anodic oxide film (AOF).

As shown in FIG. 1, the storage capacitance (C
stg) is a conductive film (g1) of the counter voltage signal line (CL).
Is formed in a portion where the width is increased.

<< Protective Film (PSV) >> A protective film (PSV) is provided on the thin film transistor (TFT).

The protective film (PSV) is provided mainly for protecting the thin film transistor (TFT) from moisture and the like, and uses a film having high transparency and good moisture resistance.

The protective film (PSV) is made of, for example, plasma C
It is formed of a silicon oxide film or a silicon nitride film formed by a VD device, and has a thickness of about 1 μm.

The protective film (PSV) is formed so as to surround the entire display matrix portion (AR), and the peripheral portion is removed so as to expose the external connection terminals (DTM, GTM).

Protective film (PSV) and gate insulating film (GI)
The former is made thicker in consideration of the protection effect, and the latter is the transconductance (gm) of the transistor.
Think thin.

Therefore, a protective film (PSV) having a high protective effect
Is formed to be larger than the gate insulating film (GI) so as to protect the peripheral portion over the widest possible range.

<< Color Filter Substrate >> FIGS. 1 and 2
Returning to, the configuration of the upper transparent glass substrate (SUB2) side (color filter substrate) will be described in detail. << Light-shielding film (BM) >> On the upper transparent glass substrate (SUB2) side, unnecessary gaps (pixel electrode (PX) and counter electrode (C
The transmitted light from gaps other than T) is emitted to the display surface side, so that the light shielding film (B
M) (a so-called black matrix) is formed.

The light-shielding film (BM) also serves to prevent external light or backlight from entering the i-type semiconductor layer (AS).

That is, the i-type semiconductor layer (AS) of the thin film transistor (TFT) is sandwiched between the upper and lower light-shielding films (BM) and the large gate electrode (GT), so that external natural light or backlight is not irradiated.

The closed polygonal outline of the light-shielding film (BM) shown in FIG. 1 indicates an opening in which the light-shielding film (BM) is not formed.

The vertical boundaries shown in FIG. 1 are determined by the alignment accuracy of the upper and lower substrates. If the alignment accuracy is better than the width of the counter electrode (CT) adjacent to the video signal line (DL), the counter electrode If the width is set between the widths, the opening can be further enlarged.

The light-shielding film (BM) has a light-shielding property and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode (PX) and the counter electrode (CT). In this embodiment, a black pigment is mixed into the resist material to form a film having a thickness of about 1.2 μm.

The light-shielding film (BM) is formed in a grid around each pixel, and an effective display area of one pixel is partitioned by the grid.

Therefore, the outline of each pixel is made clear by the light shielding film (BM).

That is, the light-shielding film (BM) has two functions of light shielding for the black matrix and the i-type semiconductor layer (AS).

The light-shielding film (BM) is also formed in a frame shape in the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG.

The light-shielding film (BM) in the peripheral portion is sealed (S
L) to prevent leakage light such as reflected light from a mounting machine such as a personal computer from entering the display matrix portion.

On the other hand, this light-shielding film (BM) is fixed about 0.3 to 1.0 mm inside the edge of the upper transparent glass substrate (SUB2), and is formed avoiding the cutting area of the upper transparent substrate (SUB2). Have been.

<< Color Filter (FIL) >> The color filter (FIL) is formed in a stripe shape by repeating red, green, and blue at positions facing the pixels. The color filter (FIL) is formed of a light-shielding film (BM). ) Is formed so as to overlap the edge portion.

The color filter (FIL) can be formed as follows.

First, a dyed base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate (SUB2), and the dyed base material other than the red filter forming region is removed by photolithography.

Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter (R).

Next, by performing similar steps,
A green filter (G) and a blue filter (B) are sequentially formed.

<< Overcoat Film (OC) >> The overcoat film (OC) prevents the dye from leaking from the color filter (FIL) to the liquid crystal layer (LC), and prevents the color filter (FIL) and the light-shielding film. It is provided to flatten the step due to (BM).

The overcoat film (OC) is made of, for example, a transparent resin material such as an acrylic resin and an epoxy resin.

<< Liquid Crystal Layer and Polarizing Plate >> Next, the liquid crystal layer, the alignment film, the polarizing plate and the like will be described.

<< Liquid Crystal Layer >> The liquid crystal material of the liquid crystal layer (LC) has a positive dielectric anisotropy (Δε) and a value of 13.
2. The refractive index anisotropy (Δn) is 0.081 (589 nm,
(20 ° C.) nematic liquid crystal is used.

The thickness (gap) of the liquid crystal layer is 3.9 μm
And the retardation (Δn · d) is 0.316.

The value of this retardation (Δn · d) is
The wavelength characteristic of the backlight is set to be approximately half the average wavelength, and the color of the transmitted light of the liquid crystal layer is white (C light source,
The chromaticity coordinates are set so that x = 0.3101 and y = 0.3163).

When the angle between the polarization transmission axis of the polarizing plate and the major axis direction of the liquid crystal molecules is 45 °, the maximum transmittance can be obtained, and the transmitted light having almost no wavelength dependency within the visible light range can be obtained. be able to.

Note that the thickness (gap) of the liquid crystal layer is controlled by polymer beads.

Note that the liquid crystal material of the liquid crystal layer (LC) is not particularly limited, and the dielectric anisotropy Δε may be negative.

The larger the value of the dielectric anisotropy (Δε), the lower the driving voltage can be. The smaller the refractive index anisotropy (Δn), the smaller the thickness (gap) of the liquid crystal layer.
Can be made thicker, the liquid crystal filling time can be shortened, and the gap variation can be reduced.

<< Orientation Film >> Polyimide is used as the orientation film (ORI).

As shown in FIG. 19, the rubbing direction (RDR) is parallel to each other between the upper and lower substrates, and the angle between the rubbing direction and the applied electric field direction (EDR) is 75 °.

Note that the angle between the rubbing direction (RDR) and the applied electric field direction (EDR) is 45 ° C. or more if the dielectric anisotropy (Δε) of the liquid crystal material of the liquid crystal layer (LC) is positive. 0 ° C. if the dielectric anisotropy (Δε) is negative, 0 °
And 45 ° or less.

In this embodiment, since the pixel electrode (PX) has a tapered angle, there is no step at both ends of the pixel electrode (PX), and the buff cloth of the rubbing machine smoothly removes the pixel electrode. (PX) Since it is in contact with the vicinity of both ends, rubbing defects are eliminated.

As a result, the alignment state of the liquid crystal molecules is stabilized, and a good display can be performed.

<< Polarizing Plate >> As shown in FIG. 19, the polarization transmission axis (MAX1) of the lower polarizing plate (POL1) is matched with the rubbing direction (RDR), and the upper polarizing plate (POL2) is set.
The polarization transmission axis (MAX2) is orthogonal to it.

As a result, in this embodiment, the normally closed characteristic in which the transmittance increases as the voltage applied to the pixel (the voltage between the pixel electrode (PX) and the counter electrode (CT)) increases. Obtainable.

<< Configuration around Display Matrix Unit (AR) >>
FIG. 5 is a diagram showing a main part plane around a display matrix (AR) portion of a display panel (PNL) including upper and lower glass substrates (SUB1, SUB2).

FIG. 6 is a diagram showing a cross section near the external connection terminal (GTM) to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

In the manufacture of this panel, if the size is small, a plurality of devices are simultaneously processed on one glass substrate and then divided in order to improve the throughput. after processing the glass substrate of a standardized size in any breed for shared, reducing the size to suit each model, in either case the glass is cut through the one way process.

FIGS. 5 and 6 show examples of the latter. Both FIGS. 5 and 6 show upper and lower transparent glass substrates (SUB1, S2).
UB2) after cutting, and LN shown in FIG. 5 indicates an edge of both substrates before cutting.

In any case, in the completed state, the external connection terminal group (Tg, Td) and the terminal (CTM) (subscripts are omitted) are present (the upper and left sides in the figure) so that they are exposed. The size of the upper transparent glass substrate (SUB2) is limited inside the lower transparent glass substrate (SUB1).

The terminal group (Tg, Td) includes a scanning circuit connection terminal (GTM) and a video signal circuit connection terminal (DTM), which will be described later, and an integrated circuit chip (CHI) having their leading wiring portions. Tape carrier package (T
CP) (FIGS. 16 and 17).

The lead wiring from the display matrix part of each group to the external connection terminal part is inclined as approaching both ends.

This is for adjusting the terminals (DTM, GTM) of the display panel (PNL) to the arrangement pitch of the packages (TCP) and the connection terminal pitch of each package (TCP).

The counter electrode terminal (CTM) is a terminal for applying a counter voltage (Vcom) to the counter electrode (CT) from an external circuit.

The counter voltage signal lines (C
L) is pulled out to the opposite side (right side in the figure) of the scanning circuit terminal (GTM), and the common voltage signal lines (CL) are grouped together by a common bus line (CB) (counter electrode connection signal line). It is connected to the electrode terminal (CTM).

Along the edges between the transparent glass substrates (SUB1, SUB2), except for the liquid crystal filling port (INJ),
A seal pattern (S) is used to seal the liquid crystal layer (LC).
L) is provided.

The seal pattern (SL) is formed from, for example, an epoxy resin.

The layers of the alignment films (ORI1, ORI2) are formed inside the seal pattern (SL), and the polarizing plates (POL1, POL2) are formed of a lower transparent glass substrate (SUB1) and an upper transparent glass substrate (SUB1). SUB2) is formed on the outer surface.

The liquid crystal layer (LC) comprises a lower alignment film (ORI1) for setting the direction of liquid crystal molecules and an upper alignment film (ORI2).
Is sealed in a region partitioned by a seal pattern (SL).

The lower alignment film (ORI1) is formed above the protective film (PSV) on the lower transparent glass substrate (SUB1) side.

In the liquid crystal display of this embodiment, the lower transparent glass substrate (SUB1) and the upper transparent glass substrate (SUB1) are used.
After 2) is formed by stacking various layers separately, a seal pattern (SL) is formed on the upper transparent glass substrate (SUB2) side, and the lower transparent glass substrate (SUB1) and the upper transparent glass substrate (SUB2) are separated. The liquid crystal (LC) is injected through the opening (INJ) of the seal pattern (SL), the injection port (INJ) is sealed with an epoxy resin or the like, and the upper and lower substrates are cut.

<< Gate Terminal (GTM) Unit >> FIG. 7 is a diagram showing a connection structure from a scanning signal line (GL) of the display matrix unit (AR) to a gate terminal (GTM) which is an external connection terminal thereof. FIG. 7A is a plan view, and FIG.
FIG. 8B is a cross-sectional view taken along the line BB shown in FIG.

FIG. 7 corresponds to the vicinity of the lower part in FIG. 5, and the oblique wiring portion is represented by a straight line for convenience.

In FIG. 7, reference symbol AO denotes a border line for direct drawing of photoresist, in other words, a photoresist pattern of selective anodic oxidation.

Therefore, this photoresist is removed after anodic oxidation, and the pattern (AO) shown in FIG. 7 does not remain as a finished product, but an oxide film (AOF) is formed on the gate wiring (GL) as shown in the sectional view. Since it is selectively formed, the trajectory remains.

In the plan view of FIG. 7A, the left side is a region covered with resist and not subjected to anodic oxidation with reference to the boundary line (AO) of the photoresist, and the right side is a region exposed from the resist and anodized.

The anodized aluminum (AL) -based conductive film (g1) has an aluminum oxide film (Al2
O3) is formed and the volume of the lower conductive portion is reduced.

Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains.

In FIG. 7, the aluminum (AL) -based conductive film (g1) is hatched for easy understanding, but the region that is not anodized is patterned in a comb shape.

This is because, when the width of the aluminum (Al) -based conductive film is large, whiskers are generated on the surface. Therefore, the width of each one is reduced, and a plurality of these are bundled in parallel. The aim is to minimize the probability of disconnection and sacrificing conductivity while preventing the generation of whiskers.

The gate terminal (GTM) has an aluminum (Al) -based conductive film (g1), further protects the surface thereof, and has a TCP (Tape Carrier Pac).
Keg) and a transparent conductive film (g2) for improving the reliability of connection with the transparent conductive film (g2).

The transparent conductive film (g2) is a transparent conductive film (Indium-Tin-O) formed by sputtering.
xide ITO: Nesa film), 1000 to 20
00 angstroms (140 in this embodiment)
(A film thickness of about 0 Å).

The conductive film (d1) formed on the aluminum (Al) -based conductive film (g1) and on the side surface thereof has a poor connection between the conductive film (g1) and the transparent conductive film (g2). Chromium (Cr) layer (d) having good connectivity to both the conductive film (g1) and the transparent conductive film (g2)
1) to reduce the connection resistance, and the conductive film (d2) remains because it is formed using the same mask as the conductive film (d1).

In the plan view of FIG. 7A, the gate insulating film (GI) is formed on the right side of the boundary line (AO), and the protective film (PSV) is formed on the left side of the boundary line (AO). The terminal portion (GTM) located at the left end is exposed from the terminal portion so that electrical contact with an external circuit can be made.

In FIG. 7, only one pair of the gate line (GL) and the gate terminal is shown. However, in practice, a plurality of such pairs are arranged vertically and the terminal group (Tg) shown in FIG.
In the manufacturing process, the left end of the gate terminal extends beyond the cutting region of the substrate and is short-circuited by a wiring (SHg) (not shown).

In the manufacturing process, such a short-circuit line (SH
g) is useful for power supply during anodization and prevention of electrostatic breakdown during rubbing of the alignment film (ORI1).

<< Drain Terminal (DTM) Unit >> FIG. 8 is a diagram showing the connection from the video signal line (DL) of the display matrix unit (AR) to the drain terminal (DTM) which is an external connection terminal. 8 (A) is a plan view thereof, and FIG.
FIG. 9B is a cross-sectional view taken along the line BB shown in FIG.

FIG. 8 corresponds to the vicinity of the upper right in FIG. 5, and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end of the lower transparent glass substrate (SUB1).

In FIG. 8, TSTd is an inspection terminal, to which an external circuit is not connected, but is wider than a wiring portion so that a probe needle or the like can be contacted.

Similarly, the width of the drain terminal (DTM) is wider than that of the wiring portion so that connection with an external circuit is possible.

A plurality of drain terminals (DTM) are vertically arranged to form a terminal group (Td) (subscript omitted) shown in FIG. 5, and a drain terminal (DTM) is provided on the lower transparent glass substrate (SUB1). , And all of them are short-circuited to each other by a wiring (SHd) (not shown) to prevent electrostatic breakdown during the manufacturing process.

The test terminals (TSTd) are provided on every other video signal line (DL) as shown in FIG.

The drain connection terminal (DTM) is formed of a single layer of the transparent conductive film (g2), and has a gate insulating film (G
The portion where I) is removed is connected to the video signal line (DL).

The semiconductor layer (AS) formed on the edge of the gate insulating film (GI) is for etching the edge of the gate insulating film (GI) in a tapered shape.

On the drain connection terminal (DTM), the protection film (PSV) is removed to make connection with an external circuit.

The lead wiring from the display matrix part (AR) to the drain terminal part (DTM) is a video signal line (DL)
Conductive layers (d1, d2) at the same level as the protective film (PS)
V), and is connected to the transparent conductive film (g2) in the protective film (PSV).

This is made of aluminum (Al) which is easily contacted.
The purpose is to protect the system conductive film (d2) with a protective film (PSV) and a seal pattern (SL) as much as possible.

<< Counter electrode terminal (CTM) >> FIG. 9 is a diagram showing the connection from the counter voltage signal line (CL) to the counter electrode terminal (CTM) which is an external connection terminal.
FIG. 9A is a plan view thereof, and FIG.
It is sectional drawing in the BB cutting line shown to (A).

FIG. 9 corresponds to the vicinity of the upper left in FIG.

Each common voltage signal line (CL) is led together to a common electrode terminal (CTM) by a common bus line (CB).

The common bus line (CB) is connected to the conductive film (g)
It has a structure in which a conductive film (d1) and a conductive film (d2) are stacked on 1).

This reduces the resistance of the common bus line (CB), and the counter voltage is supplied from an external circuit to each counter voltage signal line (C).
L).

According to this structure, the resistance of the common bus line (CB) can be reduced without adding a new conductive film.

The conductive film (g1) of the common bus line (CB)
Does not participate in the anode so as to be electrically connected to the conductive film (d1) and the conductive film (d2), and is also exposed from the gate insulating film (GI).

The counter electrode terminal (CTM) is connected to the conductive film (g
It has a structure in which a transparent conductive film (g2) is laminated on 1).

As described above, the transparent conductive film (g2) having good durability for protecting the surface and preventing electrolytic corrosion, etc.
The conductive film (g1) is covered.

<< Equivalent Circuit of the Entire Display Device >> FIG. 10 is a diagram showing a connection diagram of an equivalent circuit of the display matrix portion (AR) and its peripheral circuits.

Although FIG. 10 is a circuit diagram, it is drawn corresponding to an actual geometric arrangement.

In FIG. 10, AR indicates a display matrix section (matrix array) in which a plurality of pixels are two-dimensionally arranged.

In FIG. 10, X indicates a video signal line (DL), and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively.

.., End are added according to the order of the scanning timing.

The scanning signal line (Y) (subscript omitted) is connected to the vertical scanning circuit (V), and the video signal line (X) (subscript omitted) is connected to the video signal driving circuit (H).

The circuit (SUP) includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CRT (cathode ray tube) from a host (upper processing unit).
Is a circuit including a circuit for exchanging information for use with information for a (TFT) liquid crystal display device.

<< Driving Method >> FIG. 11 is a diagram showing driving waveforms at the time of driving in the liquid crystal display device of this embodiment.
1 (a) and FIG. 11 (b) show a gate voltage (scan signal voltage) (VG) applied to the (i-1) th and (i) th scan signal lines (GL), respectively. .

FIG. 11C shows a video signal line (D
L) shows the video signal voltage (VD) applied to
(D) shows a counter voltage (V) applied to the counter electrode (CT).
com).

Further, FIG. 11 (e) shows row (i),
(J) shows the pixel electrode voltage (Vs) applied to the pixel electrode (PX) in the pixels in the column, and FIG.
The voltage (VLC) applied to the liquid crystal layer (LC) of the pixel in the row and column (j) is shown.

In the driving method of the liquid crystal display device of the present embodiment, as shown in FIG. 11D, the counter voltage (Vcom) applied to the counter electrode (CT) is changed to a binary AC quadrature of VCH and VCL. Gate wave (GT)
The non-selection voltage of the gate voltage (VG) to be applied is changed by two values of VGLH and VGLL every scanning period.

In this case, the amplitude value of the counter voltage (Vcom) is made equal to the amplitude value of the non-selection voltage of the gate voltage (VG).

The video signal voltage (VD) applied to the video signal line (DL) is a voltage (VSIG) obtained by subtracting half the amplitude of the counter voltage (VC) from the voltage to be applied to the liquid crystal layer (LC). It is.

The counter voltage (V) applied to the counter electrode (CT)
com) may be DC, but by converting it to AC, the maximum amplitude of the video signal voltage (VD) can be reduced, and a video signal drive circuit (signal-side driver) having a low withstand voltage can be used.

<< Function of Storage Capacitance (Cstg) >> The storage capacity (Cstg) is provided for storing video information written in the pixel (after the thin film transistor (TFT) is turned off) for a long time.

The method of applying an electric field parallel to the substrate surface as in the present embodiment is different from the method of applying the electric field perpendicular to the substrate surface, and comprises a pixel electrode (PX) and a counter electrode (CT). Since there is almost no capacity (so-called liquid crystal capacity (Cpix)), video information cannot be stored in pixels without a storage capacity (Cstg).

Therefore, in the method of applying an electric field in parallel with the substrate surface, the storage capacitance (Cstg) is an essential component.

The storage capacitance (Cstg) also functions to reduce the effect of the gate potential change (ΔVG) on the pixel electrode potential (Vs) when the thin film transistor (TFT) switches.

This situation is represented by the following equation.

ΔVs = ｛Cgs / (Cgs + Cstg +
Cpix)｝ × ΔVG Here, Cgs is a parasitic capacitance formed between the gate electrode (GT) and the source electrode (SD1) of the thin film transistor (TFT), and Cpix is a pixel electrode (PX) and a counter electrode (CT). ΔVs represents a so-called feed-through voltage corresponding to a change in pixel electrode potential due to ΔVG.

The change (ΔVs) is calculated based on the liquid crystal layer (LC).
Causes a DC component to be added to the holding capacitance (Cst
The larger the value of g), the smaller the value.

The reduction of the DC component applied to the liquid crystal layer (LC) can improve the life of the liquid crystal layer (LC) and reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, the gate electrode (GT)
The source electrode (SD1) and the drain electrode (SD2) are made larger so as to completely cover the i-type semiconductor layer (AS).
Overlap area with the parasitic capacitance (Cg)
s) increases, and the pixel electrode potential (Vs) has an adverse effect of being easily affected by the gate voltage (scanning signal voltage) (VG).

However, this disadvantage can be eliminated by providing the storage capacitor (Cstg).

<< Manufacturing Method >> Next, a method of manufacturing the above-described liquid crystal display device on the lower transparent glass substrate (SUB1) side will be described with reference to FIGS.

In FIGS. 12 to 14, the characters in the center are the abbreviations of the process names, the left side is the thin film transistor (TFT) portion shown in FIG. 3, and the right side is the cross sectional shape near the gate terminal shown in FIG. The flow of is shown.

Except for Steps B and D, Steps A to I are classified according to the respective photographic processes. Each of the cross-sectional views in each of the processes is the stage where the processing after the photographic process is completed and the photoresist is removed. Is shown.

In the following description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description will be omitted.

The description will be given below according to the divided steps.

(Step A, FIG. 12) A 3000 .ANG.-thick aluminum (Al) -palladium (P) film was formed on a lower transparent glass substrate (SUB1) made of glass.
d) A conductive film (g1) made of aluminum (Al) -silicon (Si), aluminum (Al) -tantalum (Ta), aluminum (Al) -titanium (Ti) -tantalum (Ta), or the like is formed by sputtering. .

After photographic processing, the conductive film (g1) is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, glacial acetic acid and water.

As a result, the gate electrode (GT), scanning signal line (GL), counter electrode (CT), counter voltage signal line (CL), electrode (PL1), gate terminal (GTM), common bus line (CB) Of the first conductive film and the counter electrode terminal (C
TM), an anodized bus line (SHg) (not shown) for connecting the gate terminal (GTM), and an anodized pad (not shown) connected to the anodized bus line (SHg). I do.

(Step B, FIG. 12) After forming an anodic oxidation mask (AO) by direct writing, a solution in which 3% tartaric acid was adjusted to PH 6.25 ± 0.05 with ammonia was diluted 1: 9 with an ethylene glycol solution. The lower transparent glass substrate (SUB1) is immersed in the anodized solution composed of the solution thus prepared, and adjusted so that the formation current density becomes 0.5 mA / cm ² (constant current formation).

Next, an aluminum oxide film (A
Anodization is performed until the formation voltage 125 V necessary for obtaining OF) is obtained.

Thereafter, it is desirable to hold this state for several tens of minutes (constant voltage formation).

This is because a uniform aluminum oxide film (AO
This is important for obtaining F).

As a result, the conductive film (g1) is anodized, and the gate electrode (GT), the scanning signal line (GL), the counter electrode (CT), the counter voltage signal line (CL), and the electrode (P
An anodized film (AOF) having a thickness of 1800 angstroms is formed on L1).

(Step C, FIG. 12) A transparent conductive film (g2) made of an ITO film having a thickness of 1400 angstroms is formed by sputtering.

After the photographic processing, the transparent conductive film (g2) is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal (GTM),
Drain terminal (DTM) and counter electrode terminal (CTM)
Is formed.

(Step D, FIG. 13) An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus, and a silicon nitride film (Si
NX), and a silane gas and a hydrogen gas are introduced into the plasma CVD apparatus.
After forming the amorphous silicon (Si) film, the plasma C
Hydrogen gas and phosphine gas are introduced into the VD apparatus to form an N (+) type amorphous silicon (Si) film having a thickness of 300 Å.

(Step E, FIG. 13) After the photographic processing, N (+) type amorphous silicon (S) was formed using sulfur hexafluoride (SF6) and carbon tetrachloride (CC14) as dry etching gas.
i) The island of the i-type semiconductor layer (AS) is formed by selectively etching the film and the i-type amorphous silicon (Si) film.

(Step F, FIG. 13) After the photographic processing, sulfur hexafluoride (SF6) was used as a dry etching gas.
The silicon nitride film is selectively etched.

(Step G, FIG. 14) A conductive film (d1) made of chromium (Cr) having a thickness of 600 angstroms is provided by sputtering, and an aluminum (Al) -tantalum (T) having a thickness of 4000 angstroms is further provided.
a), a conductive film (d2) made of aluminum (Al) -titanium (Ti) -tantalum (Ta) or the like is provided by sputtering.

After the photographic processing, the conductive film (d2) was etched with a mixed acid solution having an increased ratio of nitric acid to the mixed acid solution of Step A, which was composed of phosphoric acid, nitric acid, glacial acetic acid and water, to form the conductive film (d1) Etching with ceric ammonium nitrate solution, video signal line (DL), source electrode (SD1), drain electrode (S
D2), the pixel electrode (PX), the electrode (PL2), the second conductive film, the third conductive film of the common bus line (CB), and the bus line (SHd) (not shown) for short-circuiting the drain terminal (DTM). Form.

By increasing the ratio of nitric acid from the mixed acid solution in step A, the resist material gradually peels off from the edge during the etching, so that the etching solution penetrates from the edge and the taper angle of the conductive film (d2) increases. Granted.

In this embodiment, aluminum (Al) -tantalum (Ta) and aluminum (Al) -titanium (T
i) Using a material such as tantalum (Ta), a conductive film (d
Although taper is applied to 2), other metals can also be tapered by mixing nitric acid with the etching solution.

As a resist material used in this example, a semiconductor resist OFPR800 (trade name) manufactured by Tokyo Ohka Chemical Co., Ltd. was used.

The taper angle can be controlled by changing the concentration of nitric acid in the etching solution.

Next, carbon tetrachloride (CCl 4) and sulfur hexafluoride (SF 6) were introduced into a dry etching apparatus, and N 2 was introduced.
The N (+) type semiconductor layer (d0) between the source and the drain is selectively removed by etching the (+) type amorphous silicon (Si) film.

(Step H, FIG. 14) An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to form a silicon nitride film having a thickness of 1 μm.

After the photographic processing, a protective film (PSV) is formed by selectively etching the silicon nitride film by a photolithography technique using sulfur hexafluoride (SF6) as a dry etching gas.

<< Display Panel (PNL) and Drive Circuit Board P
CB1 >> FIG. 15 shows the display panel (PNL) shown in FIG.
FIG. 3 is a plan view showing a state where a video signal driving circuit (H) and a vertical scanning circuit (V) are connected.

In FIG. 15, CHI is a display panel (P
15 are driving IC chips on the vertical scanning circuit side and the left ten driving IC chips on the video signal driving circuit side shown in FIG.

A TCP is a tape carrier package in which a driving IC chip (CHI) is mounted by a tape automated bonding method (TAB), as will be described later with reference to FIGS. 16 and 17. PCB1 is a tape carrier package (TCP). ), A drive circuit board on which capacitors and the like are mounted, and divided into two for a video signal drive circuit and a scan signal drive circuit.

FGP is a frame ground pad,
A spring-shaped fragment provided by cutting into a shield case (SHD) is soldered.

FC is a flat cable for electrically connecting the lower drive circuit board (PCB1) and the left drive circuit board (PCB1).

As the flat cable (FC), a cable in which a plurality of lead wires (phosphor bronze material plated with tin (Sn)) is sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer is used. use.

<< TCP Connection Structure >> FIG. 16 shows a configuration of the scanning signal driving circuit (V) and the video signal driving circuit (H).
FIG. 17 is a cross-sectional view showing a cross-sectional structure of a tape carrier package (TCP) in which an integrated circuit chip (CHI) is mounted on a flexible wiring board. FIG. 17 shows a state in which it is connected to a liquid crystal display panel (PNL) (FIG. FIG. 3 is a cross-sectional view of a main part showing a state in which the terminal is connected to a scanning signal circuit terminal (GTM).

In FIG. 16, TTB is an integrated circuit (CH
I) input terminal and wiring section, and TTM is an integrated circuit (C
HI) output terminal and wiring section, and terminals (TTB, TT
M) is made of, for example, copper (Cu), and an integrated circuit (CH) is provided at each inner tip (commonly referred to as an inner lead).
The bonding pad (PAD) of I) is connected by a so-called face-down bonding method.

[0248] The tips (commonly called outer leads) outside the terminals (TTB, TTM) correspond to the input and output of the semiconductor integrated circuit chip (CHI), respectively, and are connected to a CRT / TFT conversion circuit / power supply circuit by soldering or the like. (SUP),
Alternatively, a liquid crystal display panel (PNL) is connected by an anisotropic conductive film (ACF).

The package (TCP) has
The connection terminal (GTM) on the panel (PNL) side is connected to the panel so as to cover the exposed protective film (PSV). Therefore, the external connection terminal (GTM) (or DTM)
Is covered with at least one of a protective film (PSV) and a package (TCP), so that it is resistant to electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that solder does not stick to unnecessary portions during soldering.

The gap between the upper and lower glass substrates outside the seal pattern (SL) is protected by an epoxy resin (EPX) or the like after washing, and the package (TCP) and the upper substrate (SUB) are cleaned.
Between 2), silicone resin (SIL) is further filled to multiplex protection.

<< Drive Circuit Board (PCB2) >> The drive circuit board (PCB2) has electronic components such as ICs, capacitors and resistors mounted thereon.

The drive circuit board (PCB2) includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CRT (cathode ray tube) from a host (upper processing unit). A circuit (SUP) including a circuit for converting the information for ()) into the information for the (TFT) liquid crystal display device is mounted.

CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected.

The driving circuit board (PCB1) and the driving circuit board (PCB2) are electrically connected by a flat cable (FC).

<< Overall Configuration of Liquid Crystal Display Module (MDL) >> FIG. 18 is an exploded perspective view showing each component of the liquid crystal display module (MDL).

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW and its display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide,
RM is a reflection plate, BL is a backlight fluorescent tube, LCA is a backlight case, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble a module MDL.

The module (MDL) is entirely fixed by claws and hooks provided on a shield case (SHD).

The backlight case (LCA) is configured to house a backlight fluorescent tube (BL), a light diffusion plate (SPB), a light guide (LCB), and a reflection plate (RM). The light of the backlight fluorescent tube (BL) arranged on the side of the (LCB) is transmitted to the light guide (LCB) and the reflector (R).
M), a uniform backlight is formed on the display surface by the light diffusion plate (SPB), and the light is emitted toward the liquid crystal display panel (PNL).

An inverter circuit board (PCB3) is connected to the backlight fluorescent tube (BL), and serves as a power source for the backlight fluorescent tube (BL).

As described above in detail, in the present embodiment, the rubbing of the alignment film (ORI1) is performed by imparting a taper angle to the end face of the pixel electrode (PX).
A rubbing process in the vicinity of the end surface of the pixel electrode (PX) can be performed smoothly and reliably, and a poor alignment region can be eliminated.
An active matrix liquid crystal display device having a good contrast ratio can be obtained.

[Embodiment 2] In this embodiment, the pixel electrode (P
By giving a taper angle to both X) and the counter electrode (CT), orientation defects near the counter electrode (CT) are eliminated, and a better contrast ratio is obtained.

This embodiment is the same as Embodiment 1 except for the configuration of the counter electrode (CT) and the manufacturing method related thereto, except for the following items.

FIG. 20 is a cross-sectional view showing a cross section of a pixel (cross section taken along line 3-3 in FIG. 1) in an active matrix type color liquid crystal display device according to another embodiment (embodiment 2) of the present invention. It is.

The counter electrode (CT) is a gate electrode (GT)
And a conductive film (g1) of the same layer as the scanning signal line (GL).

Further, an anodic oxide film (AOF) of aluminum (Al) is formed on the counter electrode (CT), and the conductive film (g1) of the counter electrode (CT) has a taper angle of 45 °. Is given.

Next, the manufacturing method of this embodiment will be described.

The lower transparent glass substrate made of glass (SU
B1) Aluminum (Al) -tantalum (Ta) and aluminum (A) having a film thickness of 3000 Å on
1) A conductive film (g1) made of -titanium (Ti) -tantalum (Ta) or the like is formed by sputtering.

After the photographic processing, the conductive film (g1) was etched with a mixed acid solution composed of phosphoric acid, nitric acid, glacial acetic acid and water, in which the ratio of nitric acid was higher than that of the mixed acid solution in step A in Example 1 described above. The gate electrode (GT), the scanning signal line (GL), the counter electrode (CT), and the counter voltage signal line (C
L), electrode (PL1), gate terminal (GTM), first conductive film of common bus line (CB), counter electrode terminal (CT
M) forming a first conductive film, an anodizing bus line (SHg) (not shown) for connecting the gate terminal (GTM) and an anodizing pad (not shown) connected to the anodizing bus line (SHg); I do.

As described above, in this embodiment, the taper angle is also given to the end face of the counter electrode (CT), so that when the alignment film (ORI1) is rubbed, the pixel electrode (PX) is not rubbed.
In addition, it is possible to smoothly and reliably perform the rubbing treatment near the end face of the counter electrode (CT), to eliminate the poorly-aligned region, and to obtain an active matrix liquid crystal display device having a better contrast ratio than that of the first embodiment. it can.

[Embodiment 3] Embodiment 3 is different from Embodiment 2 described above.
Similarly to the above, by giving a taper angle to both the pixel electrode (PX) and the counter electrode (CT), the counter electrode (C
T) is to eliminate the poor orientation in the vicinity and obtain a better contrast ratio.

However, in the third embodiment, the pixel electrode (P
By forming X) and the counter electrode (CT) in the same step, a taper angle is given to both of them at the same time, and is the same as Example 1 except for the following items.

FIG. 21 is a plan view showing a pixel portion and its periphery in this embodiment, and FIG.
It is sectional drawing which shows the cross section in 3 cutting lines.

Here, as shown in FIG. 22, the pixel electrode (PX) and the counter electrode (CT) are formed in the same layer.
A taper angle is given to both end faces of the pixel electrode (PX) and the counter electrode (CT).

As a result, in the same manner as in Example 2, when rubbing the alignment film described later, the rubbing treatment is performed smoothly and reliably near the end surfaces of the pixel electrode (PX) and the counter electrode (CT), and the alignment defect is prevented. Regions can be eliminated.

In this embodiment, the pixel electrodes (PX),
Since the counter electrode (CT), the video signal line (DL), the source electrode (SD1), and the drain electrode (SD2) are formed in the same layer in the same step, the video signal line (DL) and the source electrode (SD1) Also, a similar taper angle is given to the end face of the drain electrode (SD2).

The counter electrode (CT) and the counter voltage signal line (CL) have a through hole (SH) formed in the gate insulating film (GI) and are electrically connected to each other.

When the counter voltage signal line (CL) is formed of an aluminum (Al) -based conductive film (g1),
In order to establish a connection between the counter electrode (CT) and the counter voltage signal line (CL), anodic oxidation is not performed on the counter voltage signal line (CL), the same material as the same, and those formed in the same step.

In this case, the opposite voltage signal line (C
If chromium (Cr) is used for L) and the same material as the same, and a conductive film formed in the same step, it is not necessary to perform anodic oxidation.

Further, by providing the counter voltage signal line (CL) in the same layer as the pixel electrode (PX), it is possible to avoid forming the through-hole (SH).

As described above, in this embodiment, in addition to the effects of the second embodiment, only one taper etching step is required.

In this embodiment, the counter electrode (CT) is formed in the same layer as the pixel electrode (PX) so that the taper angle is given in the same step.
The effect is the same even if X) is formed in the same layer as the counter electrode (CT) in the same step.

[Embodiment 4] [0283] This embodiment 4 is different from the above-mentioned embodiment 1 in the manufacturing method for taper etching, and therefore is the same as the above-mentioned embodiment 1 except for the following manufacturing method.

In the fourth embodiment, the etching of the pixel electrode (PX) is performed by dry etching.
In this embodiment, when the pixel electrode (PX) is dry-etched, a chemical reaction with oxygen is caused in the resist material by an oxygen asher and the side surface is evaporated.

As a result, the resist gradually disappears from the side surface, and the electrode is tapered.

As a result, the same effects as in the first embodiment can be obtained in the fourth embodiment.

The fourth embodiment can be combined with the second and third embodiments, and the combination is within the scope of the present invention.

[Embodiment 5] In each of the above embodiments, a counter voltage (CT) for applying an electric field between the pixel electrode (PX) and the liquid crystal layer (LC) in a direction substantially parallel to the substrate is applied to the counter electrode (CT). In an active matrix color liquid crystal display device for supplying a counter voltage (Vcom) from a signal line (CL), at least one of a pixel electrode (PX) and a counter electrode (CT) has a taper angle.

On the other hand, in this embodiment, in order to improve the aperture ratio of a pixel, an active matrix type color scheme in which a counter voltage (Vcom) is supplied from a neighboring scanning signal line (GL) to a counter electrode (CT). In a liquid crystal display device,
At least one of the pixel electrode (PX) and the counter electrode (CT) has a taper angle.

The structure of this embodiment (the structure of the electrode or
The electrode material and the like are the same as those in the first embodiment except for the following items.
Alternatively, it is the same as the second embodiment.

Next, the present embodiment will be described focusing on the differences from the above-described first or second embodiment.

FIG. 23 is a plan view showing one pixel of an active matrix type color liquid crystal display device according to another embodiment (Embodiment 5) of the present invention and its periphery.

[0293] As shown in FIG. 23 contiguous, in the liquid crystal display device of this embodiment, the gate electrode (GT), and, to-direction conductive <br/> electrode (CT) is run scanning signal Line and (GL) And are integrally configured.

[0294] Here, versus counter electrode (CT) is connected to the preceding line of scanning signal lines (GL).

The cross section of the pixel in this embodiment (FIG. 1)
20 is the same as FIG. 3 or FIG.

FIG. 24 is a diagram showing an equalizing circuit of the display matrix section (AR) and its peripheral circuits in the liquid crystal display device of this embodiment.

FIG. 24 is also a circuit diagram, but is drawn corresponding to the actual geometric arrangement.

In FIG. 24, AR indicates a display matrix section (matrix array) in which a plurality of pixels are two-dimensionally arranged.

In FIG. 24, PX is a pixel electrode, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively.

GL is a scanning signal line, and y0, y2, y
3,..., End indicate the order of the scanning timing.

A scanning signal line (GL) is connected to a vertical scanning circuit (V)
, And the video signal line (DL) is connected to the video signal drive circuit (H).

The circuit (SUP) includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CRT (cathode ray tube) from a host (upper processing unit).
Is a circuit including a circuit for exchanging information for use with information for a (TFT) liquid crystal display device.

FIGS. 25A and 25B are diagrams showing driving waveforms at the time of driving in the liquid crystal display device of this embodiment. FIGS. 25A and 25B show (i-1) -th and (i-th) driving waveforms, respectively. ) -Th gate signal (scan signal voltage) (VG) supplied to the scan signal line (GL).

In FIG. 25, (i) is an even number,
Accordingly, the (i-1) th scanning signal line (GL) is an odd-numbered scanning signal line (GL), and the (i) -th scanning signal line (GL) is an even-numbered scanning signal line (GL). Is shown.

FIG. 25C shows a video signal line (D
FIG. 25D shows the video signal voltage (VD) applied to the pixel electrode (PX) in the pixel of (i) row and (j) column. )
FIG. 25 (e) shows the voltage (VLC) applied to the liquid crystal layer (LC) of the pixel at (i) row and (j) column.

In the driving method of the liquid crystal display device of this embodiment, since the counter voltage (Vcom) must be applied from the scanning signal line (GL) to the counter electrode (CT), the driving voltage is supplied to the scanning signal line (GL). The non-selection voltage of the gate voltage (VG) is changed for each frame by a binary rectangular wave of VGLH and VGLM or a binary rectangular wave of VGLM and VGLL.

Further, the change in the non-selection voltage of the gate voltage (VG) supplied to the adjacent scanning signal line (GL) is prevented from being the same.

In the example shown in FIGS. 25A and 25B, the non-selection voltage of the gate voltage (VG) supplied to the (i-1) th scanning signal line (GL) is an odd frame. , VG
The LM and VGLL binary values are changed by VGLH and VGLM binary values in even frames, and the non-selection voltage of the gate voltage (VG) supplied to the (i) th scanning signal line (GL) is an odd value. In the frame, VGLH, VGLM binary, in the even frame, VGLM,
VGLL is changed by two values.

In this case, the center potential of VGLH and VGLM is V
The center potential of GL1, VGLM and VGLL is VGL2, and the amplitude values of VGLH and VGLM, and the amplitude values of VGLM and VGLL are equal to 2VB.

As described above, also in the fifth embodiment, it is possible to obtain the same effect as in the first embodiment or the second embodiment.

[Embodiment 6] In this embodiment, a pixel electrode (PX) and a counter electrode (CT) are formed in the same step as in Embodiment 3 in the same manner as in Embodiment 3 so that both of them are simultaneously formed. Are given the same taper angles as those of the third and fifth embodiments except for the following items.

Next, the present embodiment will be described with a focus on differences from the third and fifth embodiments.

FIG. 26 is a plan view showing one pixel of an active matrix type color liquid crystal display device according to another embodiment (sixth embodiment) of the present invention and its periphery.

As shown in FIG. 26, in the liquid crystal display device of this embodiment, the gate electrode (GT) is connected to the signal line (G).
And L).

[0315] Further, pairs counter electrode (CT) is connected to the through hole (SH) through the preceding scanning signal lines (GL).

Note that the cross section of the pixel in this embodiment (FIG.
1 is the same as FIG. 22.

In this case, when the scanning signal line (GL) is formed of an aluminum (Al) -based conductive film (g1), the connection between the counter electrode (CT) and the scanning signal line (GL) is established. The anodic oxidation is not performed on the scanning signal line (GL), the same material as the scanning signal line (GL), and those formed in the same process.

In this case, the scanning signal line (GL),
Further, if chromium (Cr) is used as the conductive material formed in the same material and in the same step, it is not necessary to perform anodic oxidation.

As described above, also in the sixth embodiment, it is possible to obtain the same effect as in the third embodiment.

Although the present invention has been described in detail with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.

[0321]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to [0322] the present invention, in an active matrix type liquid crystal display device employing a horizontal electric field method, the electrodes of the pixel electrode and the counter electrode is formed by a taper etching, the taper angle electrodes of the pixel electrode and the counter electrode since so as to impart, when rubbing the alignment film, it is possible to perform the rubbing treatment in the vicinity of the end surface of the electrodes of the pixel electrode and the counter electrode smoothly and reliably.

[0323] Accordingly, since it eliminates the alignment defect region, it is possible to eliminate the light leakage in the vicinity electrodes of the pixel electrode and the counter electrode, significantly improve the contrast ratio,
In addition, it is possible to prevent luminance (contrast) unevenness due to rubbing.

As a result, it is possible to provide a high quality active matrix type liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a plan view showing one pixel of an active matrix type color liquid crystal display device according to an embodiment (Example 1) of the present invention and its periphery.

FIG. 2 is a cross-sectional view showing a cross section taken along line 3-3 shown in FIG.

FIG. 3 is a sectional view showing a section of the thin film transistor (TFT) taken along section line 4-4 shown in FIG. 1;

FIG. 4 shows a storage capacitance (C
It is sectional drawing which shows the cross section of (stg).

FIG. 5 is a plan view illustrating a configuration of a matrix peripheral portion of a display panel (PNL) in the liquid crystal display device according to the first embodiment.

FIG. 6 is a cross-sectional view illustrating a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side in the liquid crystal display device according to the first embodiment.

FIG. 7 is a diagram showing a connection structure from a scanning signal line (GL) of a display matrix portion (AR) to a gate terminal (GTM) which is an external connection terminal thereof in the liquid crystal display device according to the first embodiment.

FIG. 8 is a diagram showing a connection from a video signal line (DL) of a display matrix section (AR) to a drain terminal (DTM) which is an external connection terminal thereof in the liquid crystal display device according to the first embodiment.

FIG. 9 is a diagram showing a connection from a counter voltage signal line (CL) to a counter electrode terminal (CTM) which is an external connection terminal in the liquid crystal display device according to the first embodiment.

FIG. 10 is a diagram illustrating an equalizing circuit of a display matrix unit (AR) and its peripheral circuits in the liquid crystal display device according to the first embodiment.

FIG. 11 is a diagram showing driving waveforms at the time of driving in the liquid crystal display device according to the first embodiment.

FIG. 12 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of steps A to C on the lower transparent glass substrate (SUB1) side in the liquid crystal display device of Example 1.

FIG. 13 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes D to F on the lower transparent glass substrate (SUB1) side in the liquid crystal display device of Example 1.

FIG. 14 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes G to H on the lower transparent glass substrate (SUB1) side in the liquid crystal display device of Example 1.

FIG. 15 is a liquid crystal display panel (PNL) according to the first embodiment.
FIG. 3 is a plan view showing a state where peripheral drive circuits are mounted on the circumstance.

FIG. 16 is a tape carrier package (TCP) in which an integrated circuit chip (CHI) constituting a drive circuit in the liquid crystal display device according to the first embodiment is mounted on a flexible wiring board.
FIG. 4 is a cross-sectional view showing a cross-sectional structure of FIG.

FIG. 17 shows a tape carrier package (TCP) in the liquid crystal display device according to the first embodiment and a liquid crystal display panel (PNL).
FIG. 3 is a cross-sectional view of a main part showing a state where the terminal is connected to a scanning signal circuit terminal (GTM).

FIG. 18 is an exploded perspective view of a liquid crystal display module in the liquid crystal display device according to the first embodiment.

FIG. 19 is a diagram showing a relationship among a direction of an applied electric field, a rubbing direction, and a transmission axis of a polarizing plate in the liquid crystal display device of Example 1.

20 is a cross-sectional view illustrating a cross section of a pixel (a cross section taken along line 3-3 in FIG. 1) in an active matrix color liquid crystal display device according to another embodiment (Example 2) of the present invention.

FIG. 21 is a plan view showing one pixel of an active matrix type color liquid crystal display device according to another embodiment (third embodiment) of the present invention and the periphery thereof.

FIG. 22 is a sectional view of a pixel taken along section line 3-3 shown in FIG. 21;

FIG. 23 is a plan view showing one pixel of an active matrix type color liquid crystal display device according to another embodiment (Embodiment 5) of the present invention and its periphery.

FIG. 24 is a diagram illustrating an equalizing circuit of a display matrix unit (AR) and its peripheral circuits in the liquid crystal display device according to the fifth embodiment.

FIG. 25 is a diagram showing driving waveforms at the time of driving in the liquid crystal display device of Example 5.

FIG. 26 is a plan view showing one pixel of an active matrix type color liquid crystal display device according to another embodiment (sixth embodiment) of the present invention and its periphery.

[Explanation of symbols]

SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line, CL: counter voltage signal line, PX: pixel electrode, C
T: counter electrode, GI: insulating film, GT: gate electrode, AS
... i-type semiconductor layer, SD: source or drain electrode, ORI: alignment film, POL: polarizing plate, OC: overcoat film, PSV: protective film, BM: light shielding film, FIL: color filter, LC: liquid crystal layer, TFT: thin film transistor, g, d: conductive film, Cstg: storage capacitor, AOF: anodized film, AO: anodized mask, GTM: gate terminal, DTM: drain terminal, CB: common bus line, C
TM: Counter electrode terminal, SHD: Shield case, PNL
... a liquid crystal display panel, SPB ... light diffusion plate, LCB ... light guide, BL ... backlight fluorescent tube, LCA ... backlight case, RM ... reflection plate.

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Kazuhiko Yanagawa 3300 Hayano Mobara-shi, Chiba Pref.Electronic Device Division (72) Inventor Masahiro Yanai 3300 Hayano Mobara-shi Chiba Pref. Within the Device Division (72) Nobutake Konishi 3300 Hayano, Mobara City, Chiba Pref. Electronic Device Division, Hitachi, Ltd. (56) References JP-A-6-222397 (JP, A) JP-A-7-225400 (JP) JP-A-7-244297 (JP, A) JP-A-4-346434 (JP, A) JP-A-5-21430 (JP, A) JP-A-59-29289 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1343 G02F 1/1362

Claims (2)

(57) [Claims] 1. A pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a plurality of active elements formed in a matrix on the one substrate, and each connected to the plurality of active elements. A plurality of pixel electrodes, and a plurality of opposing electrodes formed on one of the pair of substrates and applying an electric field substantially parallel to the substrate surface to the liquid crystal layer between the pixel electrodes. In the active matrix type liquid crystal display device, the counter electrode has a counter voltage signal line extending in a first direction.
And the pixel electrode, the counter electrode, and the counter voltage signal line.
Is on the one substrate on which the active element is formed
In it is formed in the same layer, an active matrix type liquid crystal display device, wherein the angle between the side surface and the substrate surface of the electrodes of the pixel electrode and the counter electrode is less than 90 degrees than 0 degrees. 2. The active matrix liquid crystal display device according to claim 1, wherein an angle between a side surface of at least one of the pixel electrode and the counter electrode and a substrate surface is 45 degrees.